1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
13 #include <dt-structs.h>
16 #include <dm/devres.h>
18 #include <linux/clk-provider.h>
19 #include <linux/err.h>
21 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
23 return (const struct clk_ops *)dev->driver->ops;
26 #if CONFIG_IS_ENABLED(OF_CONTROL)
27 # if CONFIG_IS_ENABLED(OF_PLATDATA)
28 int clk_get_by_index_platdata(struct udevice *dev, int index,
29 struct phandle_1_arg *cells, struct clk *clk)
35 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
38 clk->id = cells[0].arg[0];
43 static int clk_of_xlate_default(struct clk *clk,
44 struct ofnode_phandle_args *args)
46 debug("%s(clk=%p)\n", __func__, clk);
48 if (args->args_count > 1) {
49 debug("Invaild args_count: %d\n", args->args_count);
54 clk->id = args->args[0];
63 static int clk_get_by_index_tail(int ret, ofnode node,
64 struct ofnode_phandle_args *args,
65 const char *list_name, int index,
68 struct udevice *dev_clk;
69 const struct clk_ops *ops;
76 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
78 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
85 ops = clk_dev_ops(dev_clk);
88 ret = ops->of_xlate(clk, args);
90 ret = clk_of_xlate_default(clk, args);
92 debug("of_xlate() failed: %d\n", ret);
96 return clk_request(dev_clk, clk);
98 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
99 __func__, ofnode_get_name(node), list_name, index, ret);
103 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
104 int index, struct clk *clk)
107 struct ofnode_phandle_args args;
109 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
114 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
117 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
123 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
127 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
129 struct ofnode_phandle_args args;
132 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
135 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
139 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
141 struct ofnode_phandle_args args;
144 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
147 return clk_get_by_index_tail(ret, node, &args, "clocks",
151 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
153 int i, ret, err, count;
157 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
161 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
165 for (i = 0; i < count; i++) {
166 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
176 err = clk_release_all(bulk->clks, bulk->count);
178 debug("%s: could release all clocks for %p\n",
184 static int clk_set_default_parents(struct udevice *dev, int stage)
186 struct clk clk, parent_clk;
191 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
193 if (num_parents < 0) {
194 debug("%s: could not read assigned-clock-parents for %p\n",
199 for (index = 0; index < num_parents; index++) {
200 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
202 /* If -ENOENT, this is a no-op entry */
207 debug("%s: could not get parent clock %d for %s\n",
208 __func__, index, dev_read_name(dev));
212 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
215 debug("%s: could not get assigned clock %d for %s\n",
216 __func__, index, dev_read_name(dev));
220 /* This is clk provider device trying to reparent itself
221 * It cannot be done right now but need to wait after the
224 if (stage == 0 && clk.dev == dev)
227 if (stage > 0 && clk.dev != dev)
228 /* do not setup twice the parent clocks */
231 ret = clk_set_parent(&clk, &parent_clk);
233 * Not all drivers may support clock-reparenting (as of now).
234 * Ignore errors due to this.
240 debug("%s: failed to reparent clock %d for %s\n",
241 __func__, index, dev_read_name(dev));
249 static int clk_set_default_rates(struct udevice *dev, int stage)
258 size = dev_read_size(dev, "assigned-clock-rates");
262 num_rates = size / sizeof(u32);
263 rates = calloc(num_rates, sizeof(u32));
267 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
271 for (index = 0; index < num_rates; index++) {
272 /* If 0 is passed, this is a no-op */
276 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
279 debug("%s: could not get assigned clock %d for %s\n",
280 __func__, index, dev_read_name(dev));
284 /* This is clk provider device trying to program itself
285 * It cannot be done right now but need to wait after the
288 if (stage == 0 && clk.dev == dev)
291 if (stage > 0 && clk.dev != dev)
292 /* do not setup twice the parent clocks */
295 ret = clk_set_rate(&clk, rates[index]);
298 debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
299 __func__, index, clk.id, dev_read_name(dev));
309 int clk_set_defaults(struct udevice *dev, int stage)
313 if (!dev_of_valid(dev))
316 /* If this not in SPL and pre-reloc state, don't take any action. */
317 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
320 debug("%s(%s)\n", __func__, dev_read_name(dev));
322 ret = clk_set_default_parents(dev, stage);
326 ret = clk_set_default_rates(dev, stage);
333 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
337 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
340 index = dev_read_stringlist_search(dev, "clock-names", name);
342 debug("fdt_stringlist_search() failed: %d\n", index);
346 return clk_get_by_index(dev, index, clk);
348 # endif /* OF_PLATDATA */
350 int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
354 debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
355 ofnode_get_name(node), name, clk);
358 index = ofnode_stringlist_search(node, "clock-names", name);
360 debug("fdt_stringlist_search() failed: %d\n", index);
364 return clk_get_by_index_nodev(node, index, clk);
367 int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
371 ret = clk_get_by_name_nodev(node, name, clk);
378 int clk_release_all(struct clk *clk, int count)
382 for (i = 0; i < count; i++) {
383 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
385 /* check if clock has been previously requested */
389 ret = clk_disable(&clk[i]);
390 if (ret && ret != -ENOSYS)
393 ret = clk_free(&clk[i]);
394 if (ret && ret != -ENOSYS)
401 #endif /* OF_CONTROL */
403 int clk_request(struct udevice *dev, struct clk *clk)
405 const struct clk_ops *ops;
407 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
410 ops = clk_dev_ops(dev);
417 return ops->request(clk);
420 int clk_free(struct clk *clk)
422 const struct clk_ops *ops;
424 debug("%s(clk=%p)\n", __func__, clk);
427 ops = clk_dev_ops(clk->dev);
432 return ops->rfree(clk);
435 ulong clk_get_rate(struct clk *clk)
437 const struct clk_ops *ops;
439 debug("%s(clk=%p)\n", __func__, clk);
442 ops = clk_dev_ops(clk->dev);
447 return ops->get_rate(clk);
450 struct clk *clk_get_parent(struct clk *clk)
452 struct udevice *pdev;
455 debug("%s(clk=%p)\n", __func__, clk);
459 pdev = dev_get_parent(clk->dev);
460 pclk = dev_get_clk_ptr(pdev);
462 return ERR_PTR(-ENODEV);
467 long long clk_get_parent_rate(struct clk *clk)
469 const struct clk_ops *ops;
472 debug("%s(clk=%p)\n", __func__, clk);
476 pclk = clk_get_parent(clk);
480 ops = clk_dev_ops(pclk->dev);
484 /* Read the 'rate' if not already set or if proper flag set*/
485 if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
486 pclk->rate = clk_get_rate(pclk);
491 ulong clk_set_rate(struct clk *clk, ulong rate)
493 const struct clk_ops *ops;
495 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
498 ops = clk_dev_ops(clk->dev);
503 return ops->set_rate(clk, rate);
506 int clk_set_parent(struct clk *clk, struct clk *parent)
508 const struct clk_ops *ops;
510 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
513 ops = clk_dev_ops(clk->dev);
515 if (!ops->set_parent)
518 return ops->set_parent(clk, parent);
521 int clk_enable(struct clk *clk)
523 const struct clk_ops *ops;
524 struct clk *clkp = NULL;
527 debug("%s(clk=%p)\n", __func__, clk);
530 ops = clk_dev_ops(clk->dev);
532 if (CONFIG_IS_ENABLED(CLK_CCF)) {
533 /* Take id 0 as a non-valid clk, such as dummy */
534 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
535 if (clkp->enable_count) {
536 clkp->enable_count++;
539 if (clkp->dev->parent &&
540 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
541 ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
543 printf("Enable %s failed\n",
544 clkp->dev->parent->name);
551 ret = ops->enable(clk);
553 printf("Enable %s failed\n", clk->dev->name);
558 clkp->enable_count++;
562 return ops->enable(clk);
568 int clk_enable_bulk(struct clk_bulk *bulk)
572 for (i = 0; i < bulk->count; i++) {
573 ret = clk_enable(&bulk->clks[i]);
574 if (ret < 0 && ret != -ENOSYS)
581 int clk_disable(struct clk *clk)
583 const struct clk_ops *ops;
584 struct clk *clkp = NULL;
587 debug("%s(clk=%p)\n", __func__, clk);
590 ops = clk_dev_ops(clk->dev);
592 if (CONFIG_IS_ENABLED(CLK_CCF)) {
593 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
594 if (clkp->enable_count == 0) {
595 printf("clk %s already disabled\n",
600 if (--clkp->enable_count > 0)
605 ret = ops->disable(clk);
610 if (clkp && clkp->dev->parent &&
611 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
612 ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
614 printf("Disable %s failed\n",
615 clkp->dev->parent->name);
623 return ops->disable(clk);
629 int clk_disable_bulk(struct clk_bulk *bulk)
633 for (i = 0; i < bulk->count; i++) {
634 ret = clk_disable(&bulk->clks[i]);
635 if (ret < 0 && ret != -ENOSYS)
642 int clk_get_by_id(ulong id, struct clk **clkp)
648 ret = uclass_get(UCLASS_CLK, &uc);
652 uclass_foreach_dev(dev, uc) {
653 struct clk *clk = dev_get_clk_ptr(dev);
655 if (clk && clk->id == id) {
664 bool clk_is_match(const struct clk *p, const struct clk *q)
666 /* trivial case: identical struct clk's or both NULL */
670 /* trivial case #2: on the clk pointer is NULL */
674 /* same device, id and data */
675 if (p->dev == q->dev && p->id == q->id && p->data == q->data)
681 static void devm_clk_release(struct udevice *dev, void *res)
686 static int devm_clk_match(struct udevice *dev, void *res, void *data)
691 struct clk *devm_clk_get(struct udevice *dev, const char *id)
696 clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
698 return ERR_PTR(-ENOMEM);
700 rc = clk_get_by_name(dev, id, clk);
704 devres_add(dev, clk);
708 struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
710 struct clk *clk = devm_clk_get(dev, id);
712 if (PTR_ERR(clk) == -ENODATA)
718 void devm_clk_put(struct udevice *dev, struct clk *clk)
725 rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
729 int clk_uclass_post_probe(struct udevice *dev)
732 * when a clock provider is probed. Call clk_set_defaults()
733 * also after the device is probed. This takes care of cases
734 * where the DT is used to setup default parents and rates
735 * using assigned-clocks
737 clk_set_defaults(dev, 1);
742 UCLASS_DRIVER(clk) = {
745 .post_probe = clk_uclass_post_probe,