1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
16 #include <linux/clk-provider.h>
18 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
20 return (const struct clk_ops *)dev->driver->ops;
23 #if CONFIG_IS_ENABLED(OF_CONTROL)
24 # if CONFIG_IS_ENABLED(OF_PLATDATA)
25 int clk_get_by_index_platdata(struct udevice *dev, int index,
26 struct phandle_1_arg *cells, struct clk *clk)
32 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
35 clk->id = cells[0].arg[0];
40 static int clk_of_xlate_default(struct clk *clk,
41 struct ofnode_phandle_args *args)
43 debug("%s(clk=%p)\n", __func__, clk);
45 if (args->args_count > 1) {
46 debug("Invaild args_count: %d\n", args->args_count);
51 clk->id = args->args[0];
60 static int clk_get_by_index_tail(int ret, ofnode node,
61 struct ofnode_phandle_args *args,
62 const char *list_name, int index,
65 struct udevice *dev_clk;
66 const struct clk_ops *ops;
73 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
75 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
82 ops = clk_dev_ops(dev_clk);
85 ret = ops->of_xlate(clk, args);
87 ret = clk_of_xlate_default(clk, args);
89 debug("of_xlate() failed: %d\n", ret);
93 return clk_request(dev_clk, clk);
95 debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
96 __func__, ofnode_get_name(node), list_name, index, ret);
100 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
101 int index, struct clk *clk)
104 struct ofnode_phandle_args args;
106 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
111 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
114 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
120 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
124 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
126 struct ofnode_phandle_args args;
129 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
132 return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
136 int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
138 struct ofnode_phandle_args args;
141 ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
144 return clk_get_by_index_tail(ret, node, &args, "clocks",
148 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
150 int i, ret, err, count;
154 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
158 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
162 for (i = 0; i < count; i++) {
163 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
173 err = clk_release_all(bulk->clks, bulk->count);
175 debug("%s: could release all clocks for %p\n",
181 static int clk_set_default_parents(struct udevice *dev, int stage)
183 struct clk clk, parent_clk;
188 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
190 if (num_parents < 0) {
191 debug("%s: could not read assigned-clock-parents for %p\n",
196 for (index = 0; index < num_parents; index++) {
197 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
199 /* If -ENOENT, this is a no-op entry */
204 debug("%s: could not get parent clock %d for %s\n",
205 __func__, index, dev_read_name(dev));
209 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
212 debug("%s: could not get assigned clock %d for %s\n",
213 __func__, index, dev_read_name(dev));
217 /* This is clk provider device trying to reparent itself
218 * It cannot be done right now but need to wait after the
221 if (stage == 0 && clk.dev == dev)
224 if (stage > 0 && clk.dev != dev)
225 /* do not setup twice the parent clocks */
228 ret = clk_set_parent(&clk, &parent_clk);
230 * Not all drivers may support clock-reparenting (as of now).
231 * Ignore errors due to this.
237 debug("%s: failed to reparent clock %d for %s\n",
238 __func__, index, dev_read_name(dev));
246 static int clk_set_default_rates(struct udevice *dev, int stage)
255 size = dev_read_size(dev, "assigned-clock-rates");
259 num_rates = size / sizeof(u32);
260 rates = calloc(num_rates, sizeof(u32));
264 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
268 for (index = 0; index < num_rates; index++) {
269 /* If 0 is passed, this is a no-op */
273 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
276 debug("%s: could not get assigned clock %d for %s\n",
277 __func__, index, dev_read_name(dev));
281 /* This is clk provider device trying to program itself
282 * It cannot be done right now but need to wait after the
285 if (stage == 0 && clk.dev == dev)
288 if (stage > 0 && clk.dev != dev)
289 /* do not setup twice the parent clocks */
292 ret = clk_set_rate(&clk, rates[index]);
295 debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
296 __func__, index, clk.id, dev_read_name(dev));
306 int clk_set_defaults(struct udevice *dev, int stage)
310 if (!dev_of_valid(dev))
313 /* If this not in SPL and pre-reloc state, don't take any action. */
314 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
317 debug("%s(%s)\n", __func__, dev_read_name(dev));
319 ret = clk_set_default_parents(dev, stage);
323 ret = clk_set_default_rates(dev, stage);
329 # endif /* OF_PLATDATA */
331 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
335 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
338 index = dev_read_stringlist_search(dev, "clock-names", name);
340 debug("fdt_stringlist_search() failed: %d\n", index);
344 return clk_get_by_index(dev, index, clk);
347 int clk_release_all(struct clk *clk, int count)
351 for (i = 0; i < count; i++) {
352 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
354 /* check if clock has been previously requested */
358 ret = clk_disable(&clk[i]);
359 if (ret && ret != -ENOSYS)
362 ret = clk_free(&clk[i]);
363 if (ret && ret != -ENOSYS)
370 #endif /* OF_CONTROL */
372 int clk_request(struct udevice *dev, struct clk *clk)
374 const struct clk_ops *ops;
376 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
379 ops = clk_dev_ops(dev);
386 return ops->request(clk);
389 int clk_free(struct clk *clk)
391 const struct clk_ops *ops;
393 debug("%s(clk=%p)\n", __func__, clk);
396 ops = clk_dev_ops(clk->dev);
401 return ops->free(clk);
404 ulong clk_get_rate(struct clk *clk)
406 const struct clk_ops *ops;
408 debug("%s(clk=%p)\n", __func__, clk);
411 ops = clk_dev_ops(clk->dev);
416 return ops->get_rate(clk);
419 struct clk *clk_get_parent(struct clk *clk)
421 struct udevice *pdev;
424 debug("%s(clk=%p)\n", __func__, clk);
428 pdev = dev_get_parent(clk->dev);
429 pclk = dev_get_clk_ptr(pdev);
431 return ERR_PTR(-ENODEV);
436 long long clk_get_parent_rate(struct clk *clk)
438 const struct clk_ops *ops;
441 debug("%s(clk=%p)\n", __func__, clk);
445 pclk = clk_get_parent(clk);
449 ops = clk_dev_ops(pclk->dev);
453 /* Read the 'rate' if not already set or if proper flag set*/
454 if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
455 pclk->rate = clk_get_rate(pclk);
460 ulong clk_set_rate(struct clk *clk, ulong rate)
462 const struct clk_ops *ops;
464 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
467 ops = clk_dev_ops(clk->dev);
472 return ops->set_rate(clk, rate);
475 int clk_set_parent(struct clk *clk, struct clk *parent)
477 const struct clk_ops *ops;
479 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
482 ops = clk_dev_ops(clk->dev);
484 if (!ops->set_parent)
487 return ops->set_parent(clk, parent);
490 int clk_enable(struct clk *clk)
492 const struct clk_ops *ops;
493 struct clk *clkp = NULL;
496 debug("%s(clk=%p)\n", __func__, clk);
499 ops = clk_dev_ops(clk->dev);
501 if (CONFIG_IS_ENABLED(CLK_CCF)) {
502 /* Take id 0 as a non-valid clk, such as dummy */
503 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
504 if (clkp->enable_count) {
505 clkp->enable_count++;
508 if (clkp->dev->parent &&
509 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
510 ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
512 printf("Enable %s failed\n",
513 clkp->dev->parent->name);
520 ret = ops->enable(clk);
522 printf("Enable %s failed\n", clk->dev->name);
527 clkp->enable_count++;
531 return ops->enable(clk);
537 int clk_enable_bulk(struct clk_bulk *bulk)
541 for (i = 0; i < bulk->count; i++) {
542 ret = clk_enable(&bulk->clks[i]);
543 if (ret < 0 && ret != -ENOSYS)
550 int clk_disable(struct clk *clk)
552 const struct clk_ops *ops;
553 struct clk *clkp = NULL;
556 debug("%s(clk=%p)\n", __func__, clk);
559 ops = clk_dev_ops(clk->dev);
561 if (CONFIG_IS_ENABLED(CLK_CCF)) {
562 if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
563 if (clkp->enable_count == 0) {
564 printf("clk %s already disabled\n",
569 if (--clkp->enable_count > 0)
574 ret = ops->disable(clk);
579 if (clkp && clkp->dev->parent &&
580 device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
581 ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
583 printf("Disable %s failed\n",
584 clkp->dev->parent->name);
592 return ops->disable(clk);
598 int clk_disable_bulk(struct clk_bulk *bulk)
602 for (i = 0; i < bulk->count; i++) {
603 ret = clk_disable(&bulk->clks[i]);
604 if (ret < 0 && ret != -ENOSYS)
611 int clk_get_by_id(ulong id, struct clk **clkp)
617 ret = uclass_get(UCLASS_CLK, &uc);
621 uclass_foreach_dev(dev, uc) {
622 struct clk *clk = dev_get_clk_ptr(dev);
624 if (clk && clk->id == id) {
633 bool clk_is_match(const struct clk *p, const struct clk *q)
635 /* trivial case: identical struct clk's or both NULL */
639 /* trivial case #2: on the clk pointer is NULL */
643 /* same device, id and data */
644 if (p->dev == q->dev && p->id == q->id && p->data == q->data)
650 static void devm_clk_release(struct udevice *dev, void *res)
655 static int devm_clk_match(struct udevice *dev, void *res, void *data)
660 struct clk *devm_clk_get(struct udevice *dev, const char *id)
665 clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
667 return ERR_PTR(-ENOMEM);
669 rc = clk_get_by_name(dev, id, clk);
673 devres_add(dev, clk);
677 struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
679 struct clk *clk = devm_clk_get(dev, id);
681 if (PTR_ERR(clk) == -ENODATA)
687 void devm_clk_put(struct udevice *dev, struct clk *clk)
694 rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
698 int clk_uclass_post_probe(struct udevice *dev)
701 * when a clock provider is probed. Call clk_set_defaults()
702 * also after the device is probed. This takes care of cases
703 * where the DT is used to setup default parents and rates
704 * using assigned-clocks
706 clk_set_defaults(dev, 1);
711 UCLASS_DRIVER(clk) = {
714 .post_probe = clk_uclass_post_probe,