arm: socfpga: Enable all FPGA config support for Arria 10
[platform/kernel/u-boot.git] / drivers / clk / clk-uclass.c
1 /*
2  * Copyright (C) 2015 Google, Inc
3  * Written by Simon Glass <sjg@chromium.org>
4  * Copyright (c) 2016, NVIDIA CORPORATION.
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <common.h>
10 #include <clk.h>
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14 #include <errno.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
19 {
20         return (struct clk_ops *)dev->driver->ops;
21 }
22
23 #if CONFIG_IS_ENABLED(OF_CONTROL)
24 # if CONFIG_IS_ENABLED(OF_PLATDATA)
25 int clk_get_by_index_platdata(struct udevice *dev, int index,
26                               struct phandle_2_cell *cells, struct clk *clk)
27 {
28         int ret;
29
30         if (index != 0)
31                 return -ENOSYS;
32         ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
33         if (ret)
34                 return ret;
35         clk->id = cells[0].id;
36
37         return 0;
38 }
39 # else
40 static int clk_of_xlate_default(struct clk *clk,
41                                 struct ofnode_phandle_args *args)
42 {
43         debug("%s(clk=%p)\n", __func__, clk);
44
45         if (args->args_count > 1) {
46                 debug("Invaild args_count: %d\n", args->args_count);
47                 return -EINVAL;
48         }
49
50         if (args->args_count)
51                 clk->id = args->args[0];
52         else
53                 clk->id = 0;
54
55         return 0;
56 }
57
58 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
59 {
60         int ret;
61         struct ofnode_phandle_args args;
62         struct udevice *dev_clk;
63         struct clk_ops *ops;
64
65         debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
66
67         assert(clk);
68         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
69                                           index, &args);
70         if (ret) {
71                 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
72                       __func__, ret);
73                 return ret;
74         }
75
76         ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
77         if (ret) {
78                 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
79                       __func__, ret);
80                 return ret;
81         }
82
83         clk->dev = dev_clk;
84
85         ops = clk_dev_ops(dev_clk);
86
87         if (ops->of_xlate)
88                 ret = ops->of_xlate(clk, &args);
89         else
90                 ret = clk_of_xlate_default(clk, &args);
91         if (ret) {
92                 debug("of_xlate() failed: %d\n", ret);
93                 return ret;
94         }
95
96         return clk_request(dev_clk, clk);
97 }
98 # endif /* OF_PLATDATA */
99
100 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
101 {
102         int index;
103
104         debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
105
106         index = dev_read_stringlist_search(dev, "clock-names", name);
107         if (index < 0) {
108                 debug("fdt_stringlist_search() failed: %d\n", index);
109                 return index;
110         }
111
112         return clk_get_by_index(dev, index, clk);
113 }
114 #endif /* OF_CONTROL */
115
116 int clk_request(struct udevice *dev, struct clk *clk)
117 {
118         struct clk_ops *ops = clk_dev_ops(dev);
119
120         debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
121
122         clk->dev = dev;
123
124         if (!ops->request)
125                 return 0;
126
127         return ops->request(clk);
128 }
129
130 int clk_free(struct clk *clk)
131 {
132         struct clk_ops *ops = clk_dev_ops(clk->dev);
133
134         debug("%s(clk=%p)\n", __func__, clk);
135
136         if (!ops->free)
137                 return 0;
138
139         return ops->free(clk);
140 }
141
142 ulong clk_get_rate(struct clk *clk)
143 {
144         struct clk_ops *ops = clk_dev_ops(clk->dev);
145
146         debug("%s(clk=%p)\n", __func__, clk);
147
148         if (!ops->get_rate)
149                 return -ENOSYS;
150
151         return ops->get_rate(clk);
152 }
153
154 ulong clk_set_rate(struct clk *clk, ulong rate)
155 {
156         struct clk_ops *ops = clk_dev_ops(clk->dev);
157
158         debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
159
160         if (!ops->set_rate)
161                 return -ENOSYS;
162
163         return ops->set_rate(clk, rate);
164 }
165
166 int clk_enable(struct clk *clk)
167 {
168         struct clk_ops *ops = clk_dev_ops(clk->dev);
169
170         debug("%s(clk=%p)\n", __func__, clk);
171
172         if (!ops->enable)
173                 return -ENOSYS;
174
175         return ops->enable(clk);
176 }
177
178 int clk_disable(struct clk *clk)
179 {
180         struct clk_ops *ops = clk_dev_ops(clk->dev);
181
182         debug("%s(clk=%p)\n", __func__, clk);
183
184         if (!ops->disable)
185                 return -ENOSYS;
186
187         return ops->disable(clk);
188 }
189
190 UCLASS_DRIVER(clk) = {
191         .id             = UCLASS_CLK,
192         .name           = "clk",
193 };