1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
5 * Copyright (c) 2016, NVIDIA CORPORATION.
6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
11 #include <clk-uclass.h>
14 #include <dt-structs.h>
17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
19 return (const struct clk_ops *)dev->driver->ops;
22 #if CONFIG_IS_ENABLED(OF_CONTROL)
23 # if CONFIG_IS_ENABLED(OF_PLATDATA)
24 int clk_get_by_index_platdata(struct udevice *dev, int index,
25 struct phandle_1_arg *cells, struct clk *clk)
31 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
34 clk->id = cells[0].arg[0];
39 static int clk_of_xlate_default(struct clk *clk,
40 struct ofnode_phandle_args *args)
42 debug("%s(clk=%p)\n", __func__, clk);
44 if (args->args_count > 1) {
45 debug("Invaild args_count: %d\n", args->args_count);
50 clk->id = args->args[0];
57 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
58 int index, struct clk *clk)
61 struct ofnode_phandle_args args;
62 struct udevice *dev_clk;
63 const struct clk_ops *ops;
65 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
70 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
73 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
78 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
80 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
87 ops = clk_dev_ops(dev_clk);
90 ret = ops->of_xlate(clk, &args);
92 ret = clk_of_xlate_default(clk, &args);
94 debug("of_xlate() failed: %d\n", ret);
98 return clk_request(dev_clk, clk);
101 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
103 return clk_get_by_indexed_prop(dev, "clocks", index, clk);
106 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
108 int i, ret, err, count;
112 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
116 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
120 for (i = 0; i < count; i++) {
121 ret = clk_get_by_index(dev, i, &bulk->clks[i]);
131 err = clk_release_all(bulk->clks, bulk->count);
133 debug("%s: could release all clocks for %p\n",
139 static int clk_set_default_parents(struct udevice *dev)
141 struct clk clk, parent_clk;
146 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
148 if (num_parents < 0) {
149 debug("%s: could not read assigned-clock-parents for %p\n",
154 for (index = 0; index < num_parents; index++) {
155 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
158 debug("%s: could not get parent clock %d for %s\n",
159 __func__, index, dev_read_name(dev));
163 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
166 debug("%s: could not get assigned clock %d for %s\n",
167 __func__, index, dev_read_name(dev));
171 ret = clk_set_parent(&clk, &parent_clk);
174 * Not all drivers may support clock-reparenting (as of now).
175 * Ignore errors due to this.
181 debug("%s: failed to reparent clock %d for %s\n",
182 __func__, index, dev_read_name(dev));
190 static int clk_set_default_rates(struct udevice *dev)
199 size = dev_read_size(dev, "assigned-clock-rates");
203 num_rates = size / sizeof(u32);
204 rates = calloc(num_rates, sizeof(u32));
208 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
212 for (index = 0; index < num_rates; index++) {
213 ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
216 debug("%s: could not get assigned clock %d for %s\n",
217 __func__, index, dev_read_name(dev));
221 ret = clk_set_rate(&clk, rates[index]);
223 debug("%s: failed to set rate on clock %d for %s\n",
224 __func__, index, dev_read_name(dev));
234 int clk_set_defaults(struct udevice *dev)
238 /* If this is running pre-reloc state, don't take any action. */
239 if (!(gd->flags & GD_FLG_RELOC))
242 debug("%s(%s)\n", __func__, dev_read_name(dev));
244 ret = clk_set_default_parents(dev);
248 ret = clk_set_default_rates(dev);
254 # endif /* OF_PLATDATA */
256 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
260 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
263 index = dev_read_stringlist_search(dev, "clock-names", name);
265 debug("fdt_stringlist_search() failed: %d\n", index);
269 return clk_get_by_index(dev, index, clk);
272 int clk_release_all(struct clk *clk, int count)
276 for (i = 0; i < count; i++) {
277 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
279 /* check if clock has been previously requested */
283 ret = clk_disable(&clk[i]);
284 if (ret && ret != -ENOSYS)
287 ret = clk_free(&clk[i]);
288 if (ret && ret != -ENOSYS)
295 #endif /* OF_CONTROL */
297 int clk_request(struct udevice *dev, struct clk *clk)
299 const struct clk_ops *ops = clk_dev_ops(dev);
301 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
308 return ops->request(clk);
311 int clk_free(struct clk *clk)
313 const struct clk_ops *ops = clk_dev_ops(clk->dev);
315 debug("%s(clk=%p)\n", __func__, clk);
320 return ops->free(clk);
323 ulong clk_get_rate(struct clk *clk)
325 const struct clk_ops *ops = clk_dev_ops(clk->dev);
327 debug("%s(clk=%p)\n", __func__, clk);
332 return ops->get_rate(clk);
335 ulong clk_set_rate(struct clk *clk, ulong rate)
337 const struct clk_ops *ops = clk_dev_ops(clk->dev);
339 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
344 return ops->set_rate(clk, rate);
347 int clk_set_parent(struct clk *clk, struct clk *parent)
349 const struct clk_ops *ops = clk_dev_ops(clk->dev);
351 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
353 if (!ops->set_parent)
356 return ops->set_parent(clk, parent);
359 int clk_enable(struct clk *clk)
361 const struct clk_ops *ops = clk_dev_ops(clk->dev);
363 debug("%s(clk=%p)\n", __func__, clk);
368 return ops->enable(clk);
371 int clk_enable_bulk(struct clk_bulk *bulk)
375 for (i = 0; i < bulk->count; i++) {
376 ret = clk_enable(&bulk->clks[i]);
377 if (ret < 0 && ret != -ENOSYS)
384 int clk_disable(struct clk *clk)
386 const struct clk_ops *ops = clk_dev_ops(clk->dev);
388 debug("%s(clk=%p)\n", __func__, clk);
393 return ops->disable(clk);
396 int clk_disable_bulk(struct clk_bulk *bulk)
400 for (i = 0; i < bulk->count; i++) {
401 ret = clk_disable(&bulk->clks[i]);
402 if (ret < 0 && ret != -ENOSYS)
409 UCLASS_DRIVER(clk) = {