drivers/clk/clk-stm32mp1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
   5  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reset-controller.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20
  21 #include <dt-bindings/clock/stm32mp1-clks.h>
  22
  23 static DEFINE_SPINLOCK(rlock);
  24
  25 #define RCC_OCENSETR            0x0C
  26 #define RCC_HSICFGR             0x18
  27 #define RCC_RDLSICR             0x144
  28 #define RCC_PLL1CR              0x80
  29 #define RCC_PLL1CFGR1           0x84
  30 #define RCC_PLL1CFGR2           0x88
  31 #define RCC_PLL2CR              0x94
  32 #define RCC_PLL2CFGR1           0x98
  33 #define RCC_PLL2CFGR2           0x9C
  34 #define RCC_PLL3CR              0x880
  35 #define RCC_PLL3CFGR1           0x884
  36 #define RCC_PLL3CFGR2           0x888
  37 #define RCC_PLL4CR              0x894
  38 #define RCC_PLL4CFGR1           0x898
  39 #define RCC_PLL4CFGR2           0x89C
  40 #define RCC_APB1ENSETR          0xA00
  41 #define RCC_APB2ENSETR          0xA08
  42 #define RCC_APB3ENSETR          0xA10
  43 #define RCC_APB4ENSETR          0x200
  44 #define RCC_APB5ENSETR          0x208
  45 #define RCC_AHB2ENSETR          0xA18
  46 #define RCC_AHB3ENSETR          0xA20
  47 #define RCC_AHB4ENSETR          0xA28
  48 #define RCC_AHB5ENSETR          0x210
  49 #define RCC_AHB6ENSETR          0x218
  50 #define RCC_AHB6LPENSETR        0x318
  51 #define RCC_RCK12SELR           0x28
  52 #define RCC_RCK3SELR            0x820
  53 #define RCC_RCK4SELR            0x824
  54 #define RCC_MPCKSELR            0x20
  55 #define RCC_ASSCKSELR           0x24
  56 #define RCC_MSSCKSELR           0x48
  57 #define RCC_SPI6CKSELR          0xC4
  58 #define RCC_SDMMC12CKSELR       0x8F4
  59 #define RCC_SDMMC3CKSELR        0x8F8
  60 #define RCC_FMCCKSELR           0x904
  61 #define RCC_I2C46CKSELR         0xC0
  62 #define RCC_I2C12CKSELR         0x8C0
  63 #define RCC_I2C35CKSELR         0x8C4
  64 #define RCC_UART1CKSELR         0xC8
  65 #define RCC_QSPICKSELR          0x900
  66 #define RCC_ETHCKSELR           0x8FC
  67 #define RCC_RNG1CKSELR          0xCC
  68 #define RCC_RNG2CKSELR          0x920
  69 #define RCC_GPUCKSELR           0x938
  70 #define RCC_USBCKSELR           0x91C
  71 #define RCC_STGENCKSELR         0xD4
  72 #define RCC_SPDIFCKSELR         0x914
  73 #define RCC_SPI2S1CKSELR        0x8D8
  74 #define RCC_SPI2S23CKSELR       0x8DC
  75 #define RCC_SPI2S45CKSELR       0x8E0
  76 #define RCC_CECCKSELR           0x918
  77 #define RCC_LPTIM1CKSELR        0x934
  78 #define RCC_LPTIM23CKSELR       0x930
  79 #define RCC_LPTIM45CKSELR       0x92C
  80 #define RCC_UART24CKSELR        0x8E8
  81 #define RCC_UART35CKSELR        0x8EC
  82 #define RCC_UART6CKSELR         0x8E4
  83 #define RCC_UART78CKSELR        0x8F0
  84 #define RCC_FDCANCKSELR         0x90C
  85 #define RCC_SAI1CKSELR          0x8C8
  86 #define RCC_SAI2CKSELR          0x8CC
  87 #define RCC_SAI3CKSELR          0x8D0
  88 #define RCC_SAI4CKSELR          0x8D4
  89 #define RCC_ADCCKSELR           0x928
  90 #define RCC_MPCKDIVR            0x2C
  91 #define RCC_DSICKSELR           0x924
  92 #define RCC_CPERCKSELR          0xD0
  93 #define RCC_MCO1CFGR            0x800
  94 #define RCC_MCO2CFGR            0x804
  95 #define RCC_BDCR                0x140
  96 #define RCC_AXIDIVR             0x30
  97 #define RCC_MCUDIVR             0x830
  98 #define RCC_APB1DIVR            0x834
  99 #define RCC_APB2DIVR            0x838
 100 #define RCC_APB3DIVR            0x83C
 101 #define RCC_APB4DIVR            0x3C
 102 #define RCC_APB5DIVR            0x40
 103 #define RCC_TIMG1PRER           0x828
 104 #define RCC_TIMG2PRER           0x82C
 105 #define RCC_RTCDIVR             0x44
 106 #define RCC_DBGCFGR             0x80C
 107
 108 #define RCC_CLR 0x4
 109
 110 static const char * const ref12_parents[] = {
 111         "ck_hsi", "ck_hse"
 112 };
 113
 114 static const char * const ref3_parents[] = {
 115         "ck_hsi", "ck_hse", "ck_csi"
 116 };
 117
 118 static const char * const ref4_parents[] = {
 119         "ck_hsi", "ck_hse", "ck_csi"
 120 };
 121
 122 static const char * const cpu_src[] = {
 123         "ck_hsi", "ck_hse", "pll1_p"
 124 };
 125
 126 static const char * const axi_src[] = {
 127         "ck_hsi", "ck_hse", "pll2_p"
 128 };
 129
 130 static const char * const per_src[] = {
 131         "ck_hsi", "ck_csi", "ck_hse"
 132 };
 133
 134 static const char * const mcu_src[] = {
 135         "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
 136 };
 137
 138 static const char * const sdmmc12_src[] = {
 139         "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
 140 };
 141
 142 static const char * const sdmmc3_src[] = {
 143         "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
 144 };
 145
 146 static const char * const fmc_src[] = {
 147         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 148 };
 149
 150 static const char * const qspi_src[] = {
 151         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 152 };
 153
 154 static const char * const eth_src[] = {
 155         "pll4_p", "pll3_q"
 156 };
 157
 158 static const char * const rng_src[] = {
 159         "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
 160 };
 161
 162 static const char * const usbphy_src[] = {
 163         "ck_hse", "pll4_r", "clk-hse-div2"
 164 };
 165
 166 static const char * const usbo_src[] = {
 167         "pll4_r", "ck_usbo_48m"
 168 };
 169
 170 static const char * const stgen_src[] = {
 171         "ck_hsi", "ck_hse"
 172 };
 173
 174 static const char * const spdif_src[] = {
 175         "pll4_p", "pll3_q", "ck_hsi"
 176 };
 177
 178 static const char * const spi123_src[] = {
 179         "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 180 };
 181
 182 static const char * const spi45_src[] = {
 183         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 184 };
 185
 186 static const char * const spi6_src[] = {
 187         "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
 188 };
 189
 190 static const char * const cec_src[] = {
 191         "ck_lse", "ck_lsi", "ck_csi"
 192 };
 193
 194 static const char * const i2c12_src[] = {
 195         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 196 };
 197
 198 static const char * const i2c35_src[] = {
 199         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 200 };
 201
 202 static const char * const i2c46_src[] = {
 203         "pclk5", "pll3_q", "ck_hsi", "ck_csi"
 204 };
 205
 206 static const char * const lptim1_src[] = {
 207         "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 208 };
 209
 210 static const char * const lptim23_src[] = {
 211         "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
 212 };
 213
 214 static const char * const lptim45_src[] = {
 215         "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 216 };
 217
 218 static const char * const usart1_src[] = {
 219         "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 220 };
 221
 222 static const char * const usart234578_src[] = {
 223         "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 224 };
 225
 226 static const char * const usart6_src[] = {
 227         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 228 };
 229
 230 static const char * const fdcan_src[] = {
 231         "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 232 };
 233
 234 static const char * const sai_src[] = {
 235         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 236 };
 237
 238 static const char * const sai2_src[] = {
 239         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 240 };
 241
 242 static const char * const adc12_src[] = {
 243         "pll4_r", "ck_per", "pll3_q"
 244 };
 245
 246 static const char * const dsi_src[] = {
 247         "ck_dsi_phy", "pll4_p"
 248 };
 249
 250 static const char * const rtc_src[] = {
 251         "off", "ck_lse", "ck_lsi", "ck_hse"
 252 };
 253
 254 static const char * const mco1_src[] = {
 255         "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
 256 };
 257
 258 static const char * const mco2_src[] = {
 259         "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
 260 };
 261
 262 static const char * const ck_trace_src[] = {
 263         "ck_axi"
 264 };
 265
 266 static const struct clk_div_table axi_div_table[] = {
 267         { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
 268         { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
 269         { 0 },
 270 };
 271
 272 static const struct clk_div_table mcu_div_table[] = {
 273         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 274         { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
 275         { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
 276         { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
 277         { 0 },
 278 };
 279
 280 static const struct clk_div_table apb_div_table[] = {
 281         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 282         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 283         { 0 },
 284 };
 285
 286 static const struct clk_div_table ck_trace_div_table[] = {
 287         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 288         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 289         { 0 },
 290 };
 291
 292 #define MAX_MUX_CLK 2
 293
 294 struct stm32_mmux {
 295         u8 nbr_clk;
 296         struct clk_hw *hws[MAX_MUX_CLK];
 297 };
 298
 299 struct stm32_clk_mmux {
 300         struct clk_mux mux;
 301         struct stm32_mmux *mmux;
 302 };
 303
 304 struct stm32_mgate {
 305         u8 nbr_clk;
 306         u32 flag;
 307 };
 308
 309 struct stm32_clk_mgate {
 310         struct clk_gate gate;
 311         struct stm32_mgate *mgate;
 312         u32 mask;
 313 };
 314
 315 struct clock_config {
 316         u32 id;
 317         const char *name;
 318         const char *parent_name;
 319         const char * const *parent_names;
 320         int num_parents;
 321         unsigned long flags;
 322         void *cfg;
 323         struct clk_hw * (*func)(struct device *dev,
 324                                 struct clk_hw_onecell_data *clk_data,
 325                                 void __iomem *base, spinlock_t *lock,
 326                                 const struct clock_config *cfg);
 327 };
 328
 329 #define NO_ID ~0
 330
 331 struct gate_cfg {
 332         u32 reg_off;
 333         u8 bit_idx;
 334         u8 gate_flags;
 335 };
 336
 337 struct fixed_factor_cfg {
 338         unsigned int mult;
 339         unsigned int div;
 340 };
 341
 342 struct div_cfg {
 343         u32 reg_off;
 344         u8 shift;
 345         u8 width;
 346         u8 div_flags;
 347         const struct clk_div_table *table;
 348 };
 349
 350 struct mux_cfg {
 351         u32 reg_off;
 352         u8 shift;
 353         u8 width;
 354         u8 mux_flags;
 355         u32 *table;
 356 };
 357
 358 struct stm32_gate_cfg {
 359         struct gate_cfg         *gate;
 360         struct stm32_mgate      *mgate;
 361         const struct clk_ops    *ops;
 362 };
 363
 364 struct stm32_div_cfg {
 365         struct div_cfg          *div;
 366         const struct clk_ops    *ops;
 367 };
 368
 369 struct stm32_mux_cfg {
 370         struct mux_cfg          *mux;
 371         struct stm32_mmux       *mmux;
 372         const struct clk_ops    *ops;
 373 };
 374
 375 /* STM32 Composite clock */
 376 struct stm32_composite_cfg {
 377         const struct stm32_gate_cfg     *gate;
 378         const struct stm32_div_cfg      *div;
 379         const struct stm32_mux_cfg      *mux;
 380 };
 381
 382 static struct clk_hw *
 383 _clk_hw_register_gate(struct device *dev,
 384                       struct clk_hw_onecell_data *clk_data,
 385                       void __iomem *base, spinlock_t *lock,
 386                       const struct clock_config *cfg)
 387 {
 388         struct gate_cfg *gate_cfg = cfg->cfg;
 389
 390         return clk_hw_register_gate(dev,
 391                                     cfg->name,
 392                                     cfg->parent_name,
 393                                     cfg->flags,
 394                                     gate_cfg->reg_off + base,
 395                                     gate_cfg->bit_idx,
 396                                     gate_cfg->gate_flags,
 397                                     lock);
 398 }
 399
 400 static struct clk_hw *
 401 _clk_hw_register_fixed_factor(struct device *dev,
 402                               struct clk_hw_onecell_data *clk_data,
 403                               void __iomem *base, spinlock_t *lock,
 404                               const struct clock_config *cfg)
 405 {
 406         struct fixed_factor_cfg *ff_cfg = cfg->cfg;
 407
 408         return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
 409                                             cfg->flags, ff_cfg->mult,
 410                                             ff_cfg->div);
 411 }
 412
 413 static struct clk_hw *
 414 _clk_hw_register_divider_table(struct device *dev,
 415                                struct clk_hw_onecell_data *clk_data,
 416                                void __iomem *base, spinlock_t *lock,
 417                                const struct clock_config *cfg)
 418 {
 419         struct div_cfg *div_cfg = cfg->cfg;
 420
 421         return clk_hw_register_divider_table(dev,
 422                                              cfg->name,
 423                                              cfg->parent_name,
 424                                              cfg->flags,
 425                                              div_cfg->reg_off + base,
 426                                              div_cfg->shift,
 427                                              div_cfg->width,
 428                                              div_cfg->div_flags,
 429                                              div_cfg->table,
 430                                              lock);
 431 }
 432
 433 static struct clk_hw *
 434 _clk_hw_register_mux(struct device *dev,
 435                      struct clk_hw_onecell_data *clk_data,
 436                      void __iomem *base, spinlock_t *lock,
 437                      const struct clock_config *cfg)
 438 {
 439         struct mux_cfg *mux_cfg = cfg->cfg;
 440
 441         return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
 442                                    cfg->num_parents, cfg->flags,
 443                                    mux_cfg->reg_off + base, mux_cfg->shift,
 444                                    mux_cfg->width, mux_cfg->mux_flags, lock);
 445 }
 446
 447 /* MP1 Gate clock with set & clear registers */
 448
 449 static int mp1_gate_clk_enable(struct clk_hw *hw)
 450 {
 451         if (!clk_gate_ops.is_enabled(hw))
 452                 clk_gate_ops.enable(hw);
 453
 454         return 0;
 455 }
 456
 457 static void mp1_gate_clk_disable(struct clk_hw *hw)
 458 {
 459         struct clk_gate *gate = to_clk_gate(hw);
 460         unsigned long flags = 0;
 461
 462         if (clk_gate_ops.is_enabled(hw)) {
 463                 spin_lock_irqsave(gate->lock, flags);
 464                 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
 465                 spin_unlock_irqrestore(gate->lock, flags);
 466         }
 467 }
 468
 469 static const struct clk_ops mp1_gate_clk_ops = {
 470         .enable         = mp1_gate_clk_enable,
 471         .disable        = mp1_gate_clk_disable,
 472         .is_enabled     = clk_gate_is_enabled,
 473 };
 474
 475 static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
 476                                      const struct stm32_mux_cfg *cfg,
 477                                      spinlock_t *lock)
 478 {
 479         struct stm32_clk_mmux *mmux;
 480         struct clk_mux *mux;
 481         struct clk_hw *mux_hw;
 482
 483         if (cfg->mmux) {
 484                 mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
 485                 if (!mmux)
 486                         return ERR_PTR(-ENOMEM);
 487
 488                 mmux->mux.reg = cfg->mux->reg_off + base;
 489                 mmux->mux.shift = cfg->mux->shift;
 490                 mmux->mux.mask = (1 << cfg->mux->width) - 1;
 491                 mmux->mux.flags = cfg->mux->mux_flags;
 492                 mmux->mux.table = cfg->mux->table;
 493                 mmux->mux.lock = lock;
 494                 mmux->mmux = cfg->mmux;
 495                 mux_hw = &mmux->mux.hw;
 496                 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
 497
 498         } else {
 499                 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 500                 if (!mux)
 501                         return ERR_PTR(-ENOMEM);
 502
 503                 mux->reg = cfg->mux->reg_off + base;
 504                 mux->shift = cfg->mux->shift;
 505                 mux->mask = (1 << cfg->mux->width) - 1;
 506                 mux->flags = cfg->mux->mux_flags;
 507                 mux->table = cfg->mux->table;
 508                 mux->lock = lock;
 509                 mux_hw = &mux->hw;
 510         }
 511
 512         return mux_hw;
 513 }
 514
 515 static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
 516                                      const struct stm32_div_cfg *cfg,
 517                                      spinlock_t *lock)
 518 {
 519         struct clk_divider *div;
 520
 521         div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 522
 523         if (!div)
 524                 return ERR_PTR(-ENOMEM);
 525
 526         div->reg = cfg->div->reg_off + base;
 527         div->shift = cfg->div->shift;
 528         div->width = cfg->div->width;
 529         div->flags = cfg->div->div_flags;
 530         div->table = cfg->div->table;
 531         div->lock = lock;
 532
 533         return &div->hw;
 534 }
 535
 536 static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
 537                                       const struct stm32_gate_cfg *cfg,
 538                                       spinlock_t *lock)
 539 {
 540         struct stm32_clk_mgate *mgate;
 541         struct clk_gate *gate;
 542         struct clk_hw *gate_hw;
 543
 544         if (cfg->mgate) {
 545                 mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
 546                 if (!mgate)
 547                         return ERR_PTR(-ENOMEM);
 548
 549                 mgate->gate.reg = cfg->gate->reg_off + base;
 550                 mgate->gate.bit_idx = cfg->gate->bit_idx;
 551                 mgate->gate.flags = cfg->gate->gate_flags;
 552                 mgate->gate.lock = lock;
 553                 mgate->mask = BIT(cfg->mgate->nbr_clk++);
 554
 555                 mgate->mgate = cfg->mgate;
 556
 557                 gate_hw = &mgate->gate.hw;
 558
 559         } else {
 560                 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
 561                 if (!gate)
 562                         return ERR_PTR(-ENOMEM);
 563
 564                 gate->reg = cfg->gate->reg_off + base;
 565                 gate->bit_idx = cfg->gate->bit_idx;
 566                 gate->flags = cfg->gate->gate_flags;
 567                 gate->lock = lock;
 568
 569                 gate_hw = &gate->hw;
 570         }
 571
 572         return gate_hw;
 573 }
 574
 575 static struct clk_hw *
 576 clk_stm32_register_gate_ops(struct device *dev,
 577                             const char *name,
 578                             const char *parent_name,
 579                             unsigned long flags,
 580                             void __iomem *base,
 581                             const struct stm32_gate_cfg *cfg,
 582                             spinlock_t *lock)
 583 {
 584         struct clk_init_data init = { NULL };
 585         struct clk_hw *hw;
 586         int ret;
 587
 588         init.name = name;
 589         init.parent_names = &parent_name;
 590         init.num_parents = 1;
 591         init.flags = flags;
 592
 593         init.ops = &clk_gate_ops;
 594
 595         if (cfg->ops)
 596                 init.ops = cfg->ops;
 597
 598         hw = _get_stm32_gate(dev, base, cfg, lock);
 599         if (IS_ERR(hw))
 600                 return ERR_PTR(-ENOMEM);
 601
 602         hw->init = &init;
 603
 604         ret = clk_hw_register(dev, hw);
 605         if (ret)
 606                 hw = ERR_PTR(ret);
 607
 608         return hw;
 609 }
 610
 611 static struct clk_hw *
 612 clk_stm32_register_composite(struct device *dev,
 613                              const char *name, const char * const *parent_names,
 614                              int num_parents, void __iomem *base,
 615                              const struct stm32_composite_cfg *cfg,
 616                              unsigned long flags, spinlock_t *lock)
 617 {
 618         const struct clk_ops *mux_ops, *div_ops, *gate_ops;
 619         struct clk_hw *mux_hw, *div_hw, *gate_hw;
 620
 621         mux_hw = NULL;
 622         div_hw = NULL;
 623         gate_hw = NULL;
 624         mux_ops = NULL;
 625         div_ops = NULL;
 626         gate_ops = NULL;
 627
 628         if (cfg->mux) {
 629                 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
 630
 631                 if (!IS_ERR(mux_hw)) {
 632                         mux_ops = &clk_mux_ops;
 633
 634                         if (cfg->mux->ops)
 635                                 mux_ops = cfg->mux->ops;
 636                 }
 637         }
 638
 639         if (cfg->div) {
 640                 div_hw = _get_stm32_div(dev, base, cfg->div, lock);
 641
 642                 if (!IS_ERR(div_hw)) {
 643                         div_ops = &clk_divider_ops;
 644
 645                         if (cfg->div->ops)
 646                                 div_ops = cfg->div->ops;
 647                 }
 648         }
 649
 650         if (cfg->gate) {
 651                 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
 652
 653                 if (!IS_ERR(gate_hw)) {
 654                         gate_ops = &clk_gate_ops;
 655
 656                         if (cfg->gate->ops)
 657                                 gate_ops = cfg->gate->ops;
 658                 }
 659         }
 660
 661         return clk_hw_register_composite(dev, name, parent_names, num_parents,
 662                                        mux_hw, mux_ops, div_hw, div_ops,
 663                                        gate_hw, gate_ops, flags);
 664 }
 665
 666 #define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
 667
 668 static int mp1_mgate_clk_enable(struct clk_hw *hw)
 669 {
 670         struct clk_gate *gate = to_clk_gate(hw);
 671         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 672
 673         clk_mgate->mgate->flag |= clk_mgate->mask;
 674
 675         mp1_gate_clk_enable(hw);
 676
 677         return  0;
 678 }
 679
 680 static void mp1_mgate_clk_disable(struct clk_hw *hw)
 681 {
 682         struct clk_gate *gate = to_clk_gate(hw);
 683         struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
 684
 685         clk_mgate->mgate->flag &= ~clk_mgate->mask;
 686
 687         if (clk_mgate->mgate->flag == 0)
 688                 mp1_gate_clk_disable(hw);
 689 }
 690
 691 static const struct clk_ops mp1_mgate_clk_ops = {
 692         .enable         = mp1_mgate_clk_enable,
 693         .disable        = mp1_mgate_clk_disable,
 694         .is_enabled     = clk_gate_is_enabled,
 695
 696 };
 697
 698 #define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
 699
 700 static u8 clk_mmux_get_parent(struct clk_hw *hw)
 701 {
 702         return clk_mux_ops.get_parent(hw);
 703 }
 704
 705 static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
 706 {
 707         struct clk_mux *mux = to_clk_mux(hw);
 708         struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
 709         struct clk_hw *hwp;
 710         int ret, n;
 711
 712         ret = clk_mux_ops.set_parent(hw, index);
 713         if (ret)
 714                 return ret;
 715
 716         hwp = clk_hw_get_parent(hw);
 717
 718         for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
 719                 if (clk_mmux->mmux->hws[n] != hw)
 720                         clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
 721
 722         return 0;
 723 }
 724
 725 static const struct clk_ops clk_mmux_ops = {
 726         .get_parent     = clk_mmux_get_parent,
 727         .set_parent     = clk_mmux_set_parent,
 728         .determine_rate = __clk_mux_determine_rate,
 729 };
 730
 731 /* STM32 PLL */
 732 struct stm32_pll_obj {
 733         /* lock pll enable/disable registers */
 734         spinlock_t *lock;
 735         void __iomem *reg;
 736         struct clk_hw hw;
 737         struct clk_mux mux;
 738 };
 739
 740 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
 741
 742 #define PLL_ON          BIT(0)
 743 #define PLL_RDY         BIT(1)
 744 #define DIVN_MASK       0x1FF
 745 #define DIVM_MASK       0x3F
 746 #define DIVM_SHIFT      16
 747 #define DIVN_SHIFT      0
 748 #define FRAC_OFFSET     0xC
 749 #define FRAC_MASK       0x1FFF
 750 #define FRAC_SHIFT      3
 751 #define FRACLE          BIT(16)
 752 #define PLL_MUX_SHIFT   0
 753 #define PLL_MUX_MASK    3
 754
 755 static int __pll_is_enabled(struct clk_hw *hw)
 756 {
 757         struct stm32_pll_obj *clk_elem = to_pll(hw);
 758
 759         return readl_relaxed(clk_elem->reg) & PLL_ON;
 760 }
 761
 762 #define TIMEOUT 5
 763
 764 static int pll_enable(struct clk_hw *hw)
 765 {
 766         struct stm32_pll_obj *clk_elem = to_pll(hw);
 767         u32 reg;
 768         unsigned long flags = 0;
 769         unsigned int timeout = TIMEOUT;
 770         int bit_status = 0;
 771
 772         spin_lock_irqsave(clk_elem->lock, flags);
 773
 774         if (__pll_is_enabled(hw))
 775                 goto unlock;
 776
 777         reg = readl_relaxed(clk_elem->reg);
 778         reg |= PLL_ON;
 779         writel_relaxed(reg, clk_elem->reg);
 780
 781         /* We can't use readl_poll_timeout() because we can be blocked if
 782          * someone enables this clock before clocksource changes.
 783          * Only jiffies counter is available. Jiffies are incremented by
 784          * interruptions and enable op does not allow to be interrupted.
 785          */
 786         do {
 787                 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
 788
 789                 if (bit_status)
 790                         udelay(120);
 791
 792         } while (bit_status && --timeout);
 793
 794 unlock:
 795         spin_unlock_irqrestore(clk_elem->lock, flags);
 796
 797         return bit_status;
 798 }
 799
 800 static void pll_disable(struct clk_hw *hw)
 801 {
 802         struct stm32_pll_obj *clk_elem = to_pll(hw);
 803         u32 reg;
 804         unsigned long flags = 0;
 805
 806         spin_lock_irqsave(clk_elem->lock, flags);
 807
 808         reg = readl_relaxed(clk_elem->reg);
 809         reg &= ~PLL_ON;
 810         writel_relaxed(reg, clk_elem->reg);
 811
 812         spin_unlock_irqrestore(clk_elem->lock, flags);
 813 }
 814
 815 static u32 pll_frac_val(struct clk_hw *hw)
 816 {
 817         struct stm32_pll_obj *clk_elem = to_pll(hw);
 818         u32 reg, frac = 0;
 819
 820         reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
 821         if (reg & FRACLE)
 822                 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
 823
 824         return frac;
 825 }
 826
 827 static unsigned long pll_recalc_rate(struct clk_hw *hw,
 828                                      unsigned long parent_rate)
 829 {
 830         struct stm32_pll_obj *clk_elem = to_pll(hw);
 831         u32 reg;
 832         u32 frac, divm, divn;
 833         u64 rate, rate_frac = 0;
 834
 835         reg = readl_relaxed(clk_elem->reg + 4);
 836
 837         divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
 838         divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
 839         rate = (u64)parent_rate * divn;
 840
 841         do_div(rate, divm);
 842
 843         frac = pll_frac_val(hw);
 844         if (frac) {
 845                 rate_frac = (u64)parent_rate * (u64)frac;
 846                 do_div(rate_frac, (divm * 8192));
 847         }
 848
 849         return rate + rate_frac;
 850 }
 851
 852 static int pll_is_enabled(struct clk_hw *hw)
 853 {
 854         struct stm32_pll_obj *clk_elem = to_pll(hw);
 855         unsigned long flags = 0;
 856         int ret;
 857
 858         spin_lock_irqsave(clk_elem->lock, flags);
 859         ret = __pll_is_enabled(hw);
 860         spin_unlock_irqrestore(clk_elem->lock, flags);
 861
 862         return ret;
 863 }
 864
 865 static u8 pll_get_parent(struct clk_hw *hw)
 866 {
 867         struct stm32_pll_obj *clk_elem = to_pll(hw);
 868         struct clk_hw *mux_hw = &clk_elem->mux.hw;
 869
 870         __clk_hw_set_clk(mux_hw, hw);
 871
 872         return clk_mux_ops.get_parent(mux_hw);
 873 }
 874
 875 static const struct clk_ops pll_ops = {
 876         .enable         = pll_enable,
 877         .disable        = pll_disable,
 878         .recalc_rate    = pll_recalc_rate,
 879         .is_enabled     = pll_is_enabled,
 880         .get_parent     = pll_get_parent,
 881 };
 882
 883 static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
 884                                        const char * const *parent_names,
 885                                        int num_parents,
 886                                        void __iomem *reg,
 887                                        void __iomem *mux_reg,
 888                                        unsigned long flags,
 889                                        spinlock_t *lock)
 890 {
 891         struct stm32_pll_obj *element;
 892         struct clk_init_data init;
 893         struct clk_hw *hw;
 894         int err;
 895
 896         element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL);
 897         if (!element)
 898                 return ERR_PTR(-ENOMEM);
 899
 900         init.name = name;
 901         init.ops = &pll_ops;
 902         init.flags = flags;
 903         init.parent_names = parent_names;
 904         init.num_parents = num_parents;
 905
 906         element->mux.lock = lock;
 907         element->mux.reg =  mux_reg;
 908         element->mux.shift = PLL_MUX_SHIFT;
 909         element->mux.mask =  PLL_MUX_MASK;
 910         element->mux.flags =  CLK_MUX_READ_ONLY;
 911         element->mux.reg =  mux_reg;
 912
 913         element->hw.init = &init;
 914         element->reg = reg;
 915         element->lock = lock;
 916
 917         hw = &element->hw;
 918         err = clk_hw_register(dev, hw);
 919
 920         if (err)
 921                 return ERR_PTR(err);
 922
 923         return hw;
 924 }
 925
 926 /* Kernel Timer */
 927 struct timer_cker {
 928         /* lock the kernel output divider register */
 929         spinlock_t *lock;
 930         void __iomem *apbdiv;
 931         void __iomem *timpre;
 932         struct clk_hw hw;
 933 };
 934
 935 #define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
 936
 937 #define APB_DIV_MASK 0x07
 938 #define TIM_PRE_MASK 0x01
 939
 940 static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
 941                                 unsigned long parent_rate)
 942 {
 943         struct timer_cker *tim_ker = to_timer_cker(hw);
 944         u32 prescaler;
 945         unsigned int mult = 0;
 946
 947         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
 948         if (prescaler < 2)
 949                 return 1;
 950
 951         mult = 2;
 952
 953         if (rate / parent_rate >= 4)
 954                 mult = 4;
 955
 956         return mult;
 957 }
 958
 959 static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
 960                                  unsigned long *parent_rate)
 961 {
 962         unsigned long factor = __bestmult(hw, rate, *parent_rate);
 963
 964         return *parent_rate * factor;
 965 }
 966
 967 static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
 968                               unsigned long parent_rate)
 969 {
 970         struct timer_cker *tim_ker = to_timer_cker(hw);
 971         unsigned long flags = 0;
 972         unsigned long factor = __bestmult(hw, rate, parent_rate);
 973         int ret = 0;
 974
 975         spin_lock_irqsave(tim_ker->lock, flags);
 976
 977         switch (factor) {
 978         case 1:
 979                 break;
 980         case 2:
 981                 writel_relaxed(0, tim_ker->timpre);
 982                 break;
 983         case 4:
 984                 writel_relaxed(1, tim_ker->timpre);
 985                 break;
 986         default:
 987                 ret = -EINVAL;
 988         }
 989         spin_unlock_irqrestore(tim_ker->lock, flags);
 990
 991         return ret;
 992 }
 993
 994 static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
 995                                            unsigned long parent_rate)
 996 {
 997         struct timer_cker *tim_ker = to_timer_cker(hw);
 998         u32 prescaler, timpre;
 999         u32 mul;
1000
1001         prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
1002
1003         timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
1004
1005         if (!prescaler)
1006                 return parent_rate;
1007
1008         mul = (timpre + 1) * 2;
1009
1010         return parent_rate * mul;
1011 }
1012
1013 static const struct clk_ops timer_ker_ops = {
1014         .recalc_rate    = timer_ker_recalc_rate,
1015         .round_rate     = timer_ker_round_rate,
1016         .set_rate       = timer_ker_set_rate,
1017
1018 };
1019
1020 static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
1021                                          const char *parent_name,
1022                                          unsigned long flags,
1023                                          void __iomem *apbdiv,
1024                                          void __iomem *timpre,
1025                                          spinlock_t *lock)
1026 {
1027         struct timer_cker *tim_ker;
1028         struct clk_init_data init;
1029         struct clk_hw *hw;
1030         int err;
1031
1032         tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL);
1033         if (!tim_ker)
1034                 return ERR_PTR(-ENOMEM);
1035
1036         init.name = name;
1037         init.ops = &timer_ker_ops;
1038         init.flags = flags;
1039         init.parent_names = &parent_name;
1040         init.num_parents = 1;
1041
1042         tim_ker->hw.init = &init;
1043         tim_ker->lock = lock;
1044         tim_ker->apbdiv = apbdiv;
1045         tim_ker->timpre = timpre;
1046
1047         hw = &tim_ker->hw;
1048         err = clk_hw_register(dev, hw);
1049
1050         if (err)
1051                 return ERR_PTR(err);
1052
1053         return hw;
1054 }
1055
1056 /* The divider of RTC clock concerns only ck_hse clock */
1057 #define HSE_RTC 3
1058
1059 static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
1060                                                  unsigned long parent_rate)
1061 {
1062         if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1063                 return clk_divider_ops.recalc_rate(hw, parent_rate);
1064
1065         return parent_rate;
1066 }
1067
1068 static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
1069                                     unsigned long parent_rate)
1070 {
1071         if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
1072                 return clk_divider_ops.set_rate(hw, rate, parent_rate);
1073
1074         return parent_rate;
1075 }
1076
1077 static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
1078 {
1079         if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC))
1080                 return clk_divider_ops.determine_rate(hw, req);
1081
1082         req->rate = req->best_parent_rate;
1083
1084         return 0;
1085 }
1086
1087 static const struct clk_ops rtc_div_clk_ops = {
1088         .recalc_rate    = clk_divider_rtc_recalc_rate,
1089         .set_rate       = clk_divider_rtc_set_rate,
1090         .determine_rate = clk_divider_rtc_determine_rate
1091 };
1092
1093 struct stm32_pll_cfg {
1094         u32 offset;
1095         u32 muxoff;
1096 };
1097
1098 static struct clk_hw *_clk_register_pll(struct device *dev,
1099                                         struct clk_hw_onecell_data *clk_data,
1100                                         void __iomem *base, spinlock_t *lock,
1101                                         const struct clock_config *cfg)
1102 {
1103         struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1104
1105         return clk_register_pll(dev, cfg->name, cfg->parent_names,
1106                                 cfg->num_parents,
1107                                 base + stm_pll_cfg->offset,
1108                                 base + stm_pll_cfg->muxoff,
1109                                 cfg->flags, lock);
1110 }
1111
1112 struct stm32_cktim_cfg {
1113         u32 offset_apbdiv;
1114         u32 offset_timpre;
1115 };
1116
1117 static struct clk_hw *_clk_register_cktim(struct device *dev,
1118                                           struct clk_hw_onecell_data *clk_data,
1119                                           void __iomem *base, spinlock_t *lock,
1120                                           const struct clock_config *cfg)
1121 {
1122         struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1123
1124         return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1125                                   cktim_cfg->offset_apbdiv + base,
1126                                   cktim_cfg->offset_timpre + base, lock);
1127 }
1128
1129 static struct clk_hw *
1130 _clk_stm32_register_gate(struct device *dev,
1131                          struct clk_hw_onecell_data *clk_data,
1132                          void __iomem *base, spinlock_t *lock,
1133                          const struct clock_config *cfg)
1134 {
1135         return clk_stm32_register_gate_ops(dev,
1136                                     cfg->name,
1137                                     cfg->parent_name,
1138                                     cfg->flags,
1139                                     base,
1140                                     cfg->cfg,
1141                                     lock);
1142 }
1143
1144 static struct clk_hw *
1145 _clk_stm32_register_composite(struct device *dev,
1146                               struct clk_hw_onecell_data *clk_data,
1147                               void __iomem *base, spinlock_t *lock,
1148                               const struct clock_config *cfg)
1149 {
1150         return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1151                                             cfg->num_parents, base, cfg->cfg,
1152                                             cfg->flags, lock);
1153 }
1154
1155 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1156 {\
1157         .id             = _id,\
1158         .name           = _name,\
1159         .parent_name    = _parent,\
1160         .flags          = _flags,\
1161         .cfg            =  &(struct gate_cfg) {\
1162                 .reg_off        = _offset,\
1163                 .bit_idx        = _bit_idx,\
1164                 .gate_flags     = _gate_flags,\
1165         },\
1166         .func           = _clk_hw_register_gate,\
1167 }
1168
1169 #define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1170 {\
1171         .id             = _id,\
1172         .name           = _name,\
1173         .parent_name    = _parent,\
1174         .flags          = _flags,\
1175         .cfg            =  &(struct fixed_factor_cfg) {\
1176                 .mult = _mult,\
1177                 .div = _div,\
1178         },\
1179         .func           = _clk_hw_register_fixed_factor,\
1180 }
1181
1182 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1183                   _div_flags, _div_table)\
1184 {\
1185         .id             = _id,\
1186         .name           = _name,\
1187         .parent_name    = _parent,\
1188         .flags          = _flags,\
1189         .cfg            =  &(struct div_cfg) {\
1190                 .reg_off        = _offset,\
1191                 .shift          = _shift,\
1192                 .width          = _width,\
1193                 .div_flags      = _div_flags,\
1194                 .table          = _div_table,\
1195         },\
1196         .func           = _clk_hw_register_divider_table,\
1197 }
1198
1199 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1200         DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1201                   _div_flags, NULL)
1202
1203 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1204 {\
1205         .id             = _id,\
1206         .name           = _name,\
1207         .parent_names   = _parents,\
1208         .num_parents    = ARRAY_SIZE(_parents),\
1209         .flags          = _flags,\
1210         .cfg            =  &(struct mux_cfg) {\
1211                 .reg_off        = _offset,\
1212                 .shift          = _shift,\
1213                 .width          = _width,\
1214                 .mux_flags      = _mux_flags,\
1215         },\
1216         .func           = _clk_hw_register_mux,\
1217 }
1218
1219 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
1220 {\
1221         .id             = _id,\
1222         .name           = _name,\
1223         .parent_names   = _parents,\
1224         .num_parents    = ARRAY_SIZE(_parents),\
1225         .flags          = CLK_IGNORE_UNUSED | (_flags),\
1226         .cfg            =  &(struct stm32_pll_cfg) {\
1227                 .offset = _offset_p,\
1228                 .muxoff = _offset_mux,\
1229         },\
1230         .func           = _clk_register_pll,\
1231 }
1232
1233 #define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1234 {\
1235         .id             = NO_ID,\
1236         .name           = _name,\
1237         .parent_name    = _parent,\
1238         .flags          = _flags,\
1239         .cfg            =  &(struct stm32_cktim_cfg) {\
1240                 .offset_apbdiv = _offset_apbdiv,\
1241                 .offset_timpre = _offset_timpre,\
1242         },\
1243         .func           = _clk_register_cktim,\
1244 }
1245
1246 #define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1247                   GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1248                            _offset_set, _bit_idx, 0)
1249
1250 /* STM32 GATE */
1251 #define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1252 {\
1253         .id             = _id,\
1254         .name           = _name,\
1255         .parent_name    = _parent,\
1256         .flags          = _flags,\
1257         .cfg            = (struct stm32_gate_cfg *) {_gate},\
1258         .func           = _clk_stm32_register_gate,\
1259 }
1260
1261 #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1262         (&(struct stm32_gate_cfg) {\
1263                 &(struct gate_cfg) {\
1264                         .reg_off        = _gate_offset,\
1265                         .bit_idx        = _gate_bit_idx,\
1266                         .gate_flags     = _gate_flags,\
1267                 },\
1268                 .mgate          = _mgate,\
1269                 .ops            = _ops,\
1270         })
1271
1272 #define _STM32_MGATE(_mgate)\
1273         (&per_gate_cfg[_mgate])
1274
1275 #define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1276         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1277                     NULL, NULL)\
1278
1279 #define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1280         _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1281                     NULL, &mp1_gate_clk_ops)\
1282
1283 #define _MGATE_MP1(_mgate)\
1284         .gate = &per_gate_cfg[_mgate]
1285
1286 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1287         STM32_GATE(_id, _name, _parent, _flags,\
1288                    _GATE_MP1(_offset, _bit_idx, _gate_flags))
1289
1290 #define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1291         STM32_GATE(_id, _name, _parent, _flags,\
1292                    _STM32_MGATE(_mgate))
1293
1294 #define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1295                    _div_flags, _div_table, _ops)\
1296         .div = &(struct stm32_div_cfg) {\
1297                 &(struct div_cfg) {\
1298                         .reg_off        = _div_offset,\
1299                         .shift          = _div_shift,\
1300                         .width          = _div_width,\
1301                         .div_flags      = _div_flags,\
1302                         .table          = _div_table,\
1303                 },\
1304                 .ops            = _ops,\
1305         }
1306
1307 #define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1308         _STM32_DIV(_div_offset, _div_shift, _div_width,\
1309                    _div_flags, _div_table, NULL)\
1310
1311 #define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1312         _STM32_DIV(_div_offset, _div_shift, _div_width,\
1313                    _div_flags, _div_table, &rtc_div_clk_ops)
1314
1315 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1316         .mux = &(struct stm32_mux_cfg) {\
1317                 &(struct mux_cfg) {\
1318                         .reg_off        = _offset,\
1319                         .shift          = _shift,\
1320                         .width          = _width,\
1321                         .mux_flags      = _mux_flags,\
1322                         .table          = NULL,\
1323                 },\
1324                 .mmux           = _mmux,\
1325                 .ops            = _ops,\
1326         }
1327
1328 #define _MUX(_offset, _shift, _width, _mux_flags)\
1329         _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1330
1331 #define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1332
1333 #define PARENT(_parent) ((const char *[]) { _parent})
1334
1335 #define _NO_MUX .mux = NULL
1336 #define _NO_DIV .div = NULL
1337 #define _NO_GATE .gate = NULL
1338
1339 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1340 {\
1341         .id             = _id,\
1342         .name           = _name,\
1343         .parent_names   = _parents,\
1344         .num_parents    = ARRAY_SIZE(_parents),\
1345         .flags          = _flags,\
1346         .cfg            = &(struct stm32_composite_cfg) {\
1347                 _gate,\
1348                 _mux,\
1349                 _div,\
1350         },\
1351         .func           = _clk_stm32_register_composite,\
1352 }
1353
1354 #define PCLK(_id, _name, _parent, _flags, _mgate)\
1355         MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1356
1357 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1358              COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1359                        CLK_SET_RATE_NO_REPARENT | _flags,\
1360                        _MGATE_MP1(_mgate),\
1361                        _MMUX(_mmux),\
1362                        _NO_DIV)
1363
1364 enum {
1365         G_SAI1,
1366         G_SAI2,
1367         G_SAI3,
1368         G_SAI4,
1369         G_SPI1,
1370         G_SPI2,
1371         G_SPI3,
1372         G_SPI4,
1373         G_SPI5,
1374         G_SPI6,
1375         G_SPDIF,
1376         G_I2C1,
1377         G_I2C2,
1378         G_I2C3,
1379         G_I2C4,
1380         G_I2C5,
1381         G_I2C6,
1382         G_USART2,
1383         G_UART4,
1384         G_USART3,
1385         G_UART5,
1386         G_USART1,
1387         G_USART6,
1388         G_UART7,
1389         G_UART8,
1390         G_LPTIM1,
1391         G_LPTIM2,
1392         G_LPTIM3,
1393         G_LPTIM4,
1394         G_LPTIM5,
1395         G_LTDC,
1396         G_DSI,
1397         G_QSPI,
1398         G_FMC,
1399         G_SDMMC1,
1400         G_SDMMC2,
1401         G_SDMMC3,
1402         G_USBO,
1403         G_USBPHY,
1404         G_RNG1,
1405         G_RNG2,
1406         G_FDCAN,
1407         G_DAC12,
1408         G_CEC,
1409         G_ADC12,
1410         G_GPU,
1411         G_STGEN,
1412         G_DFSDM,
1413         G_ADFSDM,
1414         G_TIM2,
1415         G_TIM3,
1416         G_TIM4,
1417         G_TIM5,
1418         G_TIM6,
1419         G_TIM7,
1420         G_TIM12,
1421         G_TIM13,
1422         G_TIM14,
1423         G_MDIO,
1424         G_TIM1,
1425         G_TIM8,
1426         G_TIM15,
1427         G_TIM16,
1428         G_TIM17,
1429         G_SYSCFG,
1430         G_VREF,
1431         G_TMPSENS,
1432         G_PMBCTRL,
1433         G_HDP,
1434         G_IWDG2,
1435         G_STGENRO,
1436         G_DMA1,
1437         G_DMA2,
1438         G_DMAMUX,
1439         G_DCMI,
1440         G_CRYP2,
1441         G_HASH2,
1442         G_CRC2,
1443         G_HSEM,
1444         G_IPCC,
1445         G_GPIOA,
1446         G_GPIOB,
1447         G_GPIOC,
1448         G_GPIOD,
1449         G_GPIOE,
1450         G_GPIOF,
1451         G_GPIOG,
1452         G_GPIOH,
1453         G_GPIOI,
1454         G_GPIOJ,
1455         G_GPIOK,
1456         G_MDMA,
1457         G_ETHCK,
1458         G_ETHTX,
1459         G_ETHRX,
1460         G_ETHMAC,
1461         G_CRC1,
1462         G_USBH,
1463         G_ETHSTP,
1464         G_RTCAPB,
1465         G_TZC1,
1466         G_TZC2,
1467         G_TZPC,
1468         G_IWDG1,
1469         G_BSEC,
1470         G_GPIOZ,
1471         G_CRYP1,
1472         G_HASH1,
1473         G_BKPSRAM,
1474         G_DDRPERFM,
1475
1476         G_LAST
1477 };
1478
1479 static struct stm32_mgate mp1_mgate[G_LAST];
1480
1481 #define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1482                _mgate, _ops)\
1483         [_id] = {\
1484                 &(struct gate_cfg) {\
1485                         .reg_off        = _gate_offset,\
1486                         .bit_idx        = _gate_bit_idx,\
1487                         .gate_flags     = _gate_flags,\
1488                 },\
1489                 .mgate          = _mgate,\
1490                 .ops            = _ops,\
1491         }
1492
1493 #define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1494         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1495                NULL, &mp1_gate_clk_ops)
1496
1497 #define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1498         _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1499                &mp1_mgate[_id], &mp1_mgate_clk_ops)
1500
1501 /* Peripheral gates */
1502 static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1503         /* Multi gates */
1504         K_GATE(G_MDIO,          RCC_APB1ENSETR, 31, 0),
1505         K_MGATE(G_DAC12,        RCC_APB1ENSETR, 29, 0),
1506         K_MGATE(G_CEC,          RCC_APB1ENSETR, 27, 0),
1507         K_MGATE(G_SPDIF,        RCC_APB1ENSETR, 26, 0),
1508         K_MGATE(G_I2C5,         RCC_APB1ENSETR, 24, 0),
1509         K_MGATE(G_I2C3,         RCC_APB1ENSETR, 23, 0),
1510         K_MGATE(G_I2C2,         RCC_APB1ENSETR, 22, 0),
1511         K_MGATE(G_I2C1,         RCC_APB1ENSETR, 21, 0),
1512         K_MGATE(G_UART8,        RCC_APB1ENSETR, 19, 0),
1513         K_MGATE(G_UART7,        RCC_APB1ENSETR, 18, 0),
1514         K_MGATE(G_UART5,        RCC_APB1ENSETR, 17, 0),
1515         K_MGATE(G_UART4,        RCC_APB1ENSETR, 16, 0),
1516         K_MGATE(G_USART3,       RCC_APB1ENSETR, 15, 0),
1517         K_MGATE(G_USART2,       RCC_APB1ENSETR, 14, 0),
1518         K_MGATE(G_SPI3,         RCC_APB1ENSETR, 12, 0),
1519         K_MGATE(G_SPI2,         RCC_APB1ENSETR, 11, 0),
1520         K_MGATE(G_LPTIM1,       RCC_APB1ENSETR, 9, 0),
1521         K_GATE(G_TIM14,         RCC_APB1ENSETR, 8, 0),
1522         K_GATE(G_TIM13,         RCC_APB1ENSETR, 7, 0),
1523         K_GATE(G_TIM12,         RCC_APB1ENSETR, 6, 0),
1524         K_GATE(G_TIM7,          RCC_APB1ENSETR, 5, 0),
1525         K_GATE(G_TIM6,          RCC_APB1ENSETR, 4, 0),
1526         K_GATE(G_TIM5,          RCC_APB1ENSETR, 3, 0),
1527         K_GATE(G_TIM4,          RCC_APB1ENSETR, 2, 0),
1528         K_GATE(G_TIM3,          RCC_APB1ENSETR, 1, 0),
1529         K_GATE(G_TIM2,          RCC_APB1ENSETR, 0, 0),
1530
1531         K_MGATE(G_FDCAN,        RCC_APB2ENSETR, 24, 0),
1532         K_GATE(G_ADFSDM,        RCC_APB2ENSETR, 21, 0),
1533         K_GATE(G_DFSDM,         RCC_APB2ENSETR, 20, 0),
1534         K_MGATE(G_SAI3,         RCC_APB2ENSETR, 18, 0),
1535         K_MGATE(G_SAI2,         RCC_APB2ENSETR, 17, 0),
1536         K_MGATE(G_SAI1,         RCC_APB2ENSETR, 16, 0),
1537         K_MGATE(G_USART6,       RCC_APB2ENSETR, 13, 0),
1538         K_MGATE(G_SPI5,         RCC_APB2ENSETR, 10, 0),
1539         K_MGATE(G_SPI4,         RCC_APB2ENSETR, 9, 0),
1540         K_MGATE(G_SPI1,         RCC_APB2ENSETR, 8, 0),
1541         K_GATE(G_TIM17,         RCC_APB2ENSETR, 4, 0),
1542         K_GATE(G_TIM16,         RCC_APB2ENSETR, 3, 0),
1543         K_GATE(G_TIM15,         RCC_APB2ENSETR, 2, 0),
1544         K_GATE(G_TIM8,          RCC_APB2ENSETR, 1, 0),
1545         K_GATE(G_TIM1,          RCC_APB2ENSETR, 0, 0),
1546
1547         K_GATE(G_HDP,           RCC_APB3ENSETR, 20, 0),
1548         K_GATE(G_PMBCTRL,       RCC_APB3ENSETR, 17, 0),
1549         K_GATE(G_TMPSENS,       RCC_APB3ENSETR, 16, 0),
1550         K_GATE(G_VREF,          RCC_APB3ENSETR, 13, 0),
1551         K_GATE(G_SYSCFG,        RCC_APB3ENSETR, 11, 0),
1552         K_MGATE(G_SAI4,         RCC_APB3ENSETR, 8, 0),
1553         K_MGATE(G_LPTIM5,       RCC_APB3ENSETR, 3, 0),
1554         K_MGATE(G_LPTIM4,       RCC_APB3ENSETR, 2, 0),
1555         K_MGATE(G_LPTIM3,       RCC_APB3ENSETR, 1, 0),
1556         K_MGATE(G_LPTIM2,       RCC_APB3ENSETR, 0, 0),
1557
1558         K_GATE(G_STGENRO,       RCC_APB4ENSETR, 20, 0),
1559         K_MGATE(G_USBPHY,       RCC_APB4ENSETR, 16, 0),
1560         K_GATE(G_IWDG2,         RCC_APB4ENSETR, 15, 0),
1561         K_GATE(G_DDRPERFM,      RCC_APB4ENSETR, 8, 0),
1562         K_MGATE(G_DSI,          RCC_APB4ENSETR, 4, 0),
1563         K_MGATE(G_LTDC,         RCC_APB4ENSETR, 0, 0),
1564
1565         K_GATE(G_STGEN,         RCC_APB5ENSETR, 20, 0),
1566         K_GATE(G_BSEC,          RCC_APB5ENSETR, 16, 0),
1567         K_GATE(G_IWDG1,         RCC_APB5ENSETR, 15, 0),
1568         K_GATE(G_TZPC,          RCC_APB5ENSETR, 13, 0),
1569         K_GATE(G_TZC2,          RCC_APB5ENSETR, 12, 0),
1570         K_GATE(G_TZC1,          RCC_APB5ENSETR, 11, 0),
1571         K_GATE(G_RTCAPB,        RCC_APB5ENSETR, 8, 0),
1572         K_MGATE(G_USART1,       RCC_APB5ENSETR, 4, 0),
1573         K_MGATE(G_I2C6,         RCC_APB5ENSETR, 3, 0),
1574         K_MGATE(G_I2C4,         RCC_APB5ENSETR, 2, 0),
1575         K_MGATE(G_SPI6,         RCC_APB5ENSETR, 0, 0),
1576
1577         K_MGATE(G_SDMMC3,       RCC_AHB2ENSETR, 16, 0),
1578         K_MGATE(G_USBO,         RCC_AHB2ENSETR, 8, 0),
1579         K_MGATE(G_ADC12,        RCC_AHB2ENSETR, 5, 0),
1580         K_GATE(G_DMAMUX,        RCC_AHB2ENSETR, 2, 0),
1581         K_GATE(G_DMA2,          RCC_AHB2ENSETR, 1, 0),
1582         K_GATE(G_DMA1,          RCC_AHB2ENSETR, 0, 0),
1583
1584         K_GATE(G_IPCC,          RCC_AHB3ENSETR, 12, 0),
1585         K_GATE(G_HSEM,          RCC_AHB3ENSETR, 11, 0),
1586         K_GATE(G_CRC2,          RCC_AHB3ENSETR, 7, 0),
1587         K_MGATE(G_RNG2,         RCC_AHB3ENSETR, 6, 0),
1588         K_GATE(G_HASH2,         RCC_AHB3ENSETR, 5, 0),
1589         K_GATE(G_CRYP2,         RCC_AHB3ENSETR, 4, 0),
1590         K_GATE(G_DCMI,          RCC_AHB3ENSETR, 0, 0),
1591
1592         K_GATE(G_GPIOK,         RCC_AHB4ENSETR, 10, 0),
1593         K_GATE(G_GPIOJ,         RCC_AHB4ENSETR, 9, 0),
1594         K_GATE(G_GPIOI,         RCC_AHB4ENSETR, 8, 0),
1595         K_GATE(G_GPIOH,         RCC_AHB4ENSETR, 7, 0),
1596         K_GATE(G_GPIOG,         RCC_AHB4ENSETR, 6, 0),
1597         K_GATE(G_GPIOF,         RCC_AHB4ENSETR, 5, 0),
1598         K_GATE(G_GPIOE,         RCC_AHB4ENSETR, 4, 0),
1599         K_GATE(G_GPIOD,         RCC_AHB4ENSETR, 3, 0),
1600         K_GATE(G_GPIOC,         RCC_AHB4ENSETR, 2, 0),
1601         K_GATE(G_GPIOB,         RCC_AHB4ENSETR, 1, 0),
1602         K_GATE(G_GPIOA,         RCC_AHB4ENSETR, 0, 0),
1603
1604         K_GATE(G_BKPSRAM,       RCC_AHB5ENSETR, 8, 0),
1605         K_MGATE(G_RNG1,         RCC_AHB5ENSETR, 6, 0),
1606         K_GATE(G_HASH1,         RCC_AHB5ENSETR, 5, 0),
1607         K_GATE(G_CRYP1,         RCC_AHB5ENSETR, 4, 0),
1608         K_GATE(G_GPIOZ,         RCC_AHB5ENSETR, 0, 0),
1609
1610         K_GATE(G_USBH,          RCC_AHB6ENSETR, 24, 0),
1611         K_GATE(G_CRC1,          RCC_AHB6ENSETR, 20, 0),
1612         K_MGATE(G_SDMMC2,       RCC_AHB6ENSETR, 17, 0),
1613         K_MGATE(G_SDMMC1,       RCC_AHB6ENSETR, 16, 0),
1614         K_MGATE(G_QSPI,         RCC_AHB6ENSETR, 14, 0),
1615         K_MGATE(G_FMC,          RCC_AHB6ENSETR, 12, 0),
1616         K_GATE(G_ETHMAC,        RCC_AHB6ENSETR, 10, 0),
1617         K_GATE(G_ETHRX,         RCC_AHB6ENSETR, 9, 0),
1618         K_GATE(G_ETHTX,         RCC_AHB6ENSETR, 8, 0),
1619         K_GATE(G_ETHCK,         RCC_AHB6ENSETR, 7, 0),
1620         K_MGATE(G_GPU,          RCC_AHB6ENSETR, 5, 0),
1621         K_GATE(G_MDMA,          RCC_AHB6ENSETR, 0, 0),
1622         K_GATE(G_ETHSTP,        RCC_AHB6LPENSETR, 11, 0),
1623 };
1624
1625 enum {
1626         M_SDMMC12,
1627         M_SDMMC3,
1628         M_FMC,
1629         M_QSPI,
1630         M_RNG1,
1631         M_RNG2,
1632         M_USBPHY,
1633         M_USBO,
1634         M_STGEN,
1635         M_SPDIF,
1636         M_SPI1,
1637         M_SPI23,
1638         M_SPI45,
1639         M_SPI6,
1640         M_CEC,
1641         M_I2C12,
1642         M_I2C35,
1643         M_I2C46,
1644         M_LPTIM1,
1645         M_LPTIM23,
1646         M_LPTIM45,
1647         M_USART1,
1648         M_UART24,
1649         M_UART35,
1650         M_USART6,
1651         M_UART78,
1652         M_SAI1,
1653         M_SAI2,
1654         M_SAI3,
1655         M_SAI4,
1656         M_DSI,
1657         M_FDCAN,
1658         M_ADC12,
1659         M_ETHCK,
1660         M_CKPER,
1661         M_LAST
1662 };
1663
1664 static struct stm32_mmux ker_mux[M_LAST];
1665
1666 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1667         [_id] = {\
1668                 &(struct mux_cfg) {\
1669                         .reg_off        = _offset,\
1670                         .shift          = _shift,\
1671                         .width          = _width,\
1672                         .mux_flags      = _mux_flags,\
1673                         .table          = NULL,\
1674                 },\
1675                 .mmux           = _mmux,\
1676                 .ops            = _ops,\
1677         }
1678
1679 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1680         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1681                         NULL, NULL)
1682
1683 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1684         _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1685                         &ker_mux[_id], &clk_mmux_ops)
1686
1687 static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1688         /* Kernel multi mux */
1689         K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1690         K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1691         K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1692         K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1693         K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1694         K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1695         K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1696         K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1697         K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1698         K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1699         K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1700         K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1701         K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1702
1703         /*  Kernel simple mux */
1704         K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1705         K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1706         K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1707         K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1708         K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1709         K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1710         K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1711         K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1712         K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1713         K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1714         K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1715         K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1716         K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1717         K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1718         K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1719         K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1720         K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1721         K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1722         K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1723         K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1724         K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1725         K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1726 };
1727
1728 static const struct clock_config stm32mp1_clock_cfg[] = {
1729         /*  External / Internal Oscillators */
1730         GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1731         /* ck_csi is used by IO compensation and should be critical */
1732         GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1733                  RCC_OCENSETR, 4, 0),
1734         COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1735                   _GATE_MP1(RCC_OCENSETR, 0, 0),
1736                   _NO_MUX,
1737                   _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
1738                        CLK_DIVIDER_READ_ONLY, NULL)),
1739         GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1740         GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1741
1742         FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1743
1744         /* PLLs */
1745         PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
1746         PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
1747         PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
1748         PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
1749
1750         /* ODF */
1751         COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1752                   _GATE(RCC_PLL1CR, 4, 0),
1753                   _NO_MUX,
1754                   _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1755
1756         COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1757                   _GATE(RCC_PLL2CR, 4, 0),
1758                   _NO_MUX,
1759                   _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1760
1761         COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1762                   _GATE(RCC_PLL2CR, 5, 0),
1763                   _NO_MUX,
1764                   _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1765
1766         COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1767                   _GATE(RCC_PLL2CR, 6, 0),
1768                   _NO_MUX,
1769                   _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1770
1771         COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1772                   _GATE(RCC_PLL3CR, 4, 0),
1773                   _NO_MUX,
1774                   _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1775
1776         COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1777                   _GATE(RCC_PLL3CR, 5, 0),
1778                   _NO_MUX,
1779                   _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1780
1781         COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1782                   _GATE(RCC_PLL3CR, 6, 0),
1783                   _NO_MUX,
1784                   _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1785
1786         COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1787                   _GATE(RCC_PLL4CR, 4, 0),
1788                   _NO_MUX,
1789                   _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1790
1791         COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1792                   _GATE(RCC_PLL4CR, 5, 0),
1793                   _NO_MUX,
1794                   _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1795
1796         COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1797                   _GATE(RCC_PLL4CR, 6, 0),
1798                   _NO_MUX,
1799                   _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1800
1801         /* MUX system clocks */
1802         MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1803             RCC_CPERCKSELR, 0, 2, 0),
1804
1805         MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1806              CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1807
1808         COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1809                    CLK_OPS_PARENT_ENABLE,
1810                    _NO_GATE,
1811                    _MUX(RCC_ASSCKSELR, 0, 2, 0),
1812                    _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1813
1814         COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1815                    CLK_OPS_PARENT_ENABLE,
1816                    _NO_GATE,
1817                    _MUX(RCC_MSSCKSELR, 0, 2, 0),
1818                    _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1819
1820         DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1821                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1822
1823         DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1824                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1825
1826         DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1827                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1828
1829         DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1830                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1831
1832         DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1833                   3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1834
1835         /* Kernel Timers */
1836         STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1837         STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1838
1839         STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1840         STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1841         STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1842         STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1843         STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1844         STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1845         STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1846         STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1847         STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1848         STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1849         STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1850         STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1851         STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1852         STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1853
1854         /* Peripheral clocks */
1855         PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1856         PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1857         PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1858         PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1859         PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1860         PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1861         PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1862         PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1863         PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1864         PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1865         PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1866         PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1867         PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1868         PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1869         PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1870         PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1871         PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1872         PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1873         PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1874         PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1875         PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1876         PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1877         PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1878         PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1879         PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1880         PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1881         PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1882         PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1883         PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1884         PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1885         PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1886         PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1887         PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1888         PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1889         PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1890         PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1891         PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1892         PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1893         PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1894         PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1895         PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1896         PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1897         PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1898         PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1899         PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1900         PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1901         PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1902         PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1903         PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1904         PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1905         PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1906         PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1907         PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1908         PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1909         PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1910         PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1911         PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1912         PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1913         PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1914         PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1915              CLK_IS_CRITICAL, G_RTCAPB),
1916         PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
1917         PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
1918         PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1919         PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1920         PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1921         PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1922         PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1923         PCLK(DMA2, "dma2", "ck_mcu",  0, G_DMA2),
1924         PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1925         PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1926         PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1927         PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1928         PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1929         PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1930         PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1931         PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1932         PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1933         PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1934         PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1935         PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1936         PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1937         PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1938         PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1939         PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1940         PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1941         PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1942         PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1943         PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1944         PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1945         PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1946         PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1947         PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1948         PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1949         PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1950         PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1951         PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1952         PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1953         PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1954         PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
1955         PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1956         PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1957         PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1958         PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1959         PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1960         PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1961         PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1962         PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1963         PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
1964
1965         /* Kernel clocks */
1966         KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1967         KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
1968         KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
1969         KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
1970         KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
1971         KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1972         KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1973         KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1974         KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
1975         KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1976         KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1977         KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
1978         KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
1979         KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
1980         KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
1981         KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
1982         KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
1983         KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
1984         KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
1985         KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
1986         KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
1987         KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
1988         KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
1989         KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
1990         KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
1991         KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
1992         KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
1993         KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
1994         KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
1995         KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
1996         KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
1997         KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
1998         KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
1999         KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
2000         KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
2001         KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
2002         KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
2003         KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
2004         KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
2005         KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
2006         KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
2007         KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
2008         KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
2009         KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
2010         KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
2011         KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
2012
2013         /* Particulary Kernel Clocks (no mux or no gate) */
2014         MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
2015         MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
2016         MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
2017         MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
2018         MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
2019
2020         COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
2021                   CLK_SET_RATE_NO_REPARENT,
2022                   _NO_GATE,
2023                   _MMUX(M_ETHCK),
2024                   _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
2025
2026         /* RTC clock */
2027         COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
2028                   _GATE(RCC_BDCR, 20, 0),
2029                   _MUX(RCC_BDCR, 16, 2, 0),
2030                   _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
2031
2032         /* MCO clocks */
2033         COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
2034                   CLK_SET_RATE_NO_REPARENT,
2035                   _GATE(RCC_MCO1CFGR, 12, 0),
2036                   _MUX(RCC_MCO1CFGR, 0, 3, 0),
2037                   _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
2038
2039         COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
2040                   CLK_SET_RATE_NO_REPARENT,
2041                   _GATE(RCC_MCO2CFGR, 12, 0),
2042                   _MUX(RCC_MCO2CFGR, 0, 3, 0),
2043                   _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
2044
2045         /* Debug clocks */
2046         GATE(CK_DBG, "ck_sys_dbg", "ck_axi", CLK_IGNORE_UNUSED,
2047              RCC_DBGCFGR, 8, 0),
2048
2049         COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
2050                   _GATE(RCC_DBGCFGR, 9, 0),
2051                   _NO_MUX,
2052                   _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
2053 };
2054
2055 static const u32 stm32mp1_clock_secured[] = {
2056         CK_HSE,
2057         CK_HSI,
2058         CK_CSI,
2059         CK_LSI,
2060         CK_LSE,
2061         PLL1,
2062         PLL2,
2063         PLL1_P,
2064         PLL2_P,
2065         PLL2_Q,
2066         PLL2_R,
2067         CK_MPU,
2068         CK_AXI,
2069         SPI6,
2070         I2C4,
2071         I2C6,
2072         USART1,
2073         RTCAPB,
2074         TZC1,
2075         TZC2,
2076         TZPC,
2077         IWDG1,
2078         BSEC,
2079         STGEN,
2080         GPIOZ,
2081         CRYP1,
2082         HASH1,
2083         RNG1,
2084         BKPSRAM,
2085         RNG1_K,
2086         STGEN_K,
2087         SPI6_K,
2088         I2C4_K,
2089         I2C6_K,
2090         USART1_K,
2091         RTC,
2092 };
2093
2094 static bool stm32_check_security(const struct clock_config *cfg)
2095 {
2096         int i;
2097
2098         for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
2099                 if (cfg->id == stm32mp1_clock_secured[i])
2100                         return true;
2101         return false;
2102 }
2103
2104 struct stm32_rcc_match_data {
2105         const struct clock_config *cfg;
2106         unsigned int num;
2107         unsigned int maxbinding;
2108         u32 clear_offset;
2109         bool (*check_security)(const struct clock_config *cfg);
2110 };
2111
2112 static struct stm32_rcc_match_data stm32mp1_data = {
2113         .cfg            = stm32mp1_clock_cfg,
2114         .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2115         .maxbinding     = STM32MP1_LAST_CLK,
2116         .clear_offset   = RCC_CLR,
2117 };
2118
2119 static struct stm32_rcc_match_data stm32mp1_data_secure = {
2120         .cfg            = stm32mp1_clock_cfg,
2121         .num            = ARRAY_SIZE(stm32mp1_clock_cfg),
2122         .maxbinding     = STM32MP1_LAST_CLK,
2123         .clear_offset   = RCC_CLR,
2124         .check_security = &stm32_check_security
2125 };
2126
2127 static const struct of_device_id stm32mp1_match_data[] = {
2128         {
2129                 .compatible = "st,stm32mp1-rcc",
2130                 .data = &stm32mp1_data,
2131         },
2132         {
2133                 .compatible = "st,stm32mp1-rcc-secure",
2134                 .data = &stm32mp1_data_secure,
2135         },
2136         { }
2137 };
2138 MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
2139
2140 static int stm32_register_hw_clk(struct device *dev,
2141                                  struct clk_hw_onecell_data *clk_data,
2142                                  void __iomem *base, spinlock_t *lock,
2143                                  const struct clock_config *cfg)
2144 {
2145         struct clk_hw **hws;
2146         struct clk_hw *hw = ERR_PTR(-ENOENT);
2147
2148         hws = clk_data->hws;
2149
2150         if (cfg->func)
2151                 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2152
2153         if (IS_ERR(hw)) {
2154                 pr_err("Unable to register %s\n", cfg->name);
2155                 return  PTR_ERR(hw);
2156         }
2157
2158         if (cfg->id != NO_ID)
2159                 hws[cfg->id] = hw;
2160
2161         return 0;
2162 }
2163
2164 #define STM32_RESET_ID_MASK GENMASK(15, 0)
2165
2166 struct stm32_reset_data {
2167         /* reset lock */
2168         spinlock_t                      lock;
2169         struct reset_controller_dev     rcdev;
2170         void __iomem                    *membase;
2171         u32                             clear_offset;
2172 };
2173
2174 static inline struct stm32_reset_data *
2175 to_stm32_reset_data(struct reset_controller_dev *rcdev)
2176 {
2177         return container_of(rcdev, struct stm32_reset_data, rcdev);
2178 }
2179
2180 static int stm32_reset_update(struct reset_controller_dev *rcdev,
2181                               unsigned long id, bool assert)
2182 {
2183         struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2184         int reg_width = sizeof(u32);
2185         int bank = id / (reg_width * BITS_PER_BYTE);
2186         int offset = id % (reg_width * BITS_PER_BYTE);
2187
2188         if (data->clear_offset) {
2189                 void __iomem *addr;
2190
2191                 addr = data->membase + (bank * reg_width);
2192                 if (!assert)
2193                         addr += data->clear_offset;
2194
2195                 writel(BIT(offset), addr);
2196
2197         } else {
2198                 unsigned long flags;
2199                 u32 reg;
2200
2201                 spin_lock_irqsave(&data->lock, flags);
2202
2203                 reg = readl(data->membase + (bank * reg_width));
2204
2205                 if (assert)
2206                         reg |= BIT(offset);
2207                 else
2208                         reg &= ~BIT(offset);
2209
2210                 writel(reg, data->membase + (bank * reg_width));
2211
2212                 spin_unlock_irqrestore(&data->lock, flags);
2213         }
2214
2215         return 0;
2216 }
2217
2218 static int stm32_reset_assert(struct reset_controller_dev *rcdev,
2219                               unsigned long id)
2220 {
2221         return stm32_reset_update(rcdev, id, true);
2222 }
2223
2224 static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
2225                                 unsigned long id)
2226 {
2227         return stm32_reset_update(rcdev, id, false);
2228 }
2229
2230 static int stm32_reset_status(struct reset_controller_dev *rcdev,
2231                               unsigned long id)
2232 {
2233         struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
2234         int reg_width = sizeof(u32);
2235         int bank = id / (reg_width * BITS_PER_BYTE);
2236         int offset = id % (reg_width * BITS_PER_BYTE);
2237         u32 reg;
2238
2239         reg = readl(data->membase + (bank * reg_width));
2240
2241         return !!(reg & BIT(offset));
2242 }
2243
2244 static const struct reset_control_ops stm32_reset_ops = {
2245         .assert         = stm32_reset_assert,
2246         .deassert       = stm32_reset_deassert,
2247         .status         = stm32_reset_status,
2248 };
2249
2250 static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
2251                                 const struct of_device_id *match)
2252 {
2253         const struct stm32_rcc_match_data *data = match->data;
2254         struct stm32_reset_data *reset_data = NULL;
2255
2256         data = match->data;
2257
2258         reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
2259         if (!reset_data)
2260                 return -ENOMEM;
2261
2262         spin_lock_init(&reset_data->lock);
2263         reset_data->membase = base;
2264         reset_data->rcdev.owner = THIS_MODULE;
2265         reset_data->rcdev.ops = &stm32_reset_ops;
2266         reset_data->rcdev.of_node = dev_of_node(dev);
2267         reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
2268         reset_data->clear_offset = data->clear_offset;
2269
2270         return reset_controller_register(&reset_data->rcdev);
2271 }
2272
2273 static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
2274                                 const struct of_device_id *match)
2275 {
2276         const struct stm32_rcc_match_data *data = match->data;
2277         struct clk_hw_onecell_data *clk_data;
2278         struct clk_hw **hws;
2279         int err, n, max_binding;
2280
2281         max_binding =  data->maxbinding;
2282
2283         clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
2284                                 GFP_KERNEL);
2285         if (!clk_data)
2286                 return -ENOMEM;
2287
2288         clk_data->num = max_binding;
2289
2290         hws = clk_data->hws;
2291
2292         for (n = 0; n < max_binding; n++)
2293                 hws[n] = ERR_PTR(-ENOENT);
2294
2295         for (n = 0; n < data->num; n++) {
2296                 if (data->check_security && data->check_security(&data->cfg[n]))
2297                         continue;
2298
2299                 err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
2300                                             &data->cfg[n]);
2301                 if (err) {
2302                         dev_err(dev, "Can't register clk %s: %d\n",
2303                                 data->cfg[n].name, err);
2304
2305                         return err;
2306                 }
2307         }
2308
2309         return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
2310 }
2311
2312 static int stm32_rcc_init(struct device *dev, void __iomem *base,
2313                           const struct of_device_id *match_data)
2314 {
2315         const struct of_device_id *match;
2316         int err;
2317
2318         match = of_match_node(match_data, dev_of_node(dev));
2319         if (!match) {
2320                 dev_err(dev, "match data not found\n");
2321                 return -ENODEV;
2322         }
2323
2324         /* RCC Reset Configuration */
2325         err = stm32_rcc_reset_init(dev, base, match);
2326         if (err) {
2327                 pr_err("stm32mp1 reset failed to initialize\n");
2328                 return err;
2329         }
2330
2331         /* RCC Clock Configuration */
2332         err = stm32_rcc_clock_init(dev, base, match);
2333         if (err) {
2334                 pr_err("stm32mp1 clock failed to initialize\n");
2335                 return err;
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int stm32mp1_rcc_init(struct device *dev)
2342 {
2343         void __iomem *base;
2344         int ret;
2345
2346         base = of_iomap(dev_of_node(dev), 0);
2347         if (!base) {
2348                 pr_err("%pOFn: unable to map resource", dev_of_node(dev));
2349                 ret = -ENOMEM;
2350                 goto out;
2351         }
2352
2353         ret = stm32_rcc_init(dev, base, stm32mp1_match_data);
2354
2355 out:
2356         if (ret) {
2357                 if (base)
2358                         iounmap(base);
2359
2360                 of_node_put(dev_of_node(dev));
2361         }
2362
2363         return ret;
2364 }
2365
2366 static int get_clock_deps(struct device *dev)
2367 {
2368         static const char * const clock_deps_name[] = {
2369                 "hsi", "hse", "csi", "lsi", "lse",
2370         };
2371         size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
2372         struct clk **clk_deps;
2373         int i;
2374
2375         clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
2376         if (!clk_deps)
2377                 return -ENOMEM;
2378
2379         for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
2380                 struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
2381                                                      clock_deps_name[i]);
2382
2383                 if (IS_ERR(clk)) {
2384                         if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
2385                                 return PTR_ERR(clk);
2386                 } else {
2387                         /* Device gets a reference count on the clock */
2388                         clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
2389                         clk_put(clk);
2390                 }
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
2397 {
2398         struct device *dev = &pdev->dev;
2399         int ret = get_clock_deps(dev);
2400
2401         if (!ret)
2402                 ret = stm32mp1_rcc_init(dev);
2403
2404         return ret;
2405 }
2406
2407 static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
2408 {
2409         struct device *dev = &pdev->dev;
2410         struct device_node *child, *np = dev_of_node(dev);
2411
2412         for_each_available_child_of_node(np, child)
2413                 of_clk_del_provider(child);
2414
2415         return 0;
2416 }
2417
2418 static struct platform_driver stm32mp1_rcc_clocks_driver = {
2419         .driver = {
2420                 .name = "stm32mp1_rcc",
2421                 .of_match_table = stm32mp1_match_data,
2422         },
2423         .probe = stm32mp1_rcc_clocks_probe,
2424         .remove = stm32mp1_rcc_clocks_remove,
2425 };
2426
2427 static int __init stm32mp1_clocks_init(void)
2428 {
2429         return platform_driver_register(&stm32mp1_rcc_clocks_driver);
2430 }
2431 core_initcall(stm32mp1_clocks_init);