1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
7 * The Si5341 has 10 outputs and 5 synthesizers.
8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
9 * The Si5345 is similar to the Si5341, with the addition of fractional input
10 * dividers and automatic input selection.
11 * The Si5342 and Si5344 are smaller versions of the Si5345.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/gcd.h>
18 #include <linux/math64.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <asm/unaligned.h>
25 #define SI5341_NUM_INPUTS 4
27 #define SI5340_MAX_NUM_OUTPUTS 4
28 #define SI5341_MAX_NUM_OUTPUTS 10
29 #define SI5342_MAX_NUM_OUTPUTS 2
30 #define SI5344_MAX_NUM_OUTPUTS 4
31 #define SI5345_MAX_NUM_OUTPUTS 10
33 #define SI5340_NUM_SYNTH 4
34 #define SI5341_NUM_SYNTH 5
35 #define SI5342_NUM_SYNTH 2
36 #define SI5344_NUM_SYNTH 4
37 #define SI5345_NUM_SYNTH 5
39 /* Range of the synthesizer fractional divider */
40 #define SI5341_SYNTH_N_MIN 10
41 #define SI5341_SYNTH_N_MAX 4095
43 /* The chip can get its input clock from 3 input pins or an XTAL */
45 /* There is one PLL running at 13500–14256 MHz */
46 #define SI5341_PLL_VCO_MIN 13500000000ull
47 #define SI5341_PLL_VCO_MAX 14256000000ull
49 /* The 5 frequency synthesizers obtain their input from the PLL */
50 struct clk_si5341_synth {
52 struct clk_si5341 *data;
55 #define to_clk_si5341_synth(_hw) \
56 container_of(_hw, struct clk_si5341_synth, hw)
58 /* The output stages can be connected to any synth (full mux) */
59 struct clk_si5341_output {
61 struct clk_si5341 *data;
64 #define to_clk_si5341_output(_hw) \
65 container_of(_hw, struct clk_si5341_output, hw)
69 struct regmap *regmap;
70 struct i2c_client *i2c_client;
71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
73 struct clk *input_clk[SI5341_NUM_INPUTS];
74 const char *input_clk_name[SI5341_NUM_INPUTS];
75 const u16 *reg_output_offset;
76 const u16 *reg_rdiv_offset;
77 u64 freq_vco; /* 13500–14256 MHz */
82 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
84 struct clk_si5341_output_config {
85 u8 out_format_drv_bits;
91 #define SI5341_PAGE 0x0001
92 #define SI5341_PN_BASE 0x0002
93 #define SI5341_DEVICE_REV 0x0005
94 #define SI5341_STATUS 0x000C
95 #define SI5341_LOS 0x000D
96 #define SI5341_STATUS_STICKY 0x0011
97 #define SI5341_LOS_STICKY 0x0012
98 #define SI5341_SOFT_RST 0x001C
99 #define SI5341_IN_SEL 0x0021
100 #define SI5341_DEVICE_READY 0x00FE
101 #define SI5341_XAXB_CFG 0x090E
102 #define SI5341_IN_EN 0x0949
103 #define SI5341_INX_TO_PFD_EN 0x094A
106 #define SI5341_STATUS_SYSINCAL BIT(0)
107 #define SI5341_STATUS_LOSXAXB BIT(1)
108 #define SI5341_STATUS_LOSREF BIT(2)
109 #define SI5341_STATUS_LOL BIT(3)
111 /* Input selection */
112 #define SI5341_IN_SEL_MASK 0x06
113 #define SI5341_IN_SEL_SHIFT 1
114 #define SI5341_IN_SEL_REGCTRL 0x01
115 #define SI5341_INX_TO_PFD_SHIFT 4
117 /* XTAL config bits */
118 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
119 #define SI5341_XAXB_CFG_PDNB BIT(1)
121 /* Input dividers (48-bit) */
122 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
123 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
124 #define SI5341_PX_UPD 0x0230
126 /* PLL configuration */
127 #define SI5341_PLL_M_NUM 0x0235
128 #define SI5341_PLL_M_DEN 0x023B
130 /* Output configuration */
131 #define SI5341_OUT_CONFIG(output) \
132 ((output)->data->reg_output_offset[(output)->index])
133 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
134 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
135 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
136 #define SI5341_OUT_R_REG(output) \
137 ((output)->data->reg_rdiv_offset[(output)->index])
139 /* Synthesize N divider */
140 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
141 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
142 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
144 /* Synthesizer output enable, phase bypass, power mode */
145 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
146 #define SI5341_SYNTH_N_PIBYP 0x0A04
147 #define SI5341_SYNTH_N_PDNB 0x0A05
148 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
150 #define SI5341_REGISTER_MAX 0xBFF
152 /* SI5341_OUT_CONFIG bits */
153 #define SI5341_OUT_CFG_PDN BIT(0)
154 #define SI5341_OUT_CFG_OE BIT(1)
155 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
157 /* Static configuration (to be moved to firmware) */
158 struct si5341_reg_default {
163 static const char * const si5341_input_clock_names[] = {
164 "in0", "in1", "in2", "xtal"
167 /* Output configuration registers 0..9 are not quite logically organized */
168 /* Also for si5345 */
169 static const u16 si5341_reg_output_offset[] = {
182 /* for si5340, si5342 and si5344 */
183 static const u16 si5340_reg_output_offset[] = {
190 /* The location of the R divider registers */
191 static const u16 si5341_reg_rdiv_offset[] = {
203 static const u16 si5340_reg_rdiv_offset[] = {
211 * Programming sequence from ClockBuilder, settings to initialize the system
212 * using only the XTAL input, without pre-divider.
213 * This also contains settings that aren't mentioned anywhere in the datasheet.
214 * The "known" settings like synth and output configuration are done later.
216 static const struct si5341_reg_default si5341_reg_defaults[] = {
217 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
218 { 0x0018, 0xFF }, /* INT mask */
219 { 0x0021, 0x0F }, /* Select XTAL as input */
220 { 0x0022, 0x00 }, /* Not in datasheet */
221 { 0x002B, 0x02 }, /* SPI config */
222 { 0x002C, 0x20 }, /* LOS enable for XTAL */
223 { 0x002D, 0x00 }, /* LOS timing */
234 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
239 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
240 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
241 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
242 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
243 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
244 { 0x009E, 0x00 }, /* Not in datasheet */
245 { 0x0102, 0x01 }, /* Enable outputs */
246 { 0x013F, 0x00 }, /* Not in datasheet */
247 { 0x0140, 0x00 }, /* Not in datasheet */
248 { 0x0141, 0x40 }, /* OUT LOS */
249 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
253 { 0x0206, 0x00 }, /* PXAXB (2^x) */
254 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
293 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
294 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
301 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
302 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
303 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
332 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
333 { 0x0359, 0x00 }, /* Nx_DELAY */
342 { 0x0362, 0x00 }, /* Nx_DELAY end */
343 { 0x0802, 0x00 }, /* Not in datasheet */
344 { 0x0803, 0x00 }, /* Not in datasheet */
345 { 0x0804, 0x00 }, /* Not in datasheet */
346 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
347 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
348 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
349 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
350 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
351 { 0x0A02, 0x00 }, /* Not in datasheet */
352 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
355 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
356 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
357 u64 *val1, u32 *val2)
362 err = regmap_bulk_read(regmap, reg, r, 10);
366 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
367 (get_unaligned_le32(r));
368 *val2 = get_unaligned_le32(&r[6]);
373 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
374 u64 n_num, u32 n_den)
378 /* Shift left as far as possible without overflowing */
379 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
384 /* 44 bits (6 bytes) numerator */
385 put_unaligned_le32(n_num, r);
386 r[4] = (n_num >> 32) & 0xff;
387 r[5] = (n_num >> 40) & 0x0f;
388 /* 32 bits denominator */
389 put_unaligned_le32(n_den, &r[6]);
391 /* Program the fraction */
392 return regmap_bulk_write(regmap, reg, r, sizeof(r));
395 /* VCO, we assume it runs at a constant frequency */
396 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
397 unsigned long parent_rate)
399 struct clk_si5341 *data = to_clk_si5341(hw);
406 /* Assume that PDIV is not being used, just read the PLL setting */
407 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
412 if (!m_num || !m_den)
416 * Though m_num is 64-bit, only the upper bits are actually used. While
417 * calculating m_num and m_den, they are shifted as far as possible to
418 * the left. To avoid 96-bit division here, we just shift them back so
419 * we can do with just 64 bits.
423 while (res & 0xffff00000000ULL) {
428 do_div(res, (m_den >> shift));
430 /* We cannot return the actual frequency in 32 bit, store it locally */
431 data->freq_vco = res;
433 /* Report kHz since the value is out of range */
436 return (unsigned long)res;
439 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
444 err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
448 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
451 static u8 si5341_clk_get_parent(struct clk_hw *hw)
453 struct clk_si5341 *data = to_clk_si5341(hw);
454 int res = si5341_clk_get_selected_input(data);
457 return 0; /* Apparently we cannot report errors */
462 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
467 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
468 /* Enable register-based input selection */
469 val |= SI5341_IN_SEL_REGCTRL;
471 err = regmap_update_bits(data->regmap,
472 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
477 /* Enable input buffer for selected input */
478 err = regmap_update_bits(data->regmap,
479 SI5341_IN_EN, 0x07, BIT(index));
483 /* Enables the input to phase detector */
484 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
485 0x7 << SI5341_INX_TO_PFD_SHIFT,
486 BIT(index + SI5341_INX_TO_PFD_SHIFT));
490 /* Power down XTAL oscillator and buffer */
491 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
492 SI5341_XAXB_CFG_PDNB, 0);
497 * Set the P divider to "1". There's no explanation in the
498 * datasheet of these registers, but the clockbuilder software
499 * programs a "1" when the input is being used.
501 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
505 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
509 /* Set update PDIV bit */
510 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
514 /* Disable all input buffers */
515 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
519 /* Disable input to phase detector */
520 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
521 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
525 /* Power up XTAL oscillator and buffer */
526 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
527 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
535 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
537 struct clk_si5341 *data = to_clk_si5341(hw);
539 return si5341_clk_reparent(data, index);
542 static const struct clk_ops si5341_clk_ops = {
543 .set_parent = si5341_clk_set_parent,
544 .get_parent = si5341_clk_get_parent,
545 .recalc_rate = si5341_clk_recalc_rate,
548 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
550 /* The synthesizer is on if all power and enable bits are set */
551 static int si5341_synth_clk_is_on(struct clk_hw *hw)
553 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
556 u8 index = synth->index;
558 err = regmap_read(synth->data->regmap,
559 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
563 if (!(val & BIT(index)))
566 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
570 if (!(val & BIT(index)))
573 /* This bit must be 0 for the synthesizer to receive clock input */
574 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
578 return !(val & BIT(index));
581 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
583 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
584 u8 index = synth->index; /* In range 0..5 */
585 u8 mask = BIT(index);
588 regmap_update_bits(synth->data->regmap,
589 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
591 regmap_update_bits(synth->data->regmap,
592 SI5341_SYNTH_N_PDNB, mask, 0);
593 /* Disable clock input to synth (set to 1 to disable) */
594 regmap_update_bits(synth->data->regmap,
595 SI5341_SYNTH_N_CLK_DIS, mask, mask);
598 static int si5341_synth_clk_prepare(struct clk_hw *hw)
600 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
602 u8 index = synth->index;
603 u8 mask = BIT(index);
606 err = regmap_update_bits(synth->data->regmap,
607 SI5341_SYNTH_N_PDNB, mask, mask);
611 /* Enable clock input to synth (set bit to 0 to enable) */
612 err = regmap_update_bits(synth->data->regmap,
613 SI5341_SYNTH_N_CLK_DIS, mask, 0);
618 return regmap_update_bits(synth->data->regmap,
619 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
622 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
623 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
624 unsigned long parent_rate)
626 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
632 err = si5341_decode_44_32(synth->data->regmap,
633 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
636 /* Check for bogus/uninitialized settings */
637 if (!n_num || !n_den)
641 * n_num and n_den are shifted left as much as possible, so to prevent
642 * overflow in 64-bit math, we shift n_den 4 bits to the right
644 f = synth->data->freq_vco;
647 /* Now we need to to 64-bit division: f/n_num */
648 /* And compensate for the 4 bits we dropped */
649 f = div64_u64(f, (n_num >> 4));
654 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
655 unsigned long *parent_rate)
657 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
660 /* The synthesizer accuracy is such that anything in range will work */
661 f = synth->data->freq_vco;
662 do_div(f, SI5341_SYNTH_N_MAX);
666 f = synth->data->freq_vco;
667 do_div(f, SI5341_SYNTH_N_MIN);
674 static int si5341_synth_program(struct clk_si5341_synth *synth,
675 u64 n_num, u32 n_den, bool is_integer)
678 u8 index = synth->index;
680 err = si5341_encode_44_32(synth->data->regmap,
681 SI5341_SYNTH_N_NUM(index), n_num, n_den);
683 err = regmap_update_bits(synth->data->regmap,
684 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
688 return regmap_write(synth->data->regmap,
689 SI5341_SYNTH_N_UPD(index), 0x01);
693 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
694 unsigned long parent_rate)
696 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
703 n_num = synth->data->freq_vco;
705 /* see if there's an integer solution */
706 r = do_div(n_num, rate);
707 is_integer = (r == 0);
709 /* Integer divider equal to n_num */
712 /* Calculate a fractional solution */
719 dev_dbg(&synth->data->i2c_client->dev,
720 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
721 synth->index, n_num, n_den,
722 is_integer ? "int" : "frac");
724 return si5341_synth_program(synth, n_num, n_den, is_integer);
727 static const struct clk_ops si5341_synth_clk_ops = {
728 .is_prepared = si5341_synth_clk_is_on,
729 .prepare = si5341_synth_clk_prepare,
730 .unprepare = si5341_synth_clk_unprepare,
731 .recalc_rate = si5341_synth_clk_recalc_rate,
732 .round_rate = si5341_synth_clk_round_rate,
733 .set_rate = si5341_synth_clk_set_rate,
736 static int si5341_output_clk_is_on(struct clk_hw *hw)
738 struct clk_si5341_output *output = to_clk_si5341_output(hw);
742 err = regmap_read(output->data->regmap,
743 SI5341_OUT_CONFIG(output), &val);
747 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
748 return (val & 0x03) == SI5341_OUT_CFG_OE;
751 /* Disables and then powers down the output */
752 static void si5341_output_clk_unprepare(struct clk_hw *hw)
754 struct clk_si5341_output *output = to_clk_si5341_output(hw);
756 regmap_update_bits(output->data->regmap,
757 SI5341_OUT_CONFIG(output),
758 SI5341_OUT_CFG_OE, 0);
759 regmap_update_bits(output->data->regmap,
760 SI5341_OUT_CONFIG(output),
761 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
764 /* Powers up and then enables the output */
765 static int si5341_output_clk_prepare(struct clk_hw *hw)
767 struct clk_si5341_output *output = to_clk_si5341_output(hw);
770 err = regmap_update_bits(output->data->regmap,
771 SI5341_OUT_CONFIG(output),
772 SI5341_OUT_CFG_PDN, 0);
776 return regmap_update_bits(output->data->regmap,
777 SI5341_OUT_CONFIG(output),
778 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
781 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
782 unsigned long parent_rate)
784 struct clk_si5341_output *output = to_clk_si5341_output(hw);
790 err = regmap_bulk_read(output->data->regmap,
791 SI5341_OUT_R_REG(output), r, 3);
795 /* Calculate value as 24-bit integer*/
796 r_divider = r[2] << 16 | r[1] << 8 | r[0];
798 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
802 /* Divider is 2*(Rx_REG+1) */
806 err = regmap_read(output->data->regmap,
807 SI5341_OUT_CONFIG(output), &val);
811 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
814 return parent_rate / r_divider;
817 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
818 unsigned long *parent_rate)
825 r = *parent_rate >> 1;
827 /* If rate is an even divisor, no changes to parent required */
828 if (r && !(r % rate))
831 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
832 if (rate > 200000000) {
833 /* minimum r-divider is 2 */
836 /* Take a parent frequency near 400 MHz */
837 r = (400000000u / rate) & ~1;
839 *parent_rate = r * rate;
841 /* We cannot change our parent's rate, report what we can do */
843 rate = *parent_rate / (r << 1);
849 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
850 unsigned long parent_rate)
852 struct clk_si5341_output *output = to_clk_si5341_output(hw);
860 /* Frequency divider is (r_div + 1) * 2 */
861 r_div = (parent_rate / rate) >> 1;
865 else if (r_div >= BIT(24))
870 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
871 err = regmap_update_bits(output->data->regmap,
872 SI5341_OUT_CONFIG(output),
873 SI5341_OUT_CFG_RDIV_FORCE2,
874 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
878 /* Always write Rx_REG, because a zero value disables the divider */
879 r[0] = r_div ? (r_div & 0xff) : 1;
880 r[1] = (r_div >> 8) & 0xff;
881 r[2] = (r_div >> 16) & 0xff;
882 err = regmap_bulk_write(output->data->regmap,
883 SI5341_OUT_R_REG(output), r, 3);
888 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
890 return regmap_update_bits(output->data->regmap,
891 SI5341_OUT_MUX_SEL(output), 0x07, index);
894 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
896 struct clk_si5341_output *output = to_clk_si5341_output(hw);
898 if (index >= output->data->num_synth)
901 return si5341_output_reparent(output, index);
904 static u8 si5341_output_get_parent(struct clk_hw *hw)
906 struct clk_si5341_output *output = to_clk_si5341_output(hw);
909 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
914 static const struct clk_ops si5341_output_clk_ops = {
915 .is_prepared = si5341_output_clk_is_on,
916 .prepare = si5341_output_clk_prepare,
917 .unprepare = si5341_output_clk_unprepare,
918 .recalc_rate = si5341_output_clk_recalc_rate,
919 .round_rate = si5341_output_clk_round_rate,
920 .set_rate = si5341_output_clk_set_rate,
921 .set_parent = si5341_output_set_parent,
922 .get_parent = si5341_output_get_parent,
926 * The chip can be bought in a pre-programmed version, or one can program the
927 * NVM in the chip to boot up in a preset mode. This routine tries to determine
928 * if that's the case, or if we need to reset and program everything from
929 * scratch. Returns negative error, or true/false.
931 static int si5341_is_programmed_already(struct clk_si5341 *data)
936 /* Read the PLL divider value, it must have a non-zero value */
937 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
942 return !!get_unaligned_le32(r);
945 static struct clk_hw *
946 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
948 struct clk_si5341 *data = _data;
949 unsigned int idx = clkspec->args[1];
950 unsigned int group = clkspec->args[0];
954 if (idx >= data->num_outputs) {
955 dev_err(&data->i2c_client->dev,
956 "invalid output index %u\n", idx);
957 return ERR_PTR(-EINVAL);
959 return &data->clk[idx].hw;
961 if (idx >= data->num_synth) {
962 dev_err(&data->i2c_client->dev,
963 "invalid synthesizer index %u\n", idx);
964 return ERR_PTR(-EINVAL);
966 return &data->synth[idx].hw;
969 dev_err(&data->i2c_client->dev,
970 "invalid PLL index %u\n", idx);
971 return ERR_PTR(-EINVAL);
975 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
976 return ERR_PTR(-EINVAL);
980 static int si5341_probe_chip_id(struct clk_si5341 *data)
986 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
989 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
993 model = get_unaligned_le16(reg);
995 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
996 model, reg[2], reg[3]);
1000 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1001 data->num_synth = SI5340_NUM_SYNTH;
1002 data->reg_output_offset = si5340_reg_output_offset;
1003 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1006 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1007 data->num_synth = SI5341_NUM_SYNTH;
1008 data->reg_output_offset = si5341_reg_output_offset;
1009 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1012 data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1013 data->num_synth = SI5342_NUM_SYNTH;
1014 data->reg_output_offset = si5340_reg_output_offset;
1015 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1018 data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1019 data->num_synth = SI5344_NUM_SYNTH;
1020 data->reg_output_offset = si5340_reg_output_offset;
1021 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1024 data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1025 data->num_synth = SI5345_NUM_SYNTH;
1026 data->reg_output_offset = si5341_reg_output_offset;
1027 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1030 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1035 data->chip_id = model;
1040 /* Read active settings into the regmap cache for later reference */
1041 static int si5341_read_settings(struct clk_si5341 *data)
1047 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1051 err = regmap_bulk_read(data->regmap,
1052 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1056 err = regmap_bulk_read(data->regmap,
1057 SI5341_SYNTH_N_CLK_DIS, r, 1);
1061 for (i = 0; i < data->num_synth; ++i) {
1062 err = regmap_bulk_read(data->regmap,
1063 SI5341_SYNTH_N_NUM(i), r, 10);
1068 for (i = 0; i < data->num_outputs; ++i) {
1069 err = regmap_bulk_read(data->regmap,
1070 data->reg_output_offset[i], r, 4);
1074 err = regmap_bulk_read(data->regmap,
1075 data->reg_rdiv_offset[i], r, 3);
1083 static int si5341_write_multiple(struct clk_si5341 *data,
1084 const struct si5341_reg_default *values, unsigned int num_values)
1089 for (i = 0; i < num_values; ++i) {
1090 res = regmap_write(data->regmap,
1091 values[i].address, values[i].value);
1093 dev_err(&data->i2c_client->dev,
1094 "Failed to write %#x:%#x\n",
1095 values[i].address, values[i].value);
1103 static const struct si5341_reg_default si5341_preamble[] = {
1111 static const struct si5341_reg_default si5345_preamble[] = {
1116 static int si5341_send_preamble(struct clk_si5341 *data)
1121 /* For revision 2 and up, the values are slightly different */
1122 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1126 /* Write "preamble" as specified by datasheet */
1127 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1131 /* The si5342..si5345 require a different preamble */
1132 if (data->chip_id > 0x5341)
1133 res = si5341_write_multiple(data,
1134 si5345_preamble, ARRAY_SIZE(si5345_preamble));
1136 res = si5341_write_multiple(data,
1137 si5341_preamble, ARRAY_SIZE(si5341_preamble));
1141 /* Datasheet specifies a 300ms wait after sending the preamble */
1147 /* Perform a soft reset and write post-amble */
1148 static int si5341_finalize_defaults(struct clk_si5341 *data)
1153 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1157 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1159 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1163 /* The si5342..si5345 have an additional post-amble */
1164 if (data->chip_id > 0x5341) {
1165 res = regmap_write(data->regmap, 0x540, 0x0);
1170 /* Datasheet does not explain these nameless registers */
1171 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1174 res = regmap_write(data->regmap, 0x0B25, 0x02);
1182 static const struct regmap_range si5341_regmap_volatile_range[] = {
1183 regmap_reg_range(0x000C, 0x0012), /* Status */
1184 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1185 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1186 /* Update bits for P divider and synth config */
1187 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1188 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1189 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1190 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1191 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1192 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1195 static const struct regmap_access_table si5341_regmap_volatile = {
1196 .yes_ranges = si5341_regmap_volatile_range,
1197 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1200 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1201 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1204 .range_max = SI5341_REGISTER_MAX,
1205 .selector_reg = SI5341_PAGE,
1206 .selector_mask = 0xff,
1207 .selector_shift = 0,
1213 static int si5341_wait_device_ready(struct i2c_client *client)
1217 /* Datasheet warns: Any attempt to read or write any register other
1218 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1219 * NVM programming and may corrupt the register contents, as they are
1220 * read from NVM. Note that this includes accesses to the PAGE register.
1221 * Also: DEVICE_READY is available on every register page, so no page
1222 * change is needed to read it.
1223 * Do this outside regmap to avoid automatic PAGE register access.
1224 * May take up to 300ms to complete.
1226 for (count = 0; count < 15; ++count) {
1227 s32 result = i2c_smbus_read_byte_data(client,
1228 SI5341_DEVICE_READY);
1235 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1239 static const struct regmap_config si5341_regmap_config = {
1242 .cache_type = REGCACHE_RBTREE,
1243 .ranges = si5341_regmap_ranges,
1244 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1245 .max_register = SI5341_REGISTER_MAX,
1246 .volatile_table = &si5341_regmap_volatile,
1249 static int si5341_dt_parse_dt(struct i2c_client *client,
1250 struct clk_si5341_output_config *config)
1252 struct device_node *child;
1253 struct device_node *np = client->dev.of_node;
1257 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1258 SI5341_MAX_NUM_OUTPUTS);
1260 for_each_child_of_node(np, child) {
1261 if (of_property_read_u32(child, "reg", &num)) {
1262 dev_err(&client->dev, "missing reg property of %s\n",
1267 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1268 dev_err(&client->dev, "invalid clkout %d\n", num);
1272 if (!of_property_read_u32(child, "silabs,format", &val)) {
1273 /* Set cm and ampl conservatively to 3v3 settings */
1275 case 1: /* normal differential */
1276 config[num].out_cm_ampl_bits = 0x33;
1278 case 2: /* low-power differential */
1279 config[num].out_cm_ampl_bits = 0x13;
1281 case 4: /* LVCMOS */
1282 config[num].out_cm_ampl_bits = 0x33;
1283 /* Set SI recommended impedance for LVCMOS */
1284 config[num].out_format_drv_bits |= 0xc0;
1287 dev_err(&client->dev,
1288 "invalid silabs,format %u for %u\n",
1292 config[num].out_format_drv_bits &= ~0x07;
1293 config[num].out_format_drv_bits |= val & 0x07;
1294 /* Always enable the SYNC feature */
1295 config[num].out_format_drv_bits |= 0x08;
1298 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1300 dev_err(&client->dev,
1301 "invalid silabs,common-mode %u\n",
1305 config[num].out_cm_ampl_bits &= 0xf0;
1306 config[num].out_cm_ampl_bits |= val & 0x0f;
1309 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1311 dev_err(&client->dev,
1312 "invalid silabs,amplitude %u\n",
1316 config[num].out_cm_ampl_bits &= 0x0f;
1317 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1320 if (of_property_read_bool(child, "silabs,disable-high"))
1321 config[num].out_format_drv_bits |= 0x10;
1323 config[num].synth_master =
1324 of_property_read_bool(child, "silabs,synth-master");
1326 config[num].always_on =
1327 of_property_read_bool(child, "always-on");
1338 * If not pre-configured, calculate and set the PLL configuration manually.
1339 * For low-jitter performance, the PLL should be set such that the synthesizers
1340 * only need integer division.
1341 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1342 * the chip to generate any frequency on its outputs, but jitter performance
1343 * may be sub-optimal.
1345 static int si5341_initialize_pll(struct clk_si5341 *data)
1347 struct device_node *np = data->i2c_client->dev.of_node;
1352 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1353 dev_err(&data->i2c_client->dev,
1354 "PLL configuration requires silabs,pll-m-num\n");
1356 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1357 dev_err(&data->i2c_client->dev,
1358 "PLL configuration requires silabs,pll-m-den\n");
1361 if (!m_num || !m_den) {
1362 dev_err(&data->i2c_client->dev,
1363 "PLL configuration invalid, assume 14GHz\n");
1364 sel = si5341_clk_get_selected_input(data);
1368 m_den = clk_get_rate(data->input_clk[sel]) / 10;
1372 return si5341_encode_44_32(data->regmap,
1373 SI5341_PLL_M_NUM, m_num, m_den);
1376 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1382 res = si5341_clk_get_selected_input(data);
1386 /* If the current register setting is invalid, pick the first input */
1387 if (!data->input_clk[res]) {
1388 dev_dbg(&data->i2c_client->dev,
1389 "Input %d not connected, rerouting\n", res);
1391 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1392 if (data->input_clk[i]) {
1398 dev_err(&data->i2c_client->dev,
1399 "No clock input available\n");
1404 /* Make sure the selected clock is also enabled and routed */
1405 err = si5341_clk_reparent(data, res);
1409 err = clk_prepare_enable(data->input_clk[res]);
1416 static int si5341_probe(struct i2c_client *client,
1417 const struct i2c_device_id *id)
1419 struct clk_si5341 *data;
1420 struct clk_init_data init;
1422 const char *root_clock_name;
1423 const char *synth_clock_names[SI5341_NUM_SYNTH];
1426 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1427 bool initialization_required;
1430 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1434 data->i2c_client = client;
1436 /* Must be done before otherwise touching hardware */
1437 err = si5341_wait_device_ready(client);
1441 for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1442 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1443 if (IS_ERR(input)) {
1444 if (PTR_ERR(input) == -EPROBE_DEFER)
1445 return -EPROBE_DEFER;
1446 data->input_clk_name[i] = si5341_input_clock_names[i];
1448 data->input_clk[i] = input;
1449 data->input_clk_name[i] = __clk_get_name(input);
1453 err = si5341_dt_parse_dt(client, config);
1457 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1459 init.name = client->dev.of_node->name;
1460 root_clock_name = init.name;
1462 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1463 if (IS_ERR(data->regmap))
1464 return PTR_ERR(data->regmap);
1466 i2c_set_clientdata(client, data);
1468 err = si5341_probe_chip_id(data);
1472 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1473 initialization_required = true;
1475 err = si5341_is_programmed_already(data);
1479 initialization_required = !err;
1482 if (initialization_required) {
1483 /* Populate the regmap cache in preparation for "cache only" */
1484 err = si5341_read_settings(data);
1488 err = si5341_send_preamble(data);
1493 * We intend to send all 'final' register values in a single
1494 * transaction. So cache all register writes until we're done
1497 regcache_cache_only(data->regmap, true);
1499 /* Write the configuration pairs from the firmware blob */
1500 err = si5341_write_multiple(data, si5341_reg_defaults,
1501 ARRAY_SIZE(si5341_reg_defaults));
1506 /* Input must be up and running at this point */
1507 err = si5341_clk_select_active_input(data);
1511 if (initialization_required) {
1512 /* PLL configuration is required */
1513 err = si5341_initialize_pll(data);
1518 /* Register the PLL */
1519 init.parent_names = data->input_clk_name;
1520 init.num_parents = SI5341_NUM_INPUTS;
1521 init.ops = &si5341_clk_ops;
1523 data->hw.init = &init;
1525 err = devm_clk_hw_register(&client->dev, &data->hw);
1527 dev_err(&client->dev, "clock registration failed\n");
1531 init.num_parents = 1;
1532 init.parent_names = &root_clock_name;
1533 init.ops = &si5341_synth_clk_ops;
1534 for (i = 0; i < data->num_synth; ++i) {
1535 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1536 "%s.N%u", client->dev.of_node->name, i);
1537 init.name = synth_clock_names[i];
1538 data->synth[i].index = i;
1539 data->synth[i].data = data;
1540 data->synth[i].hw.init = &init;
1541 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1543 dev_err(&client->dev,
1544 "synth N%u registration failed\n", i);
1548 init.num_parents = data->num_synth;
1549 init.parent_names = synth_clock_names;
1550 init.ops = &si5341_output_clk_ops;
1551 for (i = 0; i < data->num_outputs; ++i) {
1552 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1553 client->dev.of_node->name, i);
1554 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1555 data->clk[i].index = i;
1556 data->clk[i].data = data;
1557 data->clk[i].hw.init = &init;
1558 if (config[i].out_format_drv_bits & 0x07) {
1559 regmap_write(data->regmap,
1560 SI5341_OUT_FORMAT(&data->clk[i]),
1561 config[i].out_format_drv_bits);
1562 regmap_write(data->regmap,
1563 SI5341_OUT_CM(&data->clk[i]),
1564 config[i].out_cm_ampl_bits);
1566 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1567 kfree(init.name); /* clock framework made a copy of the name */
1569 dev_err(&client->dev,
1570 "output %u registration failed\n", i);
1573 if (config[i].always_on)
1574 clk_prepare(data->clk[i].hw.clk);
1577 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1580 dev_err(&client->dev, "unable to add clk provider\n");
1584 if (initialization_required) {
1586 regcache_cache_only(data->regmap, false);
1587 err = regcache_sync(data->regmap);
1591 err = si5341_finalize_defaults(data);
1596 /* wait for device to report input clock present and PLL lock */
1597 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1598 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1601 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1605 /* clear sticky alarm bits from initialization */
1606 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1608 dev_err(&client->dev, "unable to clear sticky status\n");
1612 /* Free the names, clk framework makes copies */
1613 for (i = 0; i < data->num_synth; ++i)
1614 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1619 static const struct i2c_device_id si5341_id[] = {
1627 MODULE_DEVICE_TABLE(i2c, si5341_id);
1629 static const struct of_device_id clk_si5341_of_match[] = {
1630 { .compatible = "silabs,si5340" },
1631 { .compatible = "silabs,si5341" },
1632 { .compatible = "silabs,si5342" },
1633 { .compatible = "silabs,si5344" },
1634 { .compatible = "silabs,si5345" },
1637 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1639 static struct i2c_driver si5341_driver = {
1642 .of_match_table = clk_si5341_of_match,
1644 .probe = si5341_probe,
1645 .id_table = si5341_id,
1647 module_i2c_driver(si5341_driver);
1649 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1650 MODULE_DESCRIPTION("Si5341 driver");
1651 MODULE_LICENSE("GPL");