1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
5 * The following series can be supported:
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
10 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
13 #include <linux/clk-provider.h>
14 #include <linux/i2c.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
18 #include <linux/regmap.h>
20 #define RS9_REG_OE 0x0
21 #define RS9_REG_OE_DIF_OE(n) BIT((n) + 1)
22 #define RS9_REG_SS 0x1
23 #define RS9_REG_SS_AMP_0V6 0x0
24 #define RS9_REG_SS_AMP_0V7 0x1
25 #define RS9_REG_SS_AMP_0V8 0x2
26 #define RS9_REG_SS_AMP_0V9 0x3
27 #define RS9_REG_SS_AMP_MASK 0x3
28 #define RS9_REG_SS_SSC_100 0
29 #define RS9_REG_SS_SSC_M025 (1 << 3)
30 #define RS9_REG_SS_SSC_M050 (3 << 3)
31 #define RS9_REG_SS_SSC_MASK (3 << 3)
32 #define RS9_REG_SS_SSC_LOCK BIT(5)
33 #define RS9_REG_SR 0x2
34 #define RS9_REG_SR_2V0_DIF(n) 0
35 #define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1)
36 #define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1)
37 #define RS9_REG_REF 0x3
38 #define RS9_REG_REF_OE BIT(4)
39 #define RS9_REG_REF_OD BIT(5)
40 #define RS9_REG_REF_SR_SLOWEST 0
41 #define RS9_REG_REF_SR_SLOW (1 << 6)
42 #define RS9_REG_REF_SR_FAST (2 << 6)
43 #define RS9_REG_REF_SR_FASTER (3 << 6)
44 #define RS9_REG_VID 0x5
45 #define RS9_REG_DID 0x6
46 #define RS9_REG_BCP 0x7
48 /* Supported Renesas 9-series models. */
53 /* Structure to describe features of a particular 9-series model */
54 struct rs9_chip_info {
55 const enum rs9_model model;
56 unsigned int num_clks;
59 struct rs9_driver_data {
60 struct i2c_client *client;
61 struct regmap *regmap;
62 const struct rs9_chip_info *chip_info;
64 struct clk_hw *clk_dif[2];
71 * Renesas 9-series i2c regmap
73 static const struct regmap_range rs9_readable_ranges[] = {
74 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
75 regmap_reg_range(RS9_REG_VID, RS9_REG_BCP),
78 static const struct regmap_access_table rs9_readable_table = {
79 .yes_ranges = rs9_readable_ranges,
80 .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges),
83 static const struct regmap_range rs9_writeable_ranges[] = {
84 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
85 regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP),
88 static const struct regmap_access_table rs9_writeable_table = {
89 .yes_ranges = rs9_writeable_ranges,
90 .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges),
93 static const struct regmap_config rs9_regmap_config = {
96 .cache_type = REGCACHE_FLAT,
98 .rd_table = &rs9_readable_table,
99 .wr_table = &rs9_writeable_table,
102 static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
104 struct i2c_client *client = rs9->client;
105 unsigned char name[5] = "DIF0";
106 struct device_node *np;
111 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
112 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
114 snprintf(name, 5, "DIF%d", idx);
115 np = of_get_child_by_name(client->dev.of_node, name);
119 /* Output clock slew rate */
120 ret = of_property_read_u32(np, "renesas,slew-rate", &sr);
123 if (sr == 2000000) { /* 2V/ns */
124 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
125 rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx);
126 } else if (sr == 3000000) { /* 3V/ns (default) */
127 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
128 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
130 ret = dev_err_probe(&client->dev, -EINVAL,
131 "Invalid renesas,slew-rate value\n");
137 static int rs9_get_common_config(struct rs9_driver_data *rs9)
139 struct i2c_client *client = rs9->client;
140 struct device_node *np = client->dev.of_node;
141 unsigned int amp, ssc;
145 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
146 rs9->pll_ssc = RS9_REG_SS_SSC_100;
148 /* Output clock amplitude */
149 ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
152 if (amp == 600000) /* 0.6V */
153 rs9->pll_amplitude = RS9_REG_SS_AMP_0V6;
154 else if (amp == 700000) /* 0.7V (default) */
155 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
156 else if (amp == 800000) /* 0.8V */
157 rs9->pll_amplitude = RS9_REG_SS_AMP_0V8;
158 else if (amp == 900000) /* 0.9V */
159 rs9->pll_amplitude = RS9_REG_SS_AMP_0V9;
161 return dev_err_probe(&client->dev, -EINVAL,
162 "Invalid renesas,out-amplitude-microvolt value\n");
165 /* Output clock spread spectrum */
166 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc);
168 if (ssc == 100000) /* 100% ... no spread (default) */
169 rs9->pll_ssc = RS9_REG_SS_SSC_100;
170 else if (ssc == 99750) /* -0.25% ... down spread */
171 rs9->pll_ssc = RS9_REG_SS_SSC_M025;
172 else if (ssc == 99500) /* -0.50% ... down spread */
173 rs9->pll_ssc = RS9_REG_SS_SSC_M050;
175 return dev_err_probe(&client->dev, -EINVAL,
176 "Invalid renesas,out-spread-spectrum value\n");
182 static void rs9_update_config(struct rs9_driver_data *rs9)
186 /* If amplitude is non-default, update it. */
187 if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
188 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
192 /* If SSC is non-default, update it. */
193 if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
194 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
198 for (i = 0; i < rs9->chip_info->num_clks; i++) {
199 if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i))
202 regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i),
203 rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i));
207 static struct clk_hw *
208 rs9_of_clk_get(struct of_phandle_args *clkspec, void *data)
210 struct rs9_driver_data *rs9 = data;
211 unsigned int idx = clkspec->args[0];
213 return rs9->clk_dif[idx];
216 static int rs9_probe(struct i2c_client *client)
218 unsigned char name[5] = "DIF0";
219 struct rs9_driver_data *rs9;
223 rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL);
227 i2c_set_clientdata(client, rs9);
228 rs9->client = client;
229 rs9->chip_info = device_get_match_data(&client->dev);
233 /* Fetch common configuration from DT (if specified) */
234 ret = rs9_get_common_config(rs9);
238 /* Fetch DIFx output configuration from DT (if specified) */
239 for (i = 0; i < rs9->chip_info->num_clks; i++) {
240 ret = rs9_get_output_config(rs9, i);
245 rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config);
246 if (IS_ERR(rs9->regmap))
247 return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap),
248 "Failed to allocate register map\n");
251 for (i = 0; i < rs9->chip_info->num_clks; i++) {
252 snprintf(name, 5, "DIF%d", i);
253 hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name,
258 rs9->clk_dif[i] = hw;
261 ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9);
263 rs9_update_config(rs9);
268 static int __maybe_unused rs9_suspend(struct device *dev)
270 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
272 regcache_cache_only(rs9->regmap, true);
273 regcache_mark_dirty(rs9->regmap);
278 static int __maybe_unused rs9_resume(struct device *dev)
280 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
283 regcache_cache_only(rs9->regmap, false);
284 ret = regcache_sync(rs9->regmap);
286 dev_err(dev, "Failed to restore register map: %d\n", ret);
290 static const struct rs9_chip_info renesas_9fgv0241_info = {
291 .model = RENESAS_9FGV0241,
295 static const struct i2c_device_id rs9_id[] = {
296 { "9fgv0241", .driver_data = RENESAS_9FGV0241 },
299 MODULE_DEVICE_TABLE(i2c, rs9_id);
301 static const struct of_device_id clk_rs9_of_match[] = {
302 { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info },
305 MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
307 static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume);
309 static struct i2c_driver rs9_driver = {
311 .name = "clk-renesas-pcie-9series",
313 .of_match_table = clk_rs9_of_match,
315 .probe_new = rs9_probe,
318 module_i2c_driver(rs9_driver);
320 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
321 MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver");
322 MODULE_LICENSE("GPL");