2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * clock driver for Freescale QorIQ SoCs.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clkdev.h>
16 #include <linux/fsl/guts.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
23 #include <linux/slab.h>
30 #define PLATFORM_PLL 0
34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
37 #define MAX_PLL_DIV 16
39 struct clockgen_pll_div {
45 struct clockgen_pll_div div[MAX_PLL_DIV];
48 #define CLKSEL_VALID 1
49 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
51 struct clockgen_sourceinfo {
52 u32 flags; /* CLKSEL_xxx */
53 int pll; /* CGx_PLLn */
54 int div; /* PLL_DIVn */
57 #define NUM_MUX_PARENTS 16
59 struct clockgen_muxinfo {
60 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
69 * cmux freq must be >= platform pll.
70 * If not set, cmux freq must be >= platform pll/2
72 #define CG_CMUX_GE_PLAT 1
74 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
75 #define CG_VER3 4 /* version 3 cg: reg layout different */
76 #define CG_LITTLE_ENDIAN 8
78 struct clockgen_chipinfo {
79 const char *compat, *guts_compat;
80 const struct clockgen_muxinfo *cmux_groups[2];
81 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
82 void (*init_periph)(struct clockgen *cg);
83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
84 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
85 u32 flags; /* CG_xxx */
89 struct device_node *node;
91 struct clockgen_chipinfo info; /* mutable copy */
92 struct clk *sysclk, *coreclk;
93 struct clockgen_pll pll[6];
94 struct clk *cmux[NUM_CMUX];
95 struct clk *hwaccel[NUM_HWACCEL];
97 struct ccsr_guts __iomem *guts;
100 static struct clockgen clockgen;
102 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
104 if (cg->info.flags & CG_LITTLE_ENDIAN)
107 iowrite32be(val, reg);
110 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
114 if (cg->info.flags & CG_LITTLE_ENDIAN)
117 val = ioread32be(reg);
122 static const struct clockgen_muxinfo p2041_cmux_grp1 = {
124 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
125 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
126 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
130 static const struct clockgen_muxinfo p2041_cmux_grp2 = {
132 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
133 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
134 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
138 static const struct clockgen_muxinfo p5020_cmux_grp1 = {
140 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
141 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
142 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
146 static const struct clockgen_muxinfo p5020_cmux_grp2 = {
148 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
149 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
150 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
154 static const struct clockgen_muxinfo p5040_cmux_grp1 = {
156 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
157 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
158 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
159 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
163 static const struct clockgen_muxinfo p5040_cmux_grp2 = {
165 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
166 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
167 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
168 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
172 static const struct clockgen_muxinfo p4080_cmux_grp1 = {
174 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
175 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
176 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
177 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
178 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
182 static const struct clockgen_muxinfo p4080_cmux_grp2 = {
184 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
185 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
186 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
187 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
188 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
192 static const struct clockgen_muxinfo t1023_cmux = {
194 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
195 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
199 static const struct clockgen_muxinfo t1040_cmux = {
201 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
202 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
203 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
204 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
209 static const struct clockgen_muxinfo clockgen2_cmux_cga = {
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
213 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
217 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
221 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
225 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
229 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
233 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
237 static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
241 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
245 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
249 static const struct clockgen_muxinfo ls1028a_hwa1 = {
251 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
254 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
255 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
257 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
258 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
262 static const struct clockgen_muxinfo ls1028a_hwa2 = {
264 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
267 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
268 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
270 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
271 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
275 static const struct clockgen_muxinfo ls1028a_hwa3 = {
277 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
280 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
281 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
283 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
284 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
288 static const struct clockgen_muxinfo ls1028a_hwa4 = {
290 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
293 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
294 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
296 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
297 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
301 static const struct clockgen_muxinfo ls1043a_hwa1 = {
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
309 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
310 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
314 static const struct clockgen_muxinfo ls1043a_hwa2 = {
317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
319 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
323 static const struct clockgen_muxinfo ls1046a_hwa1 = {
327 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
328 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
329 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
330 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
331 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
332 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
336 static const struct clockgen_muxinfo ls1046a_hwa2 = {
339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
340 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
341 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
344 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
348 static const struct clockgen_muxinfo ls1012a_cmux = {
350 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
352 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
356 static const struct clockgen_muxinfo t1023_hwa1 = {
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
365 static const struct clockgen_muxinfo t1023_hwa2 = {
367 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
371 static const struct clockgen_muxinfo t2080_hwa1 = {
374 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
375 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
377 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
378 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
379 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
380 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
384 static const struct clockgen_muxinfo t2080_hwa2 = {
387 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
388 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
389 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
390 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
391 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
397 static const struct clockgen_muxinfo t4240_hwa1 = {
399 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
400 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
401 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
402 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
403 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
405 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
406 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
410 static const struct clockgen_muxinfo t4240_hwa4 = {
412 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
413 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
414 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
415 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
416 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
420 static const struct clockgen_muxinfo t4240_hwa5 = {
422 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
423 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
424 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
425 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
426 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
427 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
431 #define RCWSR7_FM1_CLK_SEL 0x40000000
432 #define RCWSR7_FM2_CLK_SEL 0x20000000
433 #define RCWSR7_HWA_ASYNC_DIV 0x04000000
435 static void __init p2041_init_periph(struct clockgen *cg)
439 reg = ioread32be(&cg->guts->rcwsr[7]);
441 if (reg & RCWSR7_FM1_CLK_SEL)
442 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
444 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
447 static void __init p4080_init_periph(struct clockgen *cg)
451 reg = ioread32be(&cg->guts->rcwsr[7]);
453 if (reg & RCWSR7_FM1_CLK_SEL)
454 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
456 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
458 if (reg & RCWSR7_FM2_CLK_SEL)
459 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
461 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
464 static void __init p5020_init_periph(struct clockgen *cg)
469 reg = ioread32be(&cg->guts->rcwsr[7]);
470 if (reg & RCWSR7_HWA_ASYNC_DIV)
473 if (reg & RCWSR7_FM1_CLK_SEL)
474 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
479 static void __init p5040_init_periph(struct clockgen *cg)
484 reg = ioread32be(&cg->guts->rcwsr[7]);
485 if (reg & RCWSR7_HWA_ASYNC_DIV)
488 if (reg & RCWSR7_FM1_CLK_SEL)
489 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
491 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
493 if (reg & RCWSR7_FM2_CLK_SEL)
494 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
496 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
499 static void __init t1023_init_periph(struct clockgen *cg)
501 cg->fman[0] = cg->hwaccel[1];
504 static void __init t1040_init_periph(struct clockgen *cg)
506 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
509 static void __init t2080_init_periph(struct clockgen *cg)
511 cg->fman[0] = cg->hwaccel[0];
514 static void __init t4240_init_periph(struct clockgen *cg)
516 cg->fman[0] = cg->hwaccel[3];
517 cg->fman[1] = cg->hwaccel[4];
520 static const struct clockgen_chipinfo chipinfo[] = {
522 .compat = "fsl,b4420-clockgen",
523 .guts_compat = "fsl,b4860-device-config",
524 .init_periph = t2080_init_periph,
526 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
535 .flags = CG_PLL_8BIT,
538 .compat = "fsl,b4860-clockgen",
539 .guts_compat = "fsl,b4860-device-config",
540 .init_periph = t2080_init_periph,
542 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
551 .flags = CG_PLL_8BIT,
554 .compat = "fsl,ls1021a-clockgen",
564 .compat = "fsl,ls1028a-clockgen",
566 &clockgen2_cmux_cga12
569 &ls1028a_hwa1, &ls1028a_hwa2,
570 &ls1028a_hwa3, &ls1028a_hwa4
576 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
579 .compat = "fsl,ls1043a-clockgen",
580 .init_periph = t2080_init_periph,
585 &ls1043a_hwa1, &ls1043a_hwa2
591 .flags = CG_PLL_8BIT,
594 .compat = "fsl,ls1046a-clockgen",
595 .init_periph = t2080_init_periph,
600 &ls1046a_hwa1, &ls1046a_hwa2
606 .flags = CG_PLL_8BIT,
609 .compat = "fsl,ls1088a-clockgen",
611 &clockgen2_cmux_cga12
617 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
620 .compat = "fsl,ls1012a-clockgen",
630 .compat = "fsl,ls2080a-clockgen",
632 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
638 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
641 .compat = "fsl,p2041-clockgen",
642 .guts_compat = "fsl,qoriq-device-config-1.0",
643 .init_periph = p2041_init_periph,
645 &p2041_cmux_grp1, &p2041_cmux_grp2
653 .compat = "fsl,p3041-clockgen",
654 .guts_compat = "fsl,qoriq-device-config-1.0",
655 .init_periph = p2041_init_periph,
657 &p2041_cmux_grp1, &p2041_cmux_grp2
665 .compat = "fsl,p4080-clockgen",
666 .guts_compat = "fsl,qoriq-device-config-1.0",
667 .init_periph = p4080_init_periph,
669 &p4080_cmux_grp1, &p4080_cmux_grp2
672 0, 0, 0, 0, 1, 1, 1, 1, -1
677 .compat = "fsl,p5020-clockgen",
678 .guts_compat = "fsl,qoriq-device-config-1.0",
679 .init_periph = p5020_init_periph,
681 &p2041_cmux_grp1, &p2041_cmux_grp2
689 .compat = "fsl,p5040-clockgen",
690 .guts_compat = "fsl,p5040-device-config",
691 .init_periph = p5040_init_periph,
693 &p5040_cmux_grp1, &p5040_cmux_grp2
701 .compat = "fsl,t1023-clockgen",
702 .guts_compat = "fsl,t1023-device-config",
703 .init_periph = t1023_init_periph,
708 &t1023_hwa1, &t1023_hwa2
714 .flags = CG_PLL_8BIT,
717 .compat = "fsl,t1040-clockgen",
718 .guts_compat = "fsl,t1040-device-config",
719 .init_periph = t1040_init_periph,
727 .flags = CG_PLL_8BIT,
730 .compat = "fsl,t2080-clockgen",
731 .guts_compat = "fsl,t2080-device-config",
732 .init_periph = t2080_init_periph,
734 &clockgen2_cmux_cga12
737 &t2080_hwa1, &t2080_hwa2
743 .flags = CG_PLL_8BIT,
746 .compat = "fsl,t4240-clockgen",
747 .guts_compat = "fsl,t4240-device-config",
748 .init_periph = t4240_init_periph,
750 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
753 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
759 .flags = CG_PLL_8BIT,
767 const struct clockgen_muxinfo *info;
769 u8 parent_to_clksel[NUM_MUX_PARENTS];
770 s8 clksel_to_parent[NUM_MUX_PARENTS];
774 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
775 #define CLKSEL_MASK 0x78000000
776 #define CLKSEL_SHIFT 27
778 static int mux_set_parent(struct clk_hw *hw, u8 idx)
780 struct mux_hwclock *hwc = to_mux_hwclock(hw);
783 if (idx >= hwc->num_parents)
786 clksel = hwc->parent_to_clksel[idx];
787 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
792 static u8 mux_get_parent(struct clk_hw *hw)
794 struct mux_hwclock *hwc = to_mux_hwclock(hw);
798 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
800 ret = hwc->clksel_to_parent[clksel];
802 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
809 static const struct clk_ops cmux_ops = {
810 .get_parent = mux_get_parent,
811 .set_parent = mux_set_parent,
815 * Don't allow setting for now, as the clock options haven't been
816 * sanitized for additional restrictions.
818 static const struct clk_ops hwaccel_ops = {
819 .get_parent = mux_get_parent,
822 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
823 struct mux_hwclock *hwc,
828 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
831 pll = hwc->info->clksel[idx].pll;
832 div = hwc->info->clksel[idx].div;
834 return &cg->pll[pll].div[div];
837 static struct clk * __init create_mux_common(struct clockgen *cg,
838 struct mux_hwclock *hwc,
839 const struct clk_ops *ops,
840 unsigned long min_rate,
841 unsigned long max_rate,
842 unsigned long pct80_rate,
843 const char *fmt, int idx)
845 struct clk_init_data init = {};
847 const struct clockgen_pll_div *div;
848 const char *parent_names[NUM_MUX_PARENTS];
852 snprintf(name, sizeof(name), fmt, idx);
854 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
857 hwc->clksel_to_parent[i] = -1;
859 div = get_pll_div(cg, hwc, i);
863 rate = clk_get_rate(div->clk);
865 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
873 parent_names[j] = div->name;
874 hwc->parent_to_clksel[j] = i;
875 hwc->clksel_to_parent[i] = j;
881 init.parent_names = parent_names;
882 init.num_parents = hwc->num_parents = j;
884 hwc->hw.init = &init;
887 clk = clk_register(NULL, &hwc->hw);
889 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
898 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
900 struct mux_hwclock *hwc;
901 const struct clockgen_pll_div *div;
902 unsigned long plat_rate, min_rate;
903 u64 max_rate, pct80_rate;
906 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
910 if (cg->info.flags & CG_VER3)
911 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
913 hwc->reg = cg->regs + 0x20 * idx;
915 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
918 * Find the rate for the default clksel, and treat it as the
919 * maximum rated core frequency. If this is an incorrect
920 * assumption, certain clock options (possibly including the
921 * default clksel) may be inappropriately excluded on certain
924 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
925 div = get_pll_div(cg, hwc, clksel);
931 max_rate = clk_get_rate(div->clk);
932 pct80_rate = max_rate * 8;
933 do_div(pct80_rate, 10);
935 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
937 if (cg->info.flags & CG_CMUX_GE_PLAT)
938 min_rate = plat_rate;
940 min_rate = plat_rate / 2;
942 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
943 pct80_rate, "cg-cmux%d", idx);
946 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
948 struct mux_hwclock *hwc;
950 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
954 hwc->reg = cg->regs + 0x20 * idx + 0x10;
955 hwc->info = cg->info.hwaccel[idx];
957 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
958 "cg-hwaccel%d", idx);
961 static void __init create_muxes(struct clockgen *cg)
965 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
966 if (cg->info.cmux_to_group[i] < 0)
968 if (cg->info.cmux_to_group[i] >=
969 ARRAY_SIZE(cg->info.cmux_groups)) {
974 cg->cmux[i] = create_one_cmux(cg, i);
977 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
978 if (!cg->info.hwaccel[i])
981 cg->hwaccel[i] = create_one_hwaccel(cg, i);
985 static void __init clockgen_init(struct device_node *np);
988 * Legacy nodes may get probed before the parent clockgen node.
989 * It is assumed that device trees with legacy nodes will not
990 * contain a "clocks" property -- otherwise the input clocks may
991 * not be initialized at this point.
993 static void __init legacy_init_clockgen(struct device_node *np)
996 clockgen_init(of_get_parent(np));
1000 static void __init core_mux_init(struct device_node *np)
1003 struct resource res;
1006 legacy_init_clockgen(np);
1008 if (of_address_to_resource(np, 0, &res))
1011 idx = (res.start & 0xf0) >> 5;
1012 clk = clockgen.cmux[idx];
1014 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1016 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1022 static struct clk __init
1023 *sysclk_from_fixed(struct device_node *node, const char *name)
1027 if (of_property_read_u32(node, "clock-frequency", &rate))
1028 return ERR_PTR(-ENODEV);
1030 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
1033 static struct clk __init *input_clock(const char *name, struct clk *clk)
1035 const char *input_name;
1037 /* Register the input clock under the desired name. */
1038 input_name = __clk_get_name(clk);
1039 clk = clk_register_fixed_factor(NULL, name, input_name,
1042 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
1048 static struct clk __init *input_clock_by_name(const char *name,
1053 clk = of_clk_get_by_name(clockgen.node, dtname);
1057 return input_clock(name, clk);
1060 static struct clk __init *input_clock_by_index(const char *name, int idx)
1064 clk = of_clk_get(clockgen.node, 0);
1068 return input_clock(name, clk);
1071 static struct clk * __init create_sysclk(const char *name)
1073 struct device_node *sysclk;
1076 clk = sysclk_from_fixed(clockgen.node, name);
1080 clk = input_clock_by_name(name, "sysclk");
1084 clk = input_clock_by_index(name, 0);
1088 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1090 clk = sysclk_from_fixed(sysclk, name);
1095 pr_err("%s: No input sysclk\n", __func__);
1099 static struct clk * __init create_coreclk(const char *name)
1103 clk = input_clock_by_name(name, "coreclk");
1108 * This indicates a mix of legacy nodes with the new coreclk
1109 * mechanism, which should never happen. If this error occurs,
1110 * don't use the wrong input clock just because coreclk isn't
1113 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1120 static void __init sysclk_init(struct device_node *node)
1124 legacy_init_clockgen(node);
1126 clk = clockgen.sysclk;
1128 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1131 #define PLL_KILL BIT(31)
1133 static void __init create_one_pll(struct clockgen *cg, int idx)
1137 struct clockgen_pll *pll = &cg->pll[idx];
1138 const char *input = "cg-sysclk";
1141 if (!(cg->info.pll_mask & (1 << idx)))
1144 if (cg->coreclk && idx != PLATFORM_PLL) {
1145 if (IS_ERR(cg->coreclk))
1148 input = "cg-coreclk";
1151 if (cg->info.flags & CG_VER3) {
1154 reg = cg->regs + 0x60080;
1157 reg = cg->regs + 0x80;
1160 reg = cg->regs + 0xa0;
1163 reg = cg->regs + 0x10080;
1166 reg = cg->regs + 0x100a0;
1169 WARN_ONCE(1, "index %d\n", idx);
1173 if (idx == PLATFORM_PLL)
1174 reg = cg->regs + 0xc00;
1176 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1179 /* Get the multiple of PLL */
1180 mult = cg_in(cg, reg);
1182 /* Check if this PLL is disabled */
1183 if (mult & PLL_KILL) {
1184 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1188 if ((cg->info.flags & CG_VER3) ||
1189 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1190 mult = (mult & GENMASK(8, 1)) >> 1;
1192 mult = (mult & GENMASK(6, 1)) >> 1;
1194 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1199 * For platform PLL, there are MAX_PLL_DIV divider clocks.
1200 * For core PLL, there are 4 divider clocks at most.
1202 if (idx != PLATFORM_PLL && i >= 4)
1205 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1206 "cg-pll%d-div%d", idx, i + 1);
1208 clk = clk_register_fixed_factor(NULL,
1209 pll->div[i].name, input, 0, mult, i + 1);
1211 pr_err("%s: %s: register failed %ld\n",
1212 __func__, pll->div[i].name, PTR_ERR(clk));
1216 pll->div[i].clk = clk;
1217 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1219 pr_err("%s: %s: register to lookup table failed %d\n",
1220 __func__, pll->div[i].name, ret);
1225 static void __init create_plls(struct clockgen *cg)
1229 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1230 create_one_pll(cg, i);
1233 static void __init legacy_pll_init(struct device_node *np, int idx)
1235 struct clockgen_pll *pll;
1236 struct clk_onecell_data *onecell_data;
1237 struct clk **subclks;
1240 legacy_init_clockgen(np);
1242 pll = &clockgen.pll[idx];
1243 count = of_property_count_strings(np, "clock-output-names");
1245 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1246 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1250 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1255 subclks[0] = pll->div[0].clk;
1256 subclks[1] = pll->div[1].clk;
1257 subclks[2] = pll->div[3].clk;
1259 subclks[0] = pll->div[0].clk;
1260 subclks[1] = pll->div[1].clk;
1261 subclks[2] = pll->div[2].clk;
1262 subclks[3] = pll->div[3].clk;
1265 onecell_data->clks = subclks;
1266 onecell_data->clk_num = count;
1268 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1270 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1277 kfree(onecell_data);
1283 static void __init pltfrm_pll_init(struct device_node *np)
1285 legacy_pll_init(np, PLATFORM_PLL);
1289 static void __init core_pll_init(struct device_node *np)
1291 struct resource res;
1294 if (of_address_to_resource(np, 0, &res))
1297 if ((res.start & 0xfff) == 0xc00) {
1299 * ls1021a devtree labels the platform PLL
1300 * with the core PLL compatible
1302 pltfrm_pll_init(np);
1304 idx = (res.start & 0xf0) >> 5;
1305 legacy_pll_init(np, CGA_PLL1 + idx);
1309 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1311 struct clockgen *cg = data;
1313 struct clockgen_pll *pll;
1316 if (clkspec->args_count < 2) {
1317 pr_err("%s: insufficient phandle args\n", __func__);
1318 return ERR_PTR(-EINVAL);
1321 type = clkspec->args[0];
1322 idx = clkspec->args[1];
1331 if (idx >= ARRAY_SIZE(cg->cmux))
1333 clk = cg->cmux[idx];
1336 if (idx >= ARRAY_SIZE(cg->hwaccel))
1338 clk = cg->hwaccel[idx];
1341 if (idx >= ARRAY_SIZE(cg->fman))
1343 clk = cg->fman[idx];
1346 pll = &cg->pll[PLATFORM_PLL];
1347 if (idx >= ARRAY_SIZE(pll->div))
1349 clk = pll->div[idx].clk;
1363 return ERR_PTR(-ENOENT);
1367 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1368 return ERR_PTR(-EINVAL);
1372 #include <asm/mpc85xx.h>
1374 static const u32 a4510_svrs[] __initconst = {
1375 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1376 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1377 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1378 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1379 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1380 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1381 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1382 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1383 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1384 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1385 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1386 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1387 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1390 #define SVR_SECURITY 0x80000 /* The Security (E) bit */
1392 static bool __init has_erratum_a4510(void)
1394 u32 svr = mfspr(SPRN_SVR);
1397 svr &= ~SVR_SECURITY;
1399 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1400 if (svr == a4510_svrs[i])
1407 static bool __init has_erratum_a4510(void)
1413 static void __init clockgen_init(struct device_node *np)
1416 bool is_old_ls1021a = false;
1418 /* May have already been called by a legacy probe */
1423 clockgen.regs = of_iomap(np, 0);
1424 if (!clockgen.regs &&
1425 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1426 /* Compatibility hack for old, broken device trees */
1427 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1428 is_old_ls1021a = true;
1430 if (!clockgen.regs) {
1431 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1435 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1436 if (of_device_is_compatible(np, chipinfo[i].compat))
1438 if (is_old_ls1021a &&
1439 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1443 if (i == ARRAY_SIZE(chipinfo)) {
1444 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1447 clockgen.info = chipinfo[i];
1449 if (clockgen.info.guts_compat) {
1450 struct device_node *guts;
1452 guts = of_find_compatible_node(NULL, NULL,
1453 clockgen.info.guts_compat);
1455 clockgen.guts = of_iomap(guts, 0);
1456 if (!clockgen.guts) {
1457 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1465 if (has_erratum_a4510())
1466 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1468 clockgen.sysclk = create_sysclk("cg-sysclk");
1469 clockgen.coreclk = create_coreclk("cg-coreclk");
1470 create_plls(&clockgen);
1471 create_muxes(&clockgen);
1473 if (clockgen.info.init_periph)
1474 clockgen.info.init_periph(&clockgen);
1476 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1478 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1484 iounmap(clockgen.regs);
1485 clockgen.regs = NULL;
1488 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1489 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1490 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1491 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1492 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1493 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1494 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1495 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1496 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1497 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1498 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1499 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1500 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1501 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1502 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1503 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1504 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1505 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1506 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1507 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1510 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1511 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1512 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1513 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1514 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1515 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1516 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1517 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);