1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 * Simple multiplexer clock implementation
14 * U-Boot CCF porting node:
16 * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
17 * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
18 * imx_cscmr1_fixup) for broken HW.
20 * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
26 #include <clk-uclass.h>
27 #include <dm/device.h>
28 #include <dm/devres.h>
29 #include <dm/uclass.h>
30 #include <linux/bitops.h>
33 #include <linux/clk-provider.h>
34 #include <linux/err.h>
37 #define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
39 int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
42 struct clk_mux *mux = to_clk_mux(clk);
43 int num_parents = mux->num_parents;
48 for (i = 0; i < num_parents; i++)
54 if (val && (flags & CLK_MUX_INDEX_BIT))
57 if (val && (flags & CLK_MUX_INDEX_ONE))
60 if (val >= num_parents)
66 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
68 unsigned int val = index;
73 if (flags & CLK_MUX_INDEX_BIT)
76 if (flags & CLK_MUX_INDEX_ONE)
83 u8 clk_mux_get_parent(struct clk *clk)
85 struct clk_mux *mux = to_clk_mux(clk);
88 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
89 val = mux->io_mux_val;
91 val = readl(mux->reg);
96 return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
99 static int clk_fetch_parent_index(struct clk *clk,
102 struct clk_mux *mux = to_clk_mux(clk);
109 for (i = 0; i < mux->num_parents; i++) {
110 if (!strcmp(parent->dev->name, mux->parent_names[i]))
117 static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
119 struct clk_mux *mux = to_clk_mux(clk);
124 index = clk_fetch_parent_index(clk, parent);
126 printf("Could not fetch index\n");
130 val = clk_mux_index_to_val(mux->table, mux->flags, index);
132 if (mux->flags & CLK_MUX_HIWORD_MASK) {
133 reg = mux->mask << (mux->shift + 16);
135 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
136 reg = mux->io_mux_val;
138 reg = readl(mux->reg);
140 reg &= ~(mux->mask << mux->shift);
142 val = val << mux->shift;
144 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
145 mux->io_mux_val = reg;
147 writel(reg, mux->reg);
153 static ulong clk_mux_get_rate(struct clk *clk)
155 struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
156 dev_get_clk_ptr(clk->dev) : clk);
157 struct udevice *parent;
161 index = clk_mux_get_parent(clk);
162 if (index >= mux->num_parents)
165 err = uclass_get_device_by_name(UCLASS_CLK, mux->parent_names[index],
170 pclk = dev_get_clk_ptr(parent);
174 return clk_get_rate(pclk);
177 const struct clk_ops clk_mux_ops = {
178 .get_rate = clk_mux_get_rate,
179 .set_parent = clk_mux_set_parent,
182 struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
183 const char * const *parent_names, u8 num_parents,
185 void __iomem *reg, u8 shift, u32 mask,
186 u8 clk_mux_flags, u32 *table)
193 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
194 width = fls(mask) - ffs(mask) + 1;
195 if (width + shift > 16) {
196 pr_err("mux value exceeds LOWORD field\n");
197 return ERR_PTR(-EINVAL);
201 /* allocate the mux */
202 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
204 return ERR_PTR(-ENOMEM);
206 /* U-boot specific assignments */
207 mux->parent_names = parent_names;
208 mux->num_parents = num_parents;
210 /* struct clk_mux assignments */
214 mux->flags = clk_mux_flags;
216 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
217 mux->io_mux_val = *(u32 *)reg;
224 * Read the current mux setup - so we assign correct parent.
226 * Changing parent would require changing internals of udevice struct
227 * for the corresponding clock (to do that define .set_parent() method).
229 ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
230 parent_names[clk_mux_get_parent(clk)]);
239 struct clk *clk_register_mux_table(struct device *dev, const char *name,
240 const char * const *parent_names, u8 num_parents,
242 void __iomem *reg, u8 shift, u32 mask,
243 u8 clk_mux_flags, u32 *table)
247 clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
248 flags, reg, shift, mask, clk_mux_flags,
251 return ERR_CAST(clk);
255 struct clk *clk_register_mux(struct device *dev, const char *name,
256 const char * const *parent_names, u8 num_parents,
258 void __iomem *reg, u8 shift, u8 width,
261 u32 mask = BIT(width) - 1;
263 return clk_register_mux_table(dev, name, parent_names, num_parents,
264 flags, reg, shift, mask, clk_mux_flags,
268 U_BOOT_DRIVER(ccf_clk_mux) = {
269 .name = UBOOT_DM_CLK_CCF_MUX,
272 .flags = DM_FLAG_PRE_RELOC,