drivers/clk/clk-k210.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
   4  * Copyright (c) 2019 Western Digital Corporation or its affiliates.
   5  */
   6 #define pr_fmt(fmt)     "k210-clk: " fmt
   7
   8 #include <linux/io.h>
   9 #include <linux/slab.h>
  10 #include <linux/spinlock.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/of.h>
  13 #include <linux/of_clk.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/of_address.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/delay.h>
  19 #include <soc/canaan/k210-sysctl.h>
  20
  21 #include <dt-bindings/clock/k210-clk.h>
  22
  23 struct k210_sysclk;
  24
  25 struct k210_clk {
  26         int id;
  27         struct k210_sysclk *ksc;
  28         struct clk_hw hw;
  29 };
  30
  31 struct k210_clk_cfg {
  32         const char *name;
  33         u8 gate_reg;
  34         u8 gate_bit;
  35         u8 div_reg;
  36         u8 div_shift;
  37         u8 div_width;
  38         u8 div_type;
  39         u8 mux_reg;
  40         u8 mux_bit;
  41 };
  42
  43 enum k210_clk_div_type {
  44         K210_DIV_NONE,
  45         K210_DIV_ONE_BASED,
  46         K210_DIV_DOUBLE_ONE_BASED,
  47         K210_DIV_POWER_OF_TWO,
  48 };
  49
  50 #define K210_GATE(_reg, _bit)   \
  51         .gate_reg = (_reg),     \
  52         .gate_bit = (_bit)
  53
  54 #define K210_DIV(_reg, _shift, _width, _type)   \
  55         .div_reg = (_reg),                      \
  56         .div_shift = (_shift),                  \
  57         .div_width = (_width),                  \
  58         .div_type = (_type)
  59
  60 #define K210_MUX(_reg, _bit)    \
  61         .mux_reg = (_reg),      \
  62         .mux_bit = (_bit)
  63
  64 static struct k210_clk_cfg k210_clk_cfgs[K210_NUM_CLKS] = {
  65         /* Gated clocks, no mux, no divider */
  66         [K210_CLK_CPU] = {
  67                 .name = "cpu",
  68                 K210_GATE(K210_SYSCTL_EN_CENT, 0)
  69         },
  70         [K210_CLK_DMA] = {
  71                 .name = "dma",
  72                 K210_GATE(K210_SYSCTL_EN_PERI, 1)
  73         },
  74         [K210_CLK_FFT] = {
  75                 .name = "fft",
  76                 K210_GATE(K210_SYSCTL_EN_PERI, 4)
  77         },
  78         [K210_CLK_GPIO] = {
  79                 .name = "gpio",
  80                 K210_GATE(K210_SYSCTL_EN_PERI, 5)
  81         },
  82         [K210_CLK_UART1] = {
  83                 .name = "uart1",
  84                 K210_GATE(K210_SYSCTL_EN_PERI, 16)
  85         },
  86         [K210_CLK_UART2] = {
  87                 .name = "uart2",
  88                 K210_GATE(K210_SYSCTL_EN_PERI, 17)
  89         },
  90         [K210_CLK_UART3] = {
  91                 .name = "uart3",
  92                 K210_GATE(K210_SYSCTL_EN_PERI, 18)
  93         },
  94         [K210_CLK_FPIOA] = {
  95                 .name = "fpioa",
  96                 K210_GATE(K210_SYSCTL_EN_PERI, 20)
  97         },
  98         [K210_CLK_SHA] = {
  99                 .name = "sha",
 100                 K210_GATE(K210_SYSCTL_EN_PERI, 26)
 101         },
 102         [K210_CLK_AES] = {
 103                 .name = "aes",
 104                 K210_GATE(K210_SYSCTL_EN_PERI, 19)
 105         },
 106         [K210_CLK_OTP] = {
 107                 .name = "otp",
 108                 K210_GATE(K210_SYSCTL_EN_PERI, 27)
 109         },
 110         [K210_CLK_RTC] = {
 111                 .name = "rtc",
 112                 K210_GATE(K210_SYSCTL_EN_PERI, 29)
 113         },
 114
 115         /* Gated divider clocks */
 116         [K210_CLK_SRAM0] = {
 117                 .name = "sram0",
 118                 K210_GATE(K210_SYSCTL_EN_CENT, 1),
 119                 K210_DIV(K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE_BASED)
 120         },
 121         [K210_CLK_SRAM1] = {
 122                 .name = "sram1",
 123                 K210_GATE(K210_SYSCTL_EN_CENT, 2),
 124                 K210_DIV(K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE_BASED)
 125         },
 126         [K210_CLK_ROM] = {
 127                 .name = "rom",
 128                 K210_GATE(K210_SYSCTL_EN_PERI, 0),
 129                 K210_DIV(K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE_BASED)
 130         },
 131         [K210_CLK_DVP] = {
 132                 .name = "dvp",
 133                 K210_GATE(K210_SYSCTL_EN_PERI, 3),
 134                 K210_DIV(K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE_BASED)
 135         },
 136         [K210_CLK_APB0] = {
 137                 .name = "apb0",
 138                 K210_GATE(K210_SYSCTL_EN_CENT, 3),
 139                 K210_DIV(K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE_BASED)
 140         },
 141         [K210_CLK_APB1] = {
 142                 .name = "apb1",
 143                 K210_GATE(K210_SYSCTL_EN_CENT, 4),
 144                 K210_DIV(K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE_BASED)
 145         },
 146         [K210_CLK_APB2] = {
 147                 .name = "apb2",
 148                 K210_GATE(K210_SYSCTL_EN_CENT, 5),
 149                 K210_DIV(K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE_BASED)
 150         },
 151         [K210_CLK_AI] = {
 152                 .name = "ai",
 153                 K210_GATE(K210_SYSCTL_EN_PERI, 2),
 154                 K210_DIV(K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE_BASED)
 155         },
 156         [K210_CLK_SPI0] = {
 157                 .name = "spi0",
 158                 K210_GATE(K210_SYSCTL_EN_PERI, 6),
 159                 K210_DIV(K210_SYSCTL_THR1, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
 160         },
 161         [K210_CLK_SPI1] = {
 162                 .name = "spi1",
 163                 K210_GATE(K210_SYSCTL_EN_PERI, 7),
 164                 K210_DIV(K210_SYSCTL_THR1, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
 165         },
 166         [K210_CLK_SPI2] = {
 167                 .name = "spi2",
 168                 K210_GATE(K210_SYSCTL_EN_PERI, 8),
 169                 K210_DIV(K210_SYSCTL_THR1, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
 170         },
 171         [K210_CLK_I2C0] = {
 172                 .name = "i2c0",
 173                 K210_GATE(K210_SYSCTL_EN_PERI, 13),
 174                 K210_DIV(K210_SYSCTL_THR5, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
 175         },
 176         [K210_CLK_I2C1] = {
 177                 .name = "i2c1",
 178                 K210_GATE(K210_SYSCTL_EN_PERI, 14),
 179                 K210_DIV(K210_SYSCTL_THR5, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
 180         },
 181         [K210_CLK_I2C2] = {
 182                 .name = "i2c2",
 183                 K210_GATE(K210_SYSCTL_EN_PERI, 15),
 184                 K210_DIV(K210_SYSCTL_THR5, 24, 8, K210_DIV_DOUBLE_ONE_BASED)
 185         },
 186         [K210_CLK_WDT0] = {
 187                 .name = "wdt0",
 188                 K210_GATE(K210_SYSCTL_EN_PERI, 24),
 189                 K210_DIV(K210_SYSCTL_THR6, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
 190         },
 191         [K210_CLK_WDT1] = {
 192                 .name = "wdt1",
 193                 K210_GATE(K210_SYSCTL_EN_PERI, 25),
 194                 K210_DIV(K210_SYSCTL_THR6, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
 195         },
 196         [K210_CLK_I2S0] = {
 197                 .name = "i2s0",
 198                 K210_GATE(K210_SYSCTL_EN_PERI, 10),
 199                 K210_DIV(K210_SYSCTL_THR3, 0, 16, K210_DIV_DOUBLE_ONE_BASED)
 200         },
 201         [K210_CLK_I2S1] = {
 202                 .name = "i2s1",
 203                 K210_GATE(K210_SYSCTL_EN_PERI, 11),
 204                 K210_DIV(K210_SYSCTL_THR3, 16, 16, K210_DIV_DOUBLE_ONE_BASED)
 205         },
 206         [K210_CLK_I2S2] = {
 207                 .name = "i2s2",
 208                 K210_GATE(K210_SYSCTL_EN_PERI, 12),
 209                 K210_DIV(K210_SYSCTL_THR4, 0, 16, K210_DIV_DOUBLE_ONE_BASED)
 210         },
 211
 212         /* Divider clocks, no gate, no mux */
 213         [K210_CLK_I2S0_M] = {
 214                 .name = "i2s0_m",
 215                 K210_DIV(K210_SYSCTL_THR4, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
 216         },
 217         [K210_CLK_I2S1_M] = {
 218                 .name = "i2s1_m",
 219                 K210_DIV(K210_SYSCTL_THR4, 24, 8, K210_DIV_DOUBLE_ONE_BASED)
 220         },
 221         [K210_CLK_I2S2_M] = {
 222                 .name = "i2s2_m",
 223                 K210_DIV(K210_SYSCTL_THR4, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
 224         },
 225
 226         /* Muxed gated divider clocks */
 227         [K210_CLK_SPI3] = {
 228                 .name = "spi3",
 229                 K210_GATE(K210_SYSCTL_EN_PERI, 9),
 230                 K210_DIV(K210_SYSCTL_THR1, 24, 8, K210_DIV_DOUBLE_ONE_BASED),
 231                 K210_MUX(K210_SYSCTL_SEL0, 12)
 232         },
 233         [K210_CLK_TIMER0] = {
 234                 .name = "timer0",
 235                 K210_GATE(K210_SYSCTL_EN_PERI, 21),
 236                 K210_DIV(K210_SYSCTL_THR2,  0, 8, K210_DIV_DOUBLE_ONE_BASED),
 237                 K210_MUX(K210_SYSCTL_SEL0, 13)
 238         },
 239         [K210_CLK_TIMER1] = {
 240                 .name = "timer1",
 241                 K210_GATE(K210_SYSCTL_EN_PERI, 22),
 242                 K210_DIV(K210_SYSCTL_THR2, 8, 8, K210_DIV_DOUBLE_ONE_BASED),
 243                 K210_MUX(K210_SYSCTL_SEL0, 14)
 244         },
 245         [K210_CLK_TIMER2] = {
 246                 .name = "timer2",
 247                 K210_GATE(K210_SYSCTL_EN_PERI, 23),
 248                 K210_DIV(K210_SYSCTL_THR2, 16, 8, K210_DIV_DOUBLE_ONE_BASED),
 249                 K210_MUX(K210_SYSCTL_SEL0, 15)
 250         },
 251 };
 252
 253 /*
 254  * PLL control register bits.
 255  */
 256 #define K210_PLL_CLKR           GENMASK(3, 0)
 257 #define K210_PLL_CLKF           GENMASK(9, 4)
 258 #define K210_PLL_CLKOD          GENMASK(13, 10)
 259 #define K210_PLL_BWADJ          GENMASK(19, 14)
 260 #define K210_PLL_RESET          (1 << 20)
 261 #define K210_PLL_PWRD           (1 << 21)
 262 #define K210_PLL_INTFB          (1 << 22)
 263 #define K210_PLL_BYPASS         (1 << 23)
 264 #define K210_PLL_TEST           (1 << 24)
 265 #define K210_PLL_EN             (1 << 25)
 266 #define K210_PLL_SEL            GENMASK(27, 26) /* PLL2 only */
 267
 268 /*
 269  * PLL lock register bits.
 270  */
 271 #define K210_PLL_LOCK           0
 272 #define K210_PLL_CLEAR_SLIP     2
 273 #define K210_PLL_TEST_OUT       3
 274
 275 /*
 276  * Clock selector register bits.
 277  */
 278 #define K210_ACLK_SEL           BIT(0)
 279 #define K210_ACLK_DIV           GENMASK(2, 1)
 280
 281 /*
 282  * PLLs.
 283  */
 284 enum k210_pll_id {
 285         K210_PLL0, K210_PLL1, K210_PLL2, K210_PLL_NUM
 286 };
 287
 288 struct k210_pll {
 289         enum k210_pll_id id;
 290         struct k210_sysclk *ksc;
 291         void __iomem *base;
 292         void __iomem *reg;
 293         void __iomem *lock;
 294         u8 lock_shift;
 295         u8 lock_width;
 296         struct clk_hw hw;
 297 };
 298 #define to_k210_pll(_hw)        container_of(_hw, struct k210_pll, hw)
 299
 300 /*
 301  * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
 302  * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
 303  * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the
 304  * same clock as the first 2.
 305  */
 306 struct k210_pll_cfg {
 307         u32 reg;
 308         u8 lock_shift;
 309         u8 lock_width;
 310         u32 r;
 311         u32 f;
 312         u32 od;
 313         u32 bwadj;
 314 };
 315
 316 static struct k210_pll_cfg k210_plls_cfg[] = {
 317         { K210_SYSCTL_PLL0,  0, 2, 0, 59, 1, 59 }, /* 780 MHz */
 318         { K210_SYSCTL_PLL1,  8, 1, 0, 59, 3, 59 }, /* 390 MHz */
 319         { K210_SYSCTL_PLL2, 16, 1, 0, 22, 1, 22 }, /* 299 MHz */
 320 };
 321
 322 /**
 323  * struct k210_sysclk - sysclk driver data
 324  * @regs: system controller registers start address
 325  * @clk_lock: clock setting spinlock
 326  * @plls: SoC PLLs descriptors
 327  * @aclk: ACLK clock
 328  * @clks: All other clocks
 329  */
 330 struct k210_sysclk {
 331         void __iomem                    *regs;
 332         spinlock_t                      clk_lock;
 333         struct k210_pll                 plls[K210_PLL_NUM];
 334         struct clk_hw                   aclk;
 335         struct k210_clk                 clks[K210_NUM_CLKS];
 336 };
 337
 338 #define to_k210_sysclk(_hw)     container_of(_hw, struct k210_sysclk, aclk)
 339
 340 /*
 341  * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
 342  */
 343 static void k210_aclk_set_selector(void __iomem *regs, u8 sel)
 344 {
 345         u32 reg = readl(regs + K210_SYSCTL_SEL0);
 346
 347         if (sel)
 348                 reg |= K210_ACLK_SEL;
 349         else
 350                 reg &= K210_ACLK_SEL;
 351         writel(reg, regs + K210_SYSCTL_SEL0);
 352 }
 353
 354 static void k210_init_pll(void __iomem *regs, enum k210_pll_id pllid,
 355                           struct k210_pll *pll)
 356 {
 357         pll->id = pllid;
 358         pll->reg = regs + k210_plls_cfg[pllid].reg;
 359         pll->lock = regs + K210_SYSCTL_PLL_LOCK;
 360         pll->lock_shift = k210_plls_cfg[pllid].lock_shift;
 361         pll->lock_width = k210_plls_cfg[pllid].lock_width;
 362 }
 363
 364 static void k210_pll_wait_for_lock(struct k210_pll *pll)
 365 {
 366         u32 reg, mask = GENMASK(pll->lock_shift + pll->lock_width - 1,
 367                                 pll->lock_shift);
 368
 369         while (true) {
 370                 reg = readl(pll->lock);
 371                 if ((reg & mask) == mask)
 372                         break;
 373
 374                 reg |= BIT(pll->lock_shift + K210_PLL_CLEAR_SLIP);
 375                 writel(reg, pll->lock);
 376         }
 377 }
 378
 379 static bool k210_pll_hw_is_enabled(struct k210_pll *pll)
 380 {
 381         u32 reg = readl(pll->reg);
 382         u32 mask = K210_PLL_PWRD | K210_PLL_EN;
 383
 384         if (reg & K210_PLL_RESET)
 385                 return false;
 386
 387         return (reg & mask) == mask;
 388 }
 389
 390 static void k210_pll_enable_hw(void __iomem *regs, struct k210_pll *pll)
 391 {
 392         struct k210_pll_cfg *pll_cfg = &k210_plls_cfg[pll->id];
 393         u32 reg;
 394
 395         if (k210_pll_hw_is_enabled(pll))
 396                 return;
 397
 398         /*
 399          * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and
 400          * SRAM running.
 401          */
 402         if (pll->id == K210_PLL0)
 403                 k210_aclk_set_selector(regs, 0);
 404
 405         /* Set PLL factors */
 406         reg = readl(pll->reg);
 407         reg &= ~GENMASK(19, 0);
 408         reg |= FIELD_PREP(K210_PLL_CLKR, pll_cfg->r);
 409         reg |= FIELD_PREP(K210_PLL_CLKF, pll_cfg->f);
 410         reg |= FIELD_PREP(K210_PLL_CLKOD, pll_cfg->od);
 411         reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj);
 412         reg |= K210_PLL_PWRD;
 413         writel(reg, pll->reg);
 414
 415         /*
 416          * Reset the PLL: ensure reset is low before asserting it.
 417          * The magic NOPs come from the Kendryte reference SDK.
 418          */
 419         reg &= ~K210_PLL_RESET;
 420         writel(reg, pll->reg);
 421         reg |= K210_PLL_RESET;
 422         writel(reg, pll->reg);
 423         nop();
 424         nop();
 425         reg &= ~K210_PLL_RESET;
 426         writel(reg, pll->reg);
 427
 428         k210_pll_wait_for_lock(pll);
 429
 430         reg &= ~K210_PLL_BYPASS;
 431         reg |= K210_PLL_EN;
 432         writel(reg, pll->reg);
 433
 434         if (pll->id == K210_PLL0)
 435                 k210_aclk_set_selector(regs, 1);
 436 }
 437
 438 static int k210_pll_enable(struct clk_hw *hw)
 439 {
 440         struct k210_pll *pll = to_k210_pll(hw);
 441         struct k210_sysclk *ksc = pll->ksc;
 442         unsigned long flags;
 443
 444         spin_lock_irqsave(&ksc->clk_lock, flags);
 445
 446         k210_pll_enable_hw(ksc->regs, pll);
 447
 448         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 449
 450         return 0;
 451 }
 452
 453 static void k210_pll_disable(struct clk_hw *hw)
 454 {
 455         struct k210_pll *pll = to_k210_pll(hw);
 456         struct k210_sysclk *ksc = pll->ksc;
 457         unsigned long flags;
 458         u32 reg;
 459
 460         /*
 461          * Bypassing before powering off is important so child clocks do not
 462          * stop working. This is especially important for pll0, the indirect
 463          * parent of the cpu clock.
 464          */
 465         spin_lock_irqsave(&ksc->clk_lock, flags);
 466         reg = readl(pll->reg);
 467         reg |= K210_PLL_BYPASS;
 468         writel(reg, pll->reg);
 469
 470         reg &= ~K210_PLL_PWRD;
 471         reg &= ~K210_PLL_EN;
 472         writel(reg, pll->reg);
 473         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 474 }
 475
 476 static int k210_pll_is_enabled(struct clk_hw *hw)
 477 {
 478         return k210_pll_hw_is_enabled(to_k210_pll(hw));
 479 }
 480
 481 static unsigned long k210_pll_get_rate(struct clk_hw *hw,
 482                                        unsigned long parent_rate)
 483 {
 484         struct k210_pll *pll = to_k210_pll(hw);
 485         u32 reg = readl(pll->reg);
 486         u32 r, f, od;
 487
 488         if (reg & K210_PLL_BYPASS)
 489                 return parent_rate;
 490
 491         if (!(reg & K210_PLL_PWRD))
 492                 return 0;
 493
 494         r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
 495         f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
 496         od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
 497
 498         return div_u64((u64)parent_rate * f, r * od);
 499 }
 500
 501 static const struct clk_ops k210_pll_ops = {
 502         .enable         = k210_pll_enable,
 503         .disable        = k210_pll_disable,
 504         .is_enabled     = k210_pll_is_enabled,
 505         .recalc_rate    = k210_pll_get_rate,
 506 };
 507
 508 static int k210_pll2_set_parent(struct clk_hw *hw, u8 index)
 509 {
 510         struct k210_pll *pll = to_k210_pll(hw);
 511         struct k210_sysclk *ksc = pll->ksc;
 512         unsigned long flags;
 513         u32 reg;
 514
 515         spin_lock_irqsave(&ksc->clk_lock, flags);
 516
 517         reg = readl(pll->reg);
 518         reg &= ~K210_PLL_SEL;
 519         reg |= FIELD_PREP(K210_PLL_SEL, index);
 520         writel(reg, pll->reg);
 521
 522         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 523
 524         return 0;
 525 }
 526
 527 static u8 k210_pll2_get_parent(struct clk_hw *hw)
 528 {
 529         struct k210_pll *pll = to_k210_pll(hw);
 530         u32 reg = readl(pll->reg);
 531
 532         return FIELD_GET(K210_PLL_SEL, reg);
 533 }
 534
 535 static const struct clk_ops k210_pll2_ops = {
 536         .enable         = k210_pll_enable,
 537         .disable        = k210_pll_disable,
 538         .is_enabled     = k210_pll_is_enabled,
 539         .recalc_rate    = k210_pll_get_rate,
 540         .determine_rate = clk_hw_determine_rate_no_reparent,
 541         .set_parent     = k210_pll2_set_parent,
 542         .get_parent     = k210_pll2_get_parent,
 543 };
 544
 545 static int __init k210_register_pll(struct device_node *np,
 546                                     struct k210_sysclk *ksc,
 547                                     enum k210_pll_id pllid, const char *name,
 548                                     int num_parents, const struct clk_ops *ops)
 549 {
 550         struct k210_pll *pll = &ksc->plls[pllid];
 551         struct clk_init_data init = {};
 552         const struct clk_parent_data parent_data[] = {
 553                 { /* .index = 0 for in0 */ },
 554                 { .hw = &ksc->plls[K210_PLL0].hw },
 555                 { .hw = &ksc->plls[K210_PLL1].hw },
 556         };
 557
 558         init.name = name;
 559         init.parent_data = parent_data;
 560         init.num_parents = num_parents;
 561         init.ops = ops;
 562
 563         pll->hw.init = &init;
 564         pll->ksc = ksc;
 565
 566         return of_clk_hw_register(np, &pll->hw);
 567 }
 568
 569 static int __init k210_register_plls(struct device_node *np,
 570                                      struct k210_sysclk *ksc)
 571 {
 572         int i, ret;
 573
 574         for (i = 0; i < K210_PLL_NUM; i++)
 575                 k210_init_pll(ksc->regs, i, &ksc->plls[i]);
 576
 577         /* PLL0 and PLL1 only have IN0 as parent */
 578         ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops);
 579         if (ret) {
 580                 pr_err("%pOFP: register PLL0 failed\n", np);
 581                 return ret;
 582         }
 583         ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops);
 584         if (ret) {
 585                 pr_err("%pOFP: register PLL1 failed\n", np);
 586                 return ret;
 587         }
 588
 589         /* PLL2 has IN0, PLL0 and PLL1 as parents */
 590         ret = k210_register_pll(np, ksc, K210_PLL2, "pll2", 3, &k210_pll2_ops);
 591         if (ret) {
 592                 pr_err("%pOFP: register PLL2 failed\n", np);
 593                 return ret;
 594         }
 595
 596         return 0;
 597 }
 598
 599 static int k210_aclk_set_parent(struct clk_hw *hw, u8 index)
 600 {
 601         struct k210_sysclk *ksc = to_k210_sysclk(hw);
 602         unsigned long flags;
 603
 604         spin_lock_irqsave(&ksc->clk_lock, flags);
 605
 606         k210_aclk_set_selector(ksc->regs, index);
 607
 608         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 609
 610         return 0;
 611 }
 612
 613 static u8 k210_aclk_get_parent(struct clk_hw *hw)
 614 {
 615         struct k210_sysclk *ksc = to_k210_sysclk(hw);
 616         u32 sel;
 617
 618         sel = readl(ksc->regs + K210_SYSCTL_SEL0) & K210_ACLK_SEL;
 619
 620         return sel ? 1 : 0;
 621 }
 622
 623 static unsigned long k210_aclk_get_rate(struct clk_hw *hw,
 624                                         unsigned long parent_rate)
 625 {
 626         struct k210_sysclk *ksc = to_k210_sysclk(hw);
 627         u32 reg = readl(ksc->regs + K210_SYSCTL_SEL0);
 628         unsigned int shift;
 629
 630         if (!(reg & 0x1))
 631                 return parent_rate;
 632
 633         shift = FIELD_GET(K210_ACLK_DIV, reg);
 634
 635         return parent_rate / (2UL << shift);
 636 }
 637
 638 static const struct clk_ops k210_aclk_ops = {
 639         .determine_rate = clk_hw_determine_rate_no_reparent,
 640         .set_parent     = k210_aclk_set_parent,
 641         .get_parent     = k210_aclk_get_parent,
 642         .recalc_rate    = k210_aclk_get_rate,
 643 };
 644
 645 /*
 646  * ACLK has IN0 and PLL0 as parents.
 647  */
 648 static int __init k210_register_aclk(struct device_node *np,
 649                                      struct k210_sysclk *ksc)
 650 {
 651         struct clk_init_data init = {};
 652         const struct clk_parent_data parent_data[] = {
 653                 { /* .index = 0 for in0 */ },
 654                 { .hw = &ksc->plls[K210_PLL0].hw },
 655         };
 656         int ret;
 657
 658         init.name = "aclk";
 659         init.parent_data = parent_data;
 660         init.num_parents = 2;
 661         init.ops = &k210_aclk_ops;
 662         ksc->aclk.init = &init;
 663
 664         ret = of_clk_hw_register(np, &ksc->aclk);
 665         if (ret) {
 666                 pr_err("%pOFP: register aclk failed\n", np);
 667                 return ret;
 668         }
 669
 670         return 0;
 671 }
 672
 673 #define to_k210_clk(_hw)        container_of(_hw, struct k210_clk, hw)
 674
 675 static int k210_clk_enable(struct clk_hw *hw)
 676 {
 677         struct k210_clk *kclk = to_k210_clk(hw);
 678         struct k210_sysclk *ksc = kclk->ksc;
 679         struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
 680         unsigned long flags;
 681         u32 reg;
 682
 683         if (!cfg->gate_reg)
 684                 return 0;
 685
 686         spin_lock_irqsave(&ksc->clk_lock, flags);
 687         reg = readl(ksc->regs + cfg->gate_reg);
 688         reg |= BIT(cfg->gate_bit);
 689         writel(reg, ksc->regs + cfg->gate_reg);
 690         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 691
 692         return 0;
 693 }
 694
 695 static void k210_clk_disable(struct clk_hw *hw)
 696 {
 697         struct k210_clk *kclk = to_k210_clk(hw);
 698         struct k210_sysclk *ksc = kclk->ksc;
 699         struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
 700         unsigned long flags;
 701         u32 reg;
 702
 703         if (!cfg->gate_reg)
 704                 return;
 705
 706         spin_lock_irqsave(&ksc->clk_lock, flags);
 707         reg = readl(ksc->regs + cfg->gate_reg);
 708         reg &= ~BIT(cfg->gate_bit);
 709         writel(reg, ksc->regs + cfg->gate_reg);
 710         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 711 }
 712
 713 static int k210_clk_set_parent(struct clk_hw *hw, u8 index)
 714 {
 715         struct k210_clk *kclk = to_k210_clk(hw);
 716         struct k210_sysclk *ksc = kclk->ksc;
 717         struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
 718         unsigned long flags;
 719         u32 reg;
 720
 721         spin_lock_irqsave(&ksc->clk_lock, flags);
 722         reg = readl(ksc->regs + cfg->mux_reg);
 723         if (index)
 724                 reg |= BIT(cfg->mux_bit);
 725         else
 726                 reg &= ~BIT(cfg->mux_bit);
 727         writel(reg, ksc->regs + cfg->mux_reg);
 728         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 729
 730         return 0;
 731 }
 732
 733 static u8 k210_clk_get_parent(struct clk_hw *hw)
 734 {
 735         struct k210_clk *kclk = to_k210_clk(hw);
 736         struct k210_sysclk *ksc = kclk->ksc;
 737         struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
 738         unsigned long flags;
 739         u32 reg, idx;
 740
 741         spin_lock_irqsave(&ksc->clk_lock, flags);
 742         reg = readl(ksc->regs + cfg->mux_reg);
 743         idx = (reg & BIT(cfg->mux_bit)) ? 1 : 0;
 744         spin_unlock_irqrestore(&ksc->clk_lock, flags);
 745
 746         return idx;
 747 }
 748
 749 static unsigned long k210_clk_get_rate(struct clk_hw *hw,
 750                                        unsigned long parent_rate)
 751 {
 752         struct k210_clk *kclk = to_k210_clk(hw);
 753         struct k210_sysclk *ksc = kclk->ksc;
 754         struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
 755         u32 reg, div_val;
 756
 757         if (!cfg->div_reg)
 758                 return parent_rate;
 759
 760         reg = readl(ksc->regs + cfg->div_reg);
 761         div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0);
 762
 763         switch (cfg->div_type) {
 764         case K210_DIV_ONE_BASED:
 765                 return parent_rate / (div_val + 1);
 766         case K210_DIV_DOUBLE_ONE_BASED:
 767                 return parent_rate / ((div_val + 1) * 2);
 768         case K210_DIV_POWER_OF_TWO:
 769                 return parent_rate / (2UL << div_val);
 770         case K210_DIV_NONE:
 771         default:
 772                 return 0;
 773         }
 774 }
 775
 776 static const struct clk_ops k210_clk_mux_ops = {
 777         .enable         = k210_clk_enable,
 778         .disable        = k210_clk_disable,
 779         .determine_rate = clk_hw_determine_rate_no_reparent,
 780         .set_parent     = k210_clk_set_parent,
 781         .get_parent     = k210_clk_get_parent,
 782         .recalc_rate    = k210_clk_get_rate,
 783 };
 784
 785 static const struct clk_ops k210_clk_ops = {
 786         .enable         = k210_clk_enable,
 787         .disable        = k210_clk_disable,
 788         .recalc_rate    = k210_clk_get_rate,
 789 };
 790
 791 static void __init k210_register_clk(struct device_node *np,
 792                                      struct k210_sysclk *ksc, int id,
 793                                      const struct clk_parent_data *parent_data,
 794                                      int num_parents, unsigned long flags)
 795 {
 796         struct k210_clk *kclk = &ksc->clks[id];
 797         struct clk_init_data init = {};
 798         int ret;
 799
 800         init.name = k210_clk_cfgs[id].name;
 801         init.flags = flags;
 802         init.parent_data = parent_data;
 803         init.num_parents = num_parents;
 804         if (num_parents > 1)
 805                 init.ops = &k210_clk_mux_ops;
 806         else
 807                 init.ops = &k210_clk_ops;
 808
 809         kclk->id = id;
 810         kclk->ksc = ksc;
 811         kclk->hw.init = &init;
 812
 813         ret = of_clk_hw_register(np, &kclk->hw);
 814         if (ret) {
 815                 pr_err("%pOFP: register clock %s failed\n",
 816                        np, k210_clk_cfgs[id].name);
 817                 kclk->id = -1;
 818         }
 819 }
 820
 821 /*
 822  * All muxed clocks have IN0 and PLL0 as parents.
 823  */
 824 static inline void __init k210_register_mux_clk(struct device_node *np,
 825                                                 struct k210_sysclk *ksc, int id)
 826 {
 827         const struct clk_parent_data parent_data[2] = {
 828                 { /* .index = 0 for in0 */ },
 829                 { .hw = &ksc->plls[K210_PLL0].hw }
 830         };
 831
 832         k210_register_clk(np, ksc, id, parent_data, 2, 0);
 833 }
 834
 835 static inline void __init k210_register_in0_child(struct device_node *np,
 836                                                 struct k210_sysclk *ksc, int id)
 837 {
 838         const struct clk_parent_data parent_data = {
 839                 /* .index = 0 for in0 */
 840         };
 841
 842         k210_register_clk(np, ksc, id, &parent_data, 1, 0);
 843 }
 844
 845 static inline void __init k210_register_pll_child(struct device_node *np,
 846                                                 struct k210_sysclk *ksc, int id,
 847                                                 enum k210_pll_id pllid,
 848                                                 unsigned long flags)
 849 {
 850         const struct clk_parent_data parent_data = {
 851                 .hw = &ksc->plls[pllid].hw,
 852         };
 853
 854         k210_register_clk(np, ksc, id, &parent_data, 1, flags);
 855 }
 856
 857 static inline void __init k210_register_aclk_child(struct device_node *np,
 858                                                 struct k210_sysclk *ksc, int id,
 859                                                 unsigned long flags)
 860 {
 861         const struct clk_parent_data parent_data = {
 862                 .hw = &ksc->aclk,
 863         };
 864
 865         k210_register_clk(np, ksc, id, &parent_data, 1, flags);
 866 }
 867
 868 static inline void __init k210_register_clk_child(struct device_node *np,
 869                                                 struct k210_sysclk *ksc, int id,
 870                                                 int parent_id)
 871 {
 872         const struct clk_parent_data parent_data = {
 873                 .hw = &ksc->clks[parent_id].hw,
 874         };
 875
 876         k210_register_clk(np, ksc, id, &parent_data, 1, 0);
 877 }
 878
 879 static struct clk_hw *k210_clk_hw_onecell_get(struct of_phandle_args *clkspec,
 880                                               void *data)
 881 {
 882         struct k210_sysclk *ksc = data;
 883         unsigned int idx = clkspec->args[0];
 884
 885         if (idx >= K210_NUM_CLKS)
 886                 return ERR_PTR(-EINVAL);
 887
 888         return &ksc->clks[idx].hw;
 889 }
 890
 891 static void __init k210_clk_init(struct device_node *np)
 892 {
 893         struct device_node *sysctl_np;
 894         struct k210_sysclk *ksc;
 895         int i, ret;
 896
 897         ksc = kzalloc(sizeof(*ksc), GFP_KERNEL);
 898         if (!ksc)
 899                 return;
 900
 901         spin_lock_init(&ksc->clk_lock);
 902         sysctl_np = of_get_parent(np);
 903         ksc->regs = of_iomap(sysctl_np, 0);
 904         of_node_put(sysctl_np);
 905         if (!ksc->regs) {
 906                 pr_err("%pOFP: failed to map registers\n", np);
 907                 return;
 908         }
 909
 910         ret = k210_register_plls(np, ksc);
 911         if (ret)
 912                 return;
 913
 914         ret = k210_register_aclk(np, ksc);
 915         if (ret)
 916                 return;
 917
 918         /*
 919          * Critical clocks: there are no consumers of the SRAM clocks,
 920          * including the AI clock for the third SRAM bank. The CPU clock
 921          * is only referenced by the uarths serial device and so would be
 922          * disabled if the serial console is disabled to switch to another
 923          * console. Mark all these clocks as critical so that they are never
 924          * disabled by the core clock management.
 925          */
 926         k210_register_aclk_child(np, ksc, K210_CLK_CPU, CLK_IS_CRITICAL);
 927         k210_register_aclk_child(np, ksc, K210_CLK_SRAM0, CLK_IS_CRITICAL);
 928         k210_register_aclk_child(np, ksc, K210_CLK_SRAM1, CLK_IS_CRITICAL);
 929         k210_register_pll_child(np, ksc, K210_CLK_AI, K210_PLL1,
 930                                 CLK_IS_CRITICAL);
 931
 932         /* Clocks with aclk as source */
 933         k210_register_aclk_child(np, ksc, K210_CLK_DMA, 0);
 934         k210_register_aclk_child(np, ksc, K210_CLK_FFT, 0);
 935         k210_register_aclk_child(np, ksc, K210_CLK_ROM, 0);
 936         k210_register_aclk_child(np, ksc, K210_CLK_DVP, 0);
 937         k210_register_aclk_child(np, ksc, K210_CLK_APB0, 0);
 938         k210_register_aclk_child(np, ksc, K210_CLK_APB1, 0);
 939         k210_register_aclk_child(np, ksc, K210_CLK_APB2, 0);
 940
 941         /* Clocks with PLL0 as source */
 942         k210_register_pll_child(np, ksc, K210_CLK_SPI0, K210_PLL0, 0);
 943         k210_register_pll_child(np, ksc, K210_CLK_SPI1, K210_PLL0, 0);
 944         k210_register_pll_child(np, ksc, K210_CLK_SPI2, K210_PLL0, 0);
 945         k210_register_pll_child(np, ksc, K210_CLK_I2C0, K210_PLL0, 0);
 946         k210_register_pll_child(np, ksc, K210_CLK_I2C1, K210_PLL0, 0);
 947         k210_register_pll_child(np, ksc, K210_CLK_I2C2, K210_PLL0, 0);
 948
 949         /* Clocks with PLL2 as source */
 950         k210_register_pll_child(np, ksc, K210_CLK_I2S0, K210_PLL2, 0);
 951         k210_register_pll_child(np, ksc, K210_CLK_I2S1, K210_PLL2, 0);
 952         k210_register_pll_child(np, ksc, K210_CLK_I2S2, K210_PLL2, 0);
 953         k210_register_pll_child(np, ksc, K210_CLK_I2S0_M, K210_PLL2, 0);
 954         k210_register_pll_child(np, ksc, K210_CLK_I2S1_M, K210_PLL2, 0);
 955         k210_register_pll_child(np, ksc, K210_CLK_I2S2_M, K210_PLL2, 0);
 956
 957         /* Clocks with IN0 as source */
 958         k210_register_in0_child(np, ksc, K210_CLK_WDT0);
 959         k210_register_in0_child(np, ksc, K210_CLK_WDT1);
 960         k210_register_in0_child(np, ksc, K210_CLK_RTC);
 961
 962         /* Clocks with APB0 as source */
 963         k210_register_clk_child(np, ksc, K210_CLK_GPIO, K210_CLK_APB0);
 964         k210_register_clk_child(np, ksc, K210_CLK_UART1, K210_CLK_APB0);
 965         k210_register_clk_child(np, ksc, K210_CLK_UART2, K210_CLK_APB0);
 966         k210_register_clk_child(np, ksc, K210_CLK_UART3, K210_CLK_APB0);
 967         k210_register_clk_child(np, ksc, K210_CLK_FPIOA, K210_CLK_APB0);
 968         k210_register_clk_child(np, ksc, K210_CLK_SHA, K210_CLK_APB0);
 969
 970         /* Clocks with APB1 as source */
 971         k210_register_clk_child(np, ksc, K210_CLK_AES, K210_CLK_APB1);
 972         k210_register_clk_child(np, ksc, K210_CLK_OTP, K210_CLK_APB1);
 973
 974         /* Mux clocks with in0 or pll0 as source */
 975         k210_register_mux_clk(np, ksc, K210_CLK_SPI3);
 976         k210_register_mux_clk(np, ksc, K210_CLK_TIMER0);
 977         k210_register_mux_clk(np, ksc, K210_CLK_TIMER1);
 978         k210_register_mux_clk(np, ksc, K210_CLK_TIMER2);
 979
 980         /* Check for registration errors */
 981         for (i = 0; i < K210_NUM_CLKS; i++) {
 982                 if (ksc->clks[i].id != i)
 983                         return;
 984         }
 985
 986         ret = of_clk_add_hw_provider(np, k210_clk_hw_onecell_get, ksc);
 987         if (ret) {
 988                 pr_err("%pOFP: add clock provider failed %d\n", np, ret);
 989                 return;
 990         }
 991
 992         pr_info("%pOFP: CPU running at %lu MHz\n",
 993                 np, clk_hw_get_rate(&ksc->clks[K210_CLK_CPU].hw) / 1000000);
 994 }
 995
 996 CLK_OF_DECLARE(k210_clk, "canaan,k210-clk", k210_clk_init);
 997
 998 /*
 999  * Enable PLL1 to be able to use the AI SRAM.
1000  */
1001 void __init k210_clk_early_init(void __iomem *regs)
1002 {
1003         struct k210_pll pll1;
1004
1005         /* Make sure ACLK selector is set to PLL0 */
1006         k210_aclk_set_selector(regs, 1);
1007
1008         /* Startup PLL1 to enable the aisram bank for general memory use */
1009         k210_init_pll(regs, K210_PLL1, &pll1);
1010         k210_pll_enable_hw(regs, &pll1);
1011 }