2 * Synopsys HSDK SDP CGU clock driver
4 * Copyright (C) 2017 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
13 #include <clk-uclass.h>
19 * Synopsys ARC HSDK clock tree.
29 * | |-->|CGU_ARC_IDIV|----------->
30 * | |-->|CREG_CORE_IF_DIV|------->
36 * | |-->|CGU_SYS_IDIV_APB|------->
37 * | |-->|CGU_SYS_IDIV_AXI|------->
38 * | |-->|CGU_SYS_IDIV_*|--------->
39 * | |-->|CGU_SYS_IDIV_EBI_REF|--->
45 * | |-->|CGU_TUN_IDIV_TUN|----------->
46 * | |-->|CGU_TUN_IDIV_ROM|----------->
47 * | |-->|CGU_TUN_IDIV_PWM|----------->
53 * |---------------------------->
63 * |-->|CGU_HDMI_IDIV_APB|------>
66 #define CGU_ARC_IDIV 0x080
67 #define CGU_TUN_IDIV_TUN 0x380
68 #define CGU_TUN_IDIV_ROM 0x390
69 #define CGU_TUN_IDIV_PWM 0x3A0
70 #define CGU_TUN_IDIV_TIMER 0x3B0
71 #define CGU_HDMI_IDIV_APB 0x480
72 #define CGU_SYS_IDIV_APB 0x180
73 #define CGU_SYS_IDIV_AXI 0x190
74 #define CGU_SYS_IDIV_ETH 0x1A0
75 #define CGU_SYS_IDIV_USB 0x1B0
76 #define CGU_SYS_IDIV_SDIO 0x1C0
77 #define CGU_SYS_IDIV_HDMI 0x1D0
78 #define CGU_SYS_IDIV_GFX_CORE 0x1E0
79 #define CGU_SYS_IDIV_GFX_DMA 0x1F0
80 #define CGU_SYS_IDIV_GFX_CFG 0x200
81 #define CGU_SYS_IDIV_DMAC_CORE 0x210
82 #define CGU_SYS_IDIV_DMAC_CFG 0x220
83 #define CGU_SYS_IDIV_SDIO_REF 0x230
84 #define CGU_SYS_IDIV_SPI_REF 0x240
85 #define CGU_SYS_IDIV_I2C_REF 0x250
86 #define CGU_SYS_IDIV_UART_REF 0x260
87 #define CGU_SYS_IDIV_EBI_REF 0x270
89 #define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
91 #define CGU_ARC_PLL 0x0
92 #define CGU_SYS_PLL 0x10
93 #define CGU_DDR_PLL 0x20
94 #define CGU_TUN_PLL 0x30
95 #define CGU_HDMI_PLL 0x40
97 #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
98 #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
99 #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
100 #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
102 #define CGU_PLL_CTRL_ODIV_SHIFT 2
103 #define CGU_PLL_CTRL_IDIV_SHIFT 4
104 #define CGU_PLL_CTRL_FBDIV_SHIFT 9
105 #define CGU_PLL_CTRL_BAND_SHIFT 20
107 #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
108 #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
109 #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
111 #define CGU_PLL_CTRL_PD BIT(0)
112 #define CGU_PLL_CTRL_BYPASS BIT(1)
114 #define CGU_PLL_STATUS_LOCK BIT(0)
115 #define CGU_PLL_STATUS_ERR BIT(1)
117 #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
119 #define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
120 #define CORE_IF_CLK_THRESHOLD_HZ 500000000
121 #define CREG_CORE_IF_CLK_DIV_1 0x0
122 #define CREG_CORE_IF_CLK_DIV_2 0x1
124 #define MIN_PLL_RATE 100000000 /* 100 MHz */
125 #define PARENT_RATE_33 33333333 /* fixed clock - xtal */
126 #define PARENT_RATE_27 27000000 /* fixed clock - xtal */
127 #define CGU_MAX_CLOCKS 27
129 #define CGU_SYS_CLOCKS 16
130 #define MAX_AXI_CLOCKS 4
132 #define CGU_TUN_CLOCKS 4
133 #define MAX_TUN_CLOCKS 6
135 struct hsdk_tun_idiv_cfg {
137 u8 val[MAX_TUN_CLOCKS];
140 struct hsdk_tun_clk_cfg {
141 const u32 clk_rate[MAX_TUN_CLOCKS];
142 const u32 pll_rate[MAX_TUN_CLOCKS];
143 const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
146 static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
147 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
148 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
149 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
150 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
151 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
152 { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
156 struct hsdk_sys_idiv_cfg {
158 u8 val[MAX_AXI_CLOCKS];
161 struct hsdk_axi_clk_cfg {
162 const u32 clk_rate[MAX_AXI_CLOCKS];
163 const u32 pll_rate[MAX_AXI_CLOCKS];
164 const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
167 static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
168 { 200000000, 400000000, 600000000, 800000000 },
169 { 800000000, 800000000, 600000000, 800000000 }, {
170 { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
171 { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
172 { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
173 { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
174 { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
175 { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
176 { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
177 { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
178 { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
179 { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
180 { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
181 { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
182 { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
183 { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
184 { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
185 { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
189 struct hsdk_pll_cfg {
197 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
198 { 100000000, 0, 11, 3, 0 },
199 { 125000000, 0, 14, 3, 0 },
200 { 133000000, 0, 15, 3, 0 },
201 { 150000000, 0, 17, 3, 0 },
202 { 200000000, 1, 47, 3, 0 },
203 { 233000000, 1, 27, 2, 0 },
204 { 300000000, 1, 35, 2, 0 },
205 { 333000000, 1, 39, 2, 0 },
206 { 400000000, 1, 47, 2, 0 },
207 { 500000000, 0, 14, 1, 0 },
208 { 600000000, 0, 17, 1, 0 },
209 { 700000000, 0, 20, 1, 0 },
210 { 750000000, 1, 44, 1, 0 },
211 { 800000000, 0, 23, 1, 0 },
212 { 900000000, 1, 26, 0, 0 },
213 { 1000000000, 1, 29, 0, 0 },
214 { 1100000000, 1, 32, 0, 0 },
215 { 1200000000, 1, 35, 0, 0 },
216 { 1300000000, 1, 38, 0, 0 },
217 { 1400000000, 1, 41, 0, 0 },
218 { 1500000000, 1, 44, 0, 0 },
219 { 1600000000, 1, 47, 0, 0 },
223 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
224 { 297000000, 0, 21, 2, 0 },
225 { 540000000, 0, 19, 1, 0 },
226 { 594000000, 0, 21, 1, 0 },
230 struct hsdk_cgu_clk {
231 /* CGU block register */
232 void __iomem *cgu_regs;
233 /* CREG block register */
234 void __iomem *creg_regs;
238 /* PLLs special registers */
239 void __iomem *spec_regs;
241 const struct hsdk_pll_devdata *pll_devdata;
243 /* Dividers registers */
244 void __iomem *idiv_regs;
247 struct hsdk_pll_devdata {
248 const u32 parent_rate;
249 const struct hsdk_pll_cfg *pll_cfg;
250 int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
251 const struct hsdk_pll_cfg *cfg);
254 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
255 const struct hsdk_pll_cfg *);
256 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
257 const struct hsdk_pll_cfg *);
259 static const struct hsdk_pll_devdata core_pll_dat = {
260 .parent_rate = PARENT_RATE_33,
261 .pll_cfg = asdt_pll_cfg,
262 .update_rate = hsdk_pll_core_update_rate,
265 static const struct hsdk_pll_devdata sdt_pll_dat = {
266 .parent_rate = PARENT_RATE_33,
267 .pll_cfg = asdt_pll_cfg,
268 .update_rate = hsdk_pll_comm_update_rate,
271 static const struct hsdk_pll_devdata hdmi_pll_dat = {
272 .parent_rate = PARENT_RATE_27,
273 .pll_cfg = hdmi_pll_cfg,
274 .update_rate = hsdk_pll_comm_update_rate,
277 static ulong idiv_set(struct clk *, ulong);
278 static ulong cpu_clk_set(struct clk *, ulong);
279 static ulong axi_clk_set(struct clk *, ulong);
280 static ulong tun_clk_set(struct clk *, ulong);
281 static ulong idiv_get(struct clk *);
282 static int idiv_off(struct clk *);
283 static ulong pll_set(struct clk *, ulong);
284 static ulong pll_get(struct clk *);
286 struct hsdk_cgu_clock_map {
290 const struct hsdk_pll_devdata *pll_devdata;
291 ulong (*get_rate)(struct clk *clk);
292 ulong (*set_rate)(struct clk *clk, ulong rate);
293 int (*disable)(struct clk *clk);
296 static const struct hsdk_cgu_clock_map clock_map[] = {
297 { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
298 { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
299 { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
300 { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
301 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
302 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
303 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
304 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
305 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
306 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
307 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
308 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
309 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
310 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
311 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
312 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
313 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
314 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
315 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
316 { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
317 { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
318 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
319 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
320 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
321 { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
322 { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
323 { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
326 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
328 iowrite32(val, clk->idiv_regs);
331 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
333 return ioread32(clk->idiv_regs);
336 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
338 iowrite32(val, clk->regs + reg);
341 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
343 return ioread32(clk->regs + reg);
346 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
348 iowrite32(val, clk->spec_regs + reg);
351 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
353 return ioread32(clk->spec_regs + reg);
356 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
357 const struct hsdk_pll_cfg *cfg)
361 /* Powerdown and Bypass bits should be cleared */
362 val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
363 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
364 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
365 val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
367 pr_debug("write configurarion: %#x\n", val);
369 hsdk_pll_write(clk, CGU_PLL_CTRL, val);
372 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
374 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
377 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
379 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
382 static ulong pll_get(struct clk *sclk)
386 u32 idiv, fbdiv, odiv;
387 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
388 u32 parent_rate = clk->pll_devdata->parent_rate;
390 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
392 pr_debug("current configurarion: %#x\n", val);
394 /* Check if PLL is bypassed */
395 if (val & CGU_PLL_CTRL_BYPASS)
398 /* Check if PLL is disabled */
399 if (val & CGU_PLL_CTRL_PD)
402 /* input divider = reg.idiv + 1 */
403 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
404 /* fb divider = 2*(reg.fbdiv + 1) */
405 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
406 /* output divider = 2^(reg.odiv) */
407 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
409 rate = (u64)parent_rate * fbdiv;
410 do_div(rate, idiv * odiv);
415 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
418 unsigned long best_rate;
419 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
420 const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
422 if (pll_cfg[0].rate == 0)
425 best_rate = pll_cfg[0].rate;
427 for (i = 1; pll_cfg[i].rate != 0; i++) {
428 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
429 best_rate = pll_cfg[i].rate;
432 pr_debug("chosen best rate: %lu\n", best_rate);
437 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
439 const struct hsdk_pll_cfg *cfg)
441 hsdk_pll_set_cfg(clk, cfg);
444 * Wait until CGU relocks and check error status.
445 * If after timeout CGU is unlocked yet return error.
447 udelay(HSDK_PLL_MAX_LOCK_TIME);
448 if (!hsdk_pll_is_locked(clk))
451 if (hsdk_pll_is_err(clk))
457 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
459 const struct hsdk_pll_cfg *cfg)
462 * When core clock exceeds 500MHz, the divider for the interface
463 * clock must be programmed to div-by-2.
465 if (rate > CORE_IF_CLK_THRESHOLD_HZ)
466 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
468 hsdk_pll_set_cfg(clk, cfg);
471 * Wait until CGU relocks and check error status.
472 * If after timeout CGU is unlocked yet return error.
474 udelay(HSDK_PLL_MAX_LOCK_TIME);
475 if (!hsdk_pll_is_locked(clk))
478 if (hsdk_pll_is_err(clk))
482 * Program divider to div-by-1 if we succesfuly set core clock below
485 if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
486 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
491 static ulong pll_set(struct clk *sclk, ulong rate)
494 unsigned long best_rate;
495 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
496 const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
498 best_rate = hsdk_pll_round_rate(sclk, rate);
500 for (i = 0; pll_cfg[i].rate != 0; i++) {
501 if (pll_cfg[i].rate == best_rate) {
502 return clk->pll_devdata->update_rate(clk, best_rate,
507 pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
508 clk->pll_devdata->parent_rate);
513 static int idiv_off(struct clk *sclk)
515 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
517 hsdk_idiv_write(clk, 0);
522 static ulong idiv_get(struct clk *sclk)
524 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
525 ulong parent_rate = pll_get(sclk);
526 u32 div_factor = hsdk_idiv_read(clk);
528 div_factor &= CGU_IDIV_MASK;
530 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
535 return parent_rate / div_factor;
538 /* Special behavior: wen we set this clock we set both idiv and pll */
539 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
543 ret = pll_set(sclk, rate);
544 idiv_set(sclk, rate);
549 /* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
550 static ulong axi_clk_set(struct clk *sclk, ulong rate)
552 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
554 int i, freq_idx = -1;
557 pll_rate = pll_get(sclk);
559 for (i = 0; i < MAX_AXI_CLOCKS; i++) {
560 if (axi_clk_cfg.clk_rate[i] == rate) {
567 pr_err("axi clk: invalid rate=%ld Hz\n", rate);
571 /* configure PLL before dividers */
572 if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
573 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
575 /* configure SYS dividers */
576 for (i = 0; i < CGU_SYS_CLOCKS; i++) {
577 clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
578 hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
581 /* configure PLL after dividers */
582 if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
583 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
588 static ulong tun_clk_set(struct clk *sclk, ulong rate)
590 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
592 int i, freq_idx = -1;
595 pll_rate = pll_get(sclk);
597 for (i = 0; i < MAX_TUN_CLOCKS; i++) {
598 if (tun_clk_cfg.clk_rate[i] == rate) {
605 pr_err("tun clk: invalid rate=%ld Hz\n", rate);
609 /* configure PLL before dividers */
610 if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
611 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
613 /* configure SYS dividers */
614 for (i = 0; i < CGU_TUN_CLOCKS; i++) {
615 clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
616 hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
619 /* configure PLL after dividers */
620 if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
621 ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
626 static ulong idiv_set(struct clk *sclk, ulong rate)
628 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
629 ulong parent_rate = pll_get(sclk);
632 div_factor = parent_rate / rate;
633 if (abs(rate - parent_rate / (div_factor + 1)) <=
634 abs(rate - parent_rate / div_factor)) {
638 if (div_factor & ~CGU_IDIV_MASK) {
639 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
640 rate, parent_rate, div_factor, CGU_IDIV_MASK);
642 div_factor = CGU_IDIV_MASK;
645 if (div_factor == 0) {
646 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
647 rate, parent_rate, div_factor);
652 hsdk_idiv_write(clk, div_factor);
657 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
659 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
661 if (sclk->id >= CGU_MAX_CLOCKS)
664 clk->pll_devdata = clock_map[sclk->id].pll_devdata;
665 clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
666 clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
667 clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
672 static ulong hsdk_cgu_get_rate(struct clk *sclk)
674 if (hsdk_prepare_clock_tree_branch(sclk))
677 return clock_map[sclk->id].get_rate(sclk);
680 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
682 if (hsdk_prepare_clock_tree_branch(sclk))
685 return clock_map[sclk->id].set_rate(sclk, rate);
688 static int hsdk_cgu_disable(struct clk *sclk)
690 if (hsdk_prepare_clock_tree_branch(sclk))
693 if (clock_map[sclk->id].disable)
694 return clock_map[sclk->id].disable(sclk);
699 static const struct clk_ops hsdk_cgu_ops = {
700 .set_rate = hsdk_cgu_set_rate,
701 .get_rate = hsdk_cgu_get_rate,
702 .disable = hsdk_cgu_disable,
705 static int hsdk_cgu_clk_probe(struct udevice *dev)
707 struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
709 BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
711 pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
712 if (!pll_clk->cgu_regs)
715 pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
716 if (!pll_clk->creg_regs)
722 static const struct udevice_id hsdk_cgu_clk_id[] = {
723 { .compatible = "snps,hsdk-cgu-clock" },
727 U_BOOT_DRIVER(hsdk_cgu_clk) = {
728 .name = "hsdk-cgu-clk",
730 .of_match = hsdk_cgu_clk_id,
731 .probe = hsdk_cgu_clk_probe,
732 .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
733 .ops = &hsdk_cgu_ops,