2 * Synopsys HSDK SDP CGU clock driver
4 * Copyright (C) 2017 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
13 #include <clk-uclass.h>
17 #include <linux/bug.h>
18 #include <linux/delay.h>
20 #include <asm/arcregs.h>
22 #include <dt-bindings/clock/snps,hsdk-cgu.h>
25 * Synopsys ARC HSDK clock tree.
35 * | |-->|CGU_ARC_IDIV|----------->
36 * | |-->|CREG_CORE_IF_DIV|------->
42 * | |-->|CGU_SYS_IDIV_APB|------->
43 * | |-->|CGU_SYS_IDIV_AXI|------->
44 * | |-->|CGU_SYS_IDIV_*|--------->
45 * | |-->|CGU_SYS_IDIV_EBI_REF|--->
51 * | |-->|CGU_TUN_IDIV_TUN|----------->
52 * | |-->|CGU_TUN_IDIV_ROM|----------->
53 * | |-->|CGU_TUN_IDIV_PWM|----------->
59 * |---------------------------->
69 * |-->|CGU_HDMI_IDIV_APB|------>
72 #define CGU_ARC_IDIV 0x080
73 #define CGU_TUN_IDIV_TUN 0x380
74 #define CGU_TUN_IDIV_ROM 0x390
75 #define CGU_TUN_IDIV_PWM 0x3A0
76 #define CGU_TUN_IDIV_TIMER 0x3B0
77 #define CGU_HDMI_IDIV_APB 0x480
78 #define CGU_SYS_IDIV_APB 0x180
79 #define CGU_SYS_IDIV_AXI 0x190
80 #define CGU_SYS_IDIV_ETH 0x1A0
81 #define CGU_SYS_IDIV_USB 0x1B0
82 #define CGU_SYS_IDIV_SDIO 0x1C0
83 #define CGU_SYS_IDIV_HDMI 0x1D0
84 #define CGU_SYS_IDIV_GFX_CORE 0x1E0
85 #define CGU_SYS_IDIV_GFX_DMA 0x1F0
86 #define CGU_SYS_IDIV_GFX_CFG 0x200
87 #define CGU_SYS_IDIV_DMAC_CORE 0x210
88 #define CGU_SYS_IDIV_DMAC_CFG 0x220
89 #define CGU_SYS_IDIV_SDIO_REF 0x230
90 #define CGU_SYS_IDIV_SPI_REF 0x240
91 #define CGU_SYS_IDIV_I2C_REF 0x250
92 #define CGU_SYS_IDIV_UART_REF 0x260
93 #define CGU_SYS_IDIV_EBI_REF 0x270
95 #define CGU_IDIV_MASK 0xFF /* All idiv have 8 significant bits */
97 #define CGU_ARC_PLL 0x0
98 #define CGU_SYS_PLL 0x10
99 #define CGU_DDR_PLL 0x20
100 #define CGU_TUN_PLL 0x30
101 #define CGU_HDMI_PLL 0x40
103 #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
104 #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
105 #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
106 #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
108 #define CGU_PLL_CTRL_ODIV_SHIFT 2
109 #define CGU_PLL_CTRL_IDIV_SHIFT 4
110 #define CGU_PLL_CTRL_FBDIV_SHIFT 9
111 #define CGU_PLL_CTRL_BAND_SHIFT 20
113 #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
114 #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
115 #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
117 #define CGU_PLL_CTRL_PD BIT(0)
118 #define CGU_PLL_CTRL_BYPASS BIT(1)
120 #define CGU_PLL_STATUS_LOCK BIT(0)
121 #define CGU_PLL_STATUS_ERR BIT(1)
123 #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
125 #define CREG_CORE_IF_DIV 0x000 /* ARC CORE interface divider */
126 #define CORE_IF_CLK_THRESHOLD_HZ 500000000
127 #define CREG_CORE_IF_CLK_DIV_1 0x0
128 #define CREG_CORE_IF_CLK_DIV_2 0x1
130 #define MIN_PLL_RATE 100000000 /* 100 MHz */
131 #define PARENT_RATE_33 33333333 /* fixed clock - xtal */
132 #define PARENT_RATE_27 27000000 /* fixed clock - xtal */
133 #define CGU_MAX_CLOCKS 27
135 #define MAX_FREQ_VARIATIONS 6
137 struct hsdk_idiv_cfg {
139 const u8 val[MAX_FREQ_VARIATIONS];
142 struct hsdk_div_full_cfg {
143 const u32 clk_rate[MAX_FREQ_VARIATIONS];
144 const u32 pll_rate[MAX_FREQ_VARIATIONS];
145 const struct hsdk_idiv_cfg idiv[];
148 static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
149 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
150 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
151 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
152 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
153 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
154 { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } },
159 static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
160 { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
161 { 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
162 { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
163 { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
164 { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
169 static const struct hsdk_div_full_cfg axi_clk_cfg = {
170 { 200000000, 400000000, 600000000, 800000000 },
171 { 800000000, 800000000, 600000000, 800000000 }, {
172 { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
173 { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */
174 { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */
175 { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */
176 { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */
177 { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */
178 { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */
179 { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */
180 { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */
181 { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */
182 { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */
183 { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */
184 { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
185 { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
186 { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
187 { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } }, /* EBI-REF */
192 struct hsdk_pll_cfg {
200 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
201 { 100000000, 0, 11, 3, 0 },
202 { 125000000, 0, 14, 3, 0 },
203 { 133000000, 0, 15, 3, 0 },
204 { 150000000, 0, 17, 3, 0 },
205 { 200000000, 1, 47, 3, 0 },
206 { 233000000, 1, 27, 2, 0 },
207 { 300000000, 1, 35, 2, 0 },
208 { 333000000, 1, 39, 2, 0 },
209 { 400000000, 1, 47, 2, 0 },
210 { 500000000, 0, 14, 1, 0 },
211 { 600000000, 0, 17, 1, 0 },
212 { 700000000, 0, 20, 1, 0 },
213 { 750000000, 1, 44, 1, 0 },
214 { 800000000, 0, 23, 1, 0 },
215 { 900000000, 1, 26, 0, 0 },
216 { 1000000000, 1, 29, 0, 0 },
217 { 1100000000, 1, 32, 0, 0 },
218 { 1200000000, 1, 35, 0, 0 },
219 { 1300000000, 1, 38, 0, 0 },
220 { 1400000000, 1, 41, 0, 0 },
221 { 1500000000, 1, 44, 0, 0 },
222 { 1600000000, 1, 47, 0, 0 },
226 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
227 { 297000000, 0, 21, 2, 0 },
228 { 540000000, 0, 19, 1, 0 },
229 { 594000000, 0, 21, 1, 0 },
233 struct hsdk_cgu_domain {
235 void __iomem *pll_regs;
236 /* PLLs special registers */
237 void __iomem *spec_regs;
239 const struct hsdk_pll_devdata *pll;
241 /* Dividers registers */
242 void __iomem *idiv_regs;
245 struct hsdk_cgu_clk {
246 const struct cgu_clk_map *map;
247 /* CGU block register */
248 void __iomem *cgu_regs;
249 /* CREG block register */
250 void __iomem *creg_regs;
252 /* The domain we are working with */
253 struct hsdk_cgu_domain curr_domain;
256 struct hsdk_pll_devdata {
257 const u32 parent_rate;
258 const struct hsdk_pll_cfg *const pll_cfg;
259 const int (*const update_rate)(struct hsdk_cgu_clk *clk,
261 const struct hsdk_pll_cfg *cfg);
264 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
265 const struct hsdk_pll_cfg *);
266 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *, unsigned long,
267 const struct hsdk_pll_cfg *);
269 static const struct hsdk_pll_devdata core_pll_dat = {
270 .parent_rate = PARENT_RATE_33,
271 .pll_cfg = asdt_pll_cfg,
272 .update_rate = hsdk_pll_core_update_rate,
275 static const struct hsdk_pll_devdata sdt_pll_dat = {
276 .parent_rate = PARENT_RATE_33,
277 .pll_cfg = asdt_pll_cfg,
278 .update_rate = hsdk_pll_comm_update_rate,
281 static const struct hsdk_pll_devdata hdmi_pll_dat = {
282 .parent_rate = PARENT_RATE_27,
283 .pll_cfg = hdmi_pll_cfg,
284 .update_rate = hsdk_pll_comm_update_rate,
287 static ulong idiv_set(struct clk *, ulong);
288 static ulong cpu_clk_set(struct clk *, ulong);
289 static ulong axi_clk_set(struct clk *, ulong);
290 static ulong tun_hsdk_set(struct clk *, ulong);
291 static ulong tun_h4xd_set(struct clk *, ulong);
292 static ulong idiv_get(struct clk *);
293 static int idiv_off(struct clk *);
294 static ulong pll_set(struct clk *, ulong);
295 static ulong pll_get(struct clk *);
298 const u32 cgu_pll_oft;
299 const u32 cgu_div_oft;
300 const struct hsdk_pll_devdata *const pll_devdata;
301 const ulong (*const get_rate)(struct clk *clk);
302 const ulong (*const set_rate)(struct clk *clk, ulong rate);
303 const int (*const disable)(struct clk *clk);
306 static const struct cgu_clk_map hsdk_clk_map[] = {
307 [CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
308 [CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
309 [CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
310 [CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
311 [CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
312 [CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
313 [CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
314 [CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
315 [CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
316 [CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
317 [CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
318 [CLK_SYS_GFX_DMA] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
319 [CLK_SYS_GFX_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
320 [CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
321 [CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
322 [CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
323 [CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
324 [CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
325 [CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
326 [CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
327 [CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
328 [CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_hsdk_set, idiv_off },
329 [CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
330 [CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
331 [CLK_TUN_TIMER] = { /* missing in HSDK */ },
332 [CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
333 [CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
336 static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
337 [CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
338 [CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
339 [CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
340 [CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
341 [CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
342 [CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
343 [CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
344 [CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
345 [CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
346 [CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
347 [CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
348 [CLK_SYS_GFX_DMA] = { /* missing in HSDK-4xD */ },
349 [CLK_SYS_GFX_CFG] = { /* missing in HSDK-4xD */ },
350 [CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
351 [CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
352 [CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
353 [CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
354 [CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
355 [CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
356 [CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
357 [CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
358 [CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_h4xd_set, idiv_off },
359 [CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
360 [CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
361 [CLK_TUN_TIMER] = { CGU_TUN_PLL, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
362 [CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
363 [CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
366 static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
368 iowrite32(val, clk->curr_domain.idiv_regs);
371 static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
373 return ioread32(clk->curr_domain.idiv_regs);
376 static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
378 iowrite32(val, clk->curr_domain.pll_regs + reg);
381 static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
383 return ioread32(clk->curr_domain.pll_regs + reg);
386 static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
388 iowrite32(val, clk->curr_domain.spec_regs + reg);
391 static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
393 return ioread32(clk->curr_domain.spec_regs + reg);
396 static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
397 const struct hsdk_pll_cfg *cfg)
401 /* Powerdown and Bypass bits should be cleared */
402 val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
403 val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
404 val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
405 val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
407 pr_debug("write configurarion: %#x\n", val);
409 hsdk_pll_write(clk, CGU_PLL_CTRL, val);
412 static inline bool hsdk_pll_is_locked(struct hsdk_cgu_clk *clk)
414 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
417 static inline bool hsdk_pll_is_err(struct hsdk_cgu_clk *clk)
419 return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
422 static ulong pll_get(struct clk *sclk)
426 u32 idiv, fbdiv, odiv;
427 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
428 u32 parent_rate = clk->curr_domain.pll->parent_rate;
430 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
432 pr_debug("current configurarion: %#x\n", val);
434 /* Check if PLL is bypassed */
435 if (val & CGU_PLL_CTRL_BYPASS)
438 /* Check if PLL is disabled */
439 if (val & CGU_PLL_CTRL_PD)
442 /* input divider = reg.idiv + 1 */
443 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
444 /* fb divider = 2*(reg.fbdiv + 1) */
445 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
446 /* output divider = 2^(reg.odiv) */
447 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
449 rate = (u64)parent_rate * fbdiv;
450 do_div(rate, idiv * odiv);
455 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
458 unsigned long best_rate;
459 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
460 const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
462 if (pll_cfg[0].rate == 0)
465 best_rate = pll_cfg[0].rate;
467 for (i = 1; pll_cfg[i].rate != 0; i++) {
468 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
469 best_rate = pll_cfg[i].rate;
472 pr_debug("chosen best rate: %lu\n", best_rate);
477 static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk *clk,
479 const struct hsdk_pll_cfg *cfg)
481 hsdk_pll_set_cfg(clk, cfg);
484 * Wait until CGU relocks and check error status.
485 * If after timeout CGU is unlocked yet return error.
487 udelay(HSDK_PLL_MAX_LOCK_TIME);
488 if (!hsdk_pll_is_locked(clk))
491 if (hsdk_pll_is_err(clk))
497 static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *clk,
499 const struct hsdk_pll_cfg *cfg)
502 * When core clock exceeds 500MHz, the divider for the interface
503 * clock must be programmed to div-by-2.
505 if (rate > CORE_IF_CLK_THRESHOLD_HZ)
506 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_2);
508 hsdk_pll_set_cfg(clk, cfg);
511 * Wait until CGU relocks and check error status.
512 * If after timeout CGU is unlocked yet return error.
514 udelay(HSDK_PLL_MAX_LOCK_TIME);
515 if (!hsdk_pll_is_locked(clk))
518 if (hsdk_pll_is_err(clk))
522 * Program divider to div-by-1 if we succesfuly set core clock below
525 if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
526 hsdk_pll_spcwrite(clk, CREG_CORE_IF_DIV, CREG_CORE_IF_CLK_DIV_1);
531 static ulong pll_set(struct clk *sclk, ulong rate)
534 unsigned long best_rate;
535 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
536 const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
537 const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
539 best_rate = hsdk_pll_round_rate(sclk, rate);
541 for (i = 0; pll_cfg[i].rate != 0; i++)
542 if (pll_cfg[i].rate == best_rate)
543 return pll->update_rate(clk, best_rate, &pll_cfg[i]);
545 pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
551 static int idiv_off(struct clk *sclk)
553 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
555 hsdk_idiv_write(clk, 0);
560 static ulong idiv_get(struct clk *sclk)
562 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
563 ulong parent_rate = pll_get(sclk);
564 u32 div_factor = hsdk_idiv_read(clk);
566 div_factor &= CGU_IDIV_MASK;
568 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
573 return parent_rate / div_factor;
576 /* Special behavior: wen we set this clock we set both idiv and pll */
577 static ulong cpu_clk_set(struct clk *sclk, ulong rate)
581 ret = pll_set(sclk, rate);
582 idiv_set(sclk, rate);
589 * when we set these clocks we set both PLL and all idiv dividers related to
592 static ulong common_div_clk_set(struct clk *sclk, ulong rate,
593 const struct hsdk_div_full_cfg *cfg)
595 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
597 int i, freq_idx = -1;
600 pll_rate = pll_get(sclk);
602 for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
603 /* unused freq variations are filled with 0 */
604 if (!cfg->clk_rate[i])
607 if (cfg->clk_rate[i] == rate) {
614 pr_err("clk: invalid rate=%ld Hz\n", rate);
618 /* configure PLL before dividers */
619 if (cfg->pll_rate[freq_idx] < pll_rate)
620 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
622 /* configure SYS dividers */
623 for (i = 0; cfg->idiv[i].oft != 0; i++) {
624 clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
625 hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
628 /* configure PLL after dividers */
629 if (cfg->pll_rate[freq_idx] >= pll_rate)
630 ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
635 static ulong axi_clk_set(struct clk *sclk, ulong rate)
637 return common_div_clk_set(sclk, rate, &axi_clk_cfg);
640 static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
642 return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
645 static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
647 return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
650 static ulong idiv_set(struct clk *sclk, ulong rate)
652 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
653 ulong parent_rate = pll_get(sclk);
656 div_factor = parent_rate / rate;
657 if (abs(rate - parent_rate / (div_factor + 1)) <=
658 abs(rate - parent_rate / div_factor)) {
662 if (div_factor & ~CGU_IDIV_MASK) {
663 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n",
664 rate, parent_rate, div_factor, CGU_IDIV_MASK);
666 div_factor = CGU_IDIV_MASK;
669 if (div_factor == 0) {
670 pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n",
671 rate, parent_rate, div_factor);
676 hsdk_idiv_write(clk, div_factor);
681 static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
683 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
685 if (sclk->id >= CGU_MAX_CLOCKS)
688 /* clocks missing in current map have their entry zeroed */
689 if (!clk->map[sclk->id].pll_devdata)
692 clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
693 clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
694 clk->curr_domain.spec_regs = clk->creg_regs;
695 clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
700 static ulong hsdk_cgu_get_rate(struct clk *sclk)
702 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
704 if (hsdk_prepare_clock_tree_branch(sclk))
707 return clk->map[sclk->id].get_rate(sclk);
710 static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
712 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
714 if (hsdk_prepare_clock_tree_branch(sclk))
717 if (clk->map[sclk->id].set_rate)
718 return clk->map[sclk->id].set_rate(sclk, rate);
723 static int hsdk_cgu_disable(struct clk *sclk)
725 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
727 if (hsdk_prepare_clock_tree_branch(sclk))
730 if (clk->map[sclk->id].disable)
731 return clk->map[sclk->id].disable(sclk);
736 static const struct clk_ops hsdk_cgu_ops = {
737 .set_rate = hsdk_cgu_set_rate,
738 .get_rate = hsdk_cgu_get_rate,
739 .disable = hsdk_cgu_disable,
742 static int hsdk_cgu_clk_probe(struct udevice *dev)
744 struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
746 BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
747 BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
749 /* Choose which clock map to use in runtime */
750 if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
751 hsdk_clk->map = hsdk_clk_map;
753 hsdk_clk->map = hsdk_4xd_clk_map;
755 hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
756 if (!hsdk_clk->cgu_regs)
759 hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
760 if (!hsdk_clk->creg_regs)
766 static const struct udevice_id hsdk_cgu_clk_id[] = {
767 { .compatible = "snps,hsdk-cgu-clock" },
771 U_BOOT_DRIVER(hsdk_cgu_clk) = {
772 .name = "hsdk-cgu-clk",
774 .of_match = hsdk_cgu_clk_id,
775 .probe = hsdk_cgu_clk_probe,
776 .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk),
777 .ops = &hsdk_cgu_ops,