drivers/clk/clk-hifiberry-dachd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Clock Driver for HiFiBerry DAC+ HD
   4  *
   5  * Author: Joerg Schambacher, i2Audio GmbH for HiFiBerry
   6  *         Copyright 2020
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/clk.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/slab.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/i2c.h>
  26 #include <linux/regmap.h>
  27
  28 #define NO_PLL_RESET                    0
  29 #define PLL_RESET                       1
  30 #define HIFIBERRY_PLL_MAX_REGISTER      256
  31 #define DEFAULT_RATE                    44100
  32
  33 static struct reg_default hifiberry_pll_reg_defaults[] = {
  34         {0x02, 0x53}, {0x03, 0x00}, {0x07, 0x20}, {0x0F, 0x00},
  35         {0x10, 0x0D}, {0x11, 0x1D}, {0x12, 0x0D}, {0x13, 0x8C},
  36         {0x14, 0x8C}, {0x15, 0x8C}, {0x16, 0x8C}, {0x17, 0x8C},
  37         {0x18, 0x2A}, {0x1C, 0x00}, {0x1D, 0x0F}, {0x1F, 0x00},
  38         {0x2A, 0x00}, {0x2C, 0x00}, {0x2F, 0x00}, {0x30, 0x00},
  39         {0x31, 0x00}, {0x32, 0x00}, {0x34, 0x00}, {0x37, 0x00},
  40         {0x38, 0x00}, {0x39, 0x00}, {0x3A, 0x00}, {0x3B, 0x01},
  41         {0x3E, 0x00}, {0x3F, 0x00}, {0x40, 0x00}, {0x41, 0x00},
  42         {0x5A, 0x00}, {0x5B, 0x00}, {0x95, 0x00}, {0x96, 0x00},
  43         {0x97, 0x00}, {0x98, 0x00}, {0x99, 0x00}, {0x9A, 0x00},
  44         {0x9B, 0x00}, {0xA2, 0x00}, {0xA3, 0x00}, {0xA4, 0x00},
  45         {0xB7, 0x92},
  46         {0x1A, 0x3D}, {0x1B, 0x09}, {0x1E, 0xF3}, {0x20, 0x13},
  47         {0x21, 0x75}, {0x2B, 0x04}, {0x2D, 0x11}, {0x2E, 0xE0},
  48         {0x3D, 0x7A},
  49         {0x35, 0x9D}, {0x36, 0x00}, {0x3C, 0x42},
  50         { 177, 0xAC},
  51 };
  52 static struct reg_default common_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  53 static int num_common_pll_regs;
  54 static struct reg_default dedicated_192k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  55 static int num_dedicated_192k_pll_regs;
  56 static struct reg_default dedicated_96k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  57 static int num_dedicated_96k_pll_regs;
  58 static struct reg_default dedicated_48k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  59 static int num_dedicated_48k_pll_regs;
  60 static struct reg_default dedicated_176k4_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  61 static int num_dedicated_176k4_pll_regs;
  62 static struct reg_default dedicated_88k2_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  63 static int num_dedicated_88k2_pll_regs;
  64 static struct reg_default dedicated_44k1_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
  65 static int num_dedicated_44k1_pll_regs;
  66
  67 /**
  68  * struct clk_hifiberry_drvdata - Common struct to the HiFiBerry DAC HD Clk
  69  * @hw: clk_hw for the common clk framework
  70  */
  71 struct clk_hifiberry_drvdata {
  72         struct regmap *regmap;
  73         struct clk *clk;
  74         struct clk_hw hw;
  75         unsigned long rate;
  76 };
  77
  78 #define to_hifiberry_clk(_hw) \
  79         container_of(_hw, struct clk_hifiberry_drvdata, hw)
  80
  81 static int clk_hifiberry_dachd_write_pll_regs(struct regmap *regmap,
  82                                 struct reg_default *regs,
  83                                 int num, int do_pll_reset)
  84 {
  85         int i;
  86         int ret = 0;
  87         char pll_soft_reset[] = { 177, 0xAC, };
  88
  89         for (i = 0; i < num; i++) {
  90                 ret |= regmap_write(regmap, regs[i].reg, regs[i].def);
  91                 if (ret)
  92                         return ret;
  93         }
  94         if (do_pll_reset) {
  95                 ret |= regmap_write(regmap, pll_soft_reset[0],
  96                                                 pll_soft_reset[1]);
  97                 mdelay(10);
  98         }
  99         return ret;
 100 }
 101
 102 static unsigned long clk_hifiberry_dachd_recalc_rate(struct clk_hw *hw,
 103         unsigned long parent_rate)
 104 {
 105         return to_hifiberry_clk(hw)->rate;
 106 }
 107
 108 static long clk_hifiberry_dachd_round_rate(struct clk_hw *hw,
 109         unsigned long rate, unsigned long *parent_rate)
 110 {
 111         return rate;
 112 }
 113
 114 static int clk_hifiberry_dachd_set_rate(struct clk_hw *hw,
 115         unsigned long rate, unsigned long parent_rate)
 116 {
 117         int ret;
 118         struct clk_hifiberry_drvdata *drvdata = to_hifiberry_clk(hw);
 119
 120         switch (rate) {
 121         case 44100:
 122                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 123                         dedicated_44k1_pll_regs, num_dedicated_44k1_pll_regs,
 124                         PLL_RESET);
 125                 break;
 126         case 88200:
 127                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 128                         dedicated_88k2_pll_regs, num_dedicated_88k2_pll_regs,
 129                         PLL_RESET);
 130                 break;
 131         case 176400:
 132                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 133                         dedicated_176k4_pll_regs, num_dedicated_176k4_pll_regs,
 134                         PLL_RESET);
 135                 break;
 136         case 48000:
 137                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 138                         dedicated_48k_pll_regs, num_dedicated_48k_pll_regs,
 139                         PLL_RESET);
 140                 break;
 141         case 96000:
 142                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 143                         dedicated_96k_pll_regs, num_dedicated_96k_pll_regs,
 144                         PLL_RESET);
 145                 break;
 146         case 192000:
 147                 ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
 148                         dedicated_192k_pll_regs, num_dedicated_192k_pll_regs,
 149                         PLL_RESET);
 150                 break;
 151         default:
 152                 ret = -EINVAL;
 153                 break;
 154         }
 155         to_hifiberry_clk(hw)->rate = rate;
 156
 157         return ret;
 158 }
 159
 160 const struct clk_ops clk_hifiberry_dachd_rate_ops = {
 161         .recalc_rate = clk_hifiberry_dachd_recalc_rate,
 162         .round_rate = clk_hifiberry_dachd_round_rate,
 163         .set_rate = clk_hifiberry_dachd_set_rate,
 164 };
 165
 166 static int clk_hifiberry_get_prop_values(struct device *dev,
 167                                         char *prop_name,
 168                                         struct reg_default *regs)
 169 {
 170         int ret;
 171         int i;
 172         u8 tmp[2 * HIFIBERRY_PLL_MAX_REGISTER];
 173
 174         ret = of_property_read_variable_u8_array(dev->of_node, prop_name,
 175                         tmp, 0, 2 * HIFIBERRY_PLL_MAX_REGISTER);
 176         if (ret < 0)
 177                 return ret;
 178         if (ret & 1) {
 179                 dev_err(dev,
 180                         "%s <%s> -> #%i odd number of bytes for reg/val pairs!",
 181                         __func__,
 182                         prop_name,
 183                         ret);
 184                 return -EINVAL;
 185         }
 186         ret /= 2;
 187         for (i = 0; i < ret; i++) {
 188                 regs[i].reg = (u32)tmp[2 * i];
 189                 regs[i].def = (u32)tmp[2 * i + 1];
 190         }
 191         return ret;
 192 }
 193
 194
 195 static int clk_hifiberry_dachd_dt_parse(struct device *dev)
 196 {
 197         num_common_pll_regs = clk_hifiberry_get_prop_values(dev,
 198                                 "common_pll_regs", common_pll_regs);
 199         num_dedicated_44k1_pll_regs = clk_hifiberry_get_prop_values(dev,
 200                                 "44k1_pll_regs", dedicated_44k1_pll_regs);
 201         num_dedicated_88k2_pll_regs = clk_hifiberry_get_prop_values(dev,
 202                                 "88k2_pll_regs", dedicated_88k2_pll_regs);
 203         num_dedicated_176k4_pll_regs = clk_hifiberry_get_prop_values(dev,
 204                                 "176k4_pll_regs", dedicated_176k4_pll_regs);
 205         num_dedicated_48k_pll_regs = clk_hifiberry_get_prop_values(dev,
 206                                 "48k_pll_regs", dedicated_48k_pll_regs);
 207         num_dedicated_96k_pll_regs = clk_hifiberry_get_prop_values(dev,
 208                                 "96k_pll_regs", dedicated_96k_pll_regs);
 209         num_dedicated_192k_pll_regs = clk_hifiberry_get_prop_values(dev,
 210                                 "192k_pll_regs", dedicated_192k_pll_regs);
 211         return 0;
 212 }
 213
 214
 215 static int clk_hifiberry_dachd_remove(struct device *dev)
 216 {
 217         of_clk_del_provider(dev->of_node);
 218         return 0;
 219 }
 220
 221 const struct regmap_config hifiberry_pll_regmap = {
 222         .reg_bits = 8,
 223         .val_bits = 8,
 224         .max_register = HIFIBERRY_PLL_MAX_REGISTER,
 225         .reg_defaults = hifiberry_pll_reg_defaults,
 226         .num_reg_defaults = ARRAY_SIZE(hifiberry_pll_reg_defaults),
 227         .cache_type = REGCACHE_RBTREE,
 228 };
 229 EXPORT_SYMBOL_GPL(hifiberry_pll_regmap);
 230
 231
 232 static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c,
 233                              const struct i2c_device_id *id)
 234 {
 235         struct clk_hifiberry_drvdata *hdclk;
 236         int ret = 0;
 237         struct clk_init_data init;
 238         struct device *dev = &i2c->dev;
 239         struct device_node *dev_node = dev->of_node;
 240         struct regmap_config config = hifiberry_pll_regmap;
 241
 242         hdclk = devm_kzalloc(&i2c->dev,
 243                         sizeof(struct clk_hifiberry_drvdata), GFP_KERNEL);
 244         if (!hdclk)
 245                 return -ENOMEM;
 246
 247         i2c_set_clientdata(i2c, hdclk);
 248
 249         hdclk->regmap = devm_regmap_init_i2c(i2c, &config);
 250
 251         if (IS_ERR(hdclk->regmap))
 252                 return PTR_ERR(hdclk->regmap);
 253
 254         /* start PLL to allow detection of DAC */
 255         ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap,
 256                                 hifiberry_pll_reg_defaults,
 257                                 ARRAY_SIZE(hifiberry_pll_reg_defaults),
 258                                 PLL_RESET);
 259         if (ret)
 260                 return ret;
 261
 262         clk_hifiberry_dachd_dt_parse(dev);
 263
 264         /* restart PLL with configs from DTB */
 265         ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, common_pll_regs,
 266                                         num_common_pll_regs, PLL_RESET);
 267         if (ret)
 268                 return ret;
 269
 270         init.name = "clk-hifiberry-dachd";
 271         init.ops = &clk_hifiberry_dachd_rate_ops;
 272         init.flags = 0;
 273         init.parent_names = NULL;
 274         init.num_parents = 0;
 275
 276         hdclk->hw.init = &init;
 277
 278         hdclk->clk = devm_clk_register(dev, &hdclk->hw);
 279         if (IS_ERR(hdclk->clk)) {
 280                 dev_err(dev, "unable to register %s\n", init.name);
 281                 return PTR_ERR(hdclk->clk);
 282         }
 283
 284         ret = of_clk_add_provider(dev_node, of_clk_src_simple_get, hdclk->clk);
 285         if (ret != 0) {
 286                 dev_err(dev, "Cannot of_clk_add_provider");
 287                 return ret;
 288         }
 289
 290         ret = clk_set_rate(hdclk->hw.clk, DEFAULT_RATE);
 291         if (ret != 0) {
 292                 dev_err(dev, "Cannot set rate : %d\n",  ret);
 293                 return -EINVAL;
 294         }
 295
 296         return ret;
 297 }
 298
 299 static int clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c)
 300 {
 301         clk_hifiberry_dachd_remove(&i2c->dev);
 302         return 0;
 303 }
 304
 305 static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = {
 306         { "dachd-clk", },
 307         { }
 308 };
 309 MODULE_DEVICE_TABLE(i2c, clk_hifiberry_dachd_i2c_id);
 310
 311 static const struct of_device_id clk_hifiberry_dachd_of_match[] = {
 312         { .compatible = "hifiberry,dachd-clk", },
 313         { }
 314 };
 315 MODULE_DEVICE_TABLE(of, clk_hifiberry_dachd_of_match);
 316
 317 static struct i2c_driver clk_hifiberry_dachd_i2c_driver = {
 318         .probe          = clk_hifiberry_dachd_i2c_probe,
 319         .remove         = clk_hifiberry_dachd_i2c_remove,
 320         .id_table       = clk_hifiberry_dachd_i2c_id,
 321         .driver         = {
 322                 .name   = "dachd-clk",
 323                 .of_match_table = of_match_ptr(clk_hifiberry_dachd_of_match),
 324         },
 325 };
 326
 327 module_i2c_driver(clk_hifiberry_dachd_i2c_driver);
 328
 329
 330 MODULE_DESCRIPTION("HiFiBerry DAC+ HD clock driver");
 331 MODULE_AUTHOR("Joerg Schambacher <joerg@i2audio.com>");
 332 MODULE_LICENSE("GPL v2");
 333 MODULE_ALIAS("platform:clk-hifiberry-dachd");