1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Gated clock implementation
13 #include <clk-uclass.h>
14 #include <dm/device.h>
15 #include <dm/devres.h>
16 #include <linux/bitops.h>
17 #include <linux/clk-provider.h>
20 #include <linux/err.h>
22 #define UBOOT_DM_CLK_GATE "clk_gate"
25 * DOC: basic gatable clock which can gate and ungate it's output
27 * Traits of this clock:
28 * prepare - clk_(un)prepare only ensures parent is (un)prepared
29 * enable - clk_enable and clk_disable are functional & control gating
30 * rate - inherits rate from parent. No clk_set_rate support
31 * parent - fixed parent. No clk_set_parent support
35 * It works on following logic:
37 * For enabling clock, enable = 1
38 * set2dis = 1 -> clear bit -> set = 0
39 * set2dis = 0 -> set bit -> set = 1
41 * For disabling clock, enable = 0
42 * set2dis = 1 -> set bit -> set = 1
43 * set2dis = 0 -> clear bit -> set = 0
45 * So, result is always: enable xor set2dis.
47 static void clk_gate_endisable(struct clk *clk, int enable)
49 struct clk_gate *gate = to_clk_gate(clk);
50 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
55 if (gate->flags & CLK_GATE_HIWORD_MASK) {
56 reg = BIT(gate->bit_idx + 16);
58 reg |= BIT(gate->bit_idx);
60 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
61 reg = gate->io_gate_val;
63 reg = readl(gate->reg);
67 reg |= BIT(gate->bit_idx);
69 reg &= ~BIT(gate->bit_idx);
72 writel(reg, gate->reg);
75 static int clk_gate_enable(struct clk *clk)
77 clk_gate_endisable(clk, 1);
82 static int clk_gate_disable(struct clk *clk)
84 clk_gate_endisable(clk, 0);
89 int clk_gate_is_enabled(struct clk *clk)
91 struct clk_gate *gate = to_clk_gate(clk);
94 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
95 reg = gate->io_gate_val;
97 reg = readl(gate->reg);
100 /* if a set bit disables this clk, flip it before masking */
101 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
102 reg ^= BIT(gate->bit_idx);
104 reg &= BIT(gate->bit_idx);
109 const struct clk_ops clk_gate_ops = {
110 .enable = clk_gate_enable,
111 .disable = clk_gate_disable,
112 .get_rate = clk_generic_get_rate,
115 struct clk *clk_register_gate(struct device *dev, const char *name,
116 const char *parent_name, unsigned long flags,
117 void __iomem *reg, u8 bit_idx,
118 u8 clk_gate_flags, spinlock_t *lock)
120 struct clk_gate *gate;
124 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
126 pr_err("gate bit exceeds LOWORD field\n");
127 return ERR_PTR(-EINVAL);
131 /* allocate the gate */
132 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
134 return ERR_PTR(-ENOMEM);
136 /* struct clk_gate assignments */
138 gate->bit_idx = bit_idx;
139 gate->flags = clk_gate_flags;
140 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
141 gate->io_gate_val = *(u32 *)reg;
146 ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
155 U_BOOT_DRIVER(clk_gate) = {
156 .name = UBOOT_DM_CLK_GATE,
158 .ops = &clk_gate_ops,
159 .flags = DM_FLAG_PRE_RELOC,