2 * Copyright (C) 2014 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Adjustable fractional divider clock implementation.
9 * Output rate = (m / n) * parent_rate.
10 * Uses rational best approximation algorithm.
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/device.h>
16 #include <linux/slab.h>
17 #include <linux/rational.h>
19 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
21 static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
22 unsigned long parent_rate)
24 struct clk_fractional_divider *fd = to_clk_fd(hw);
25 unsigned long flags = 0;
31 spin_lock_irqsave(fd->lock, flags);
35 val = clk_readl(fd->reg);
38 spin_unlock_irqrestore(fd->lock, flags);
42 m = (val & fd->mmask) >> fd->mshift;
43 n = (val & fd->nmask) >> fd->nshift;
48 ret = (u64)parent_rate * m;
54 static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
55 unsigned long *parent_rate)
57 struct clk_fractional_divider *fd = to_clk_fd(hw);
62 if (!rate || rate >= *parent_rate)
66 * Get rate closer to *parent_rate to guarantee there is no overflow
67 * for m and n. In the result it will be the nearest rate left shifted
68 * by (scale - fd->nwidth) bits.
70 scale = fls_long(*parent_rate / rate - 1);
71 if (scale > fd->nwidth)
72 rate <<= scale - fd->nwidth;
74 rational_best_approximation(rate, *parent_rate,
75 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
78 ret = (u64)*parent_rate * m;
84 static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
85 unsigned long parent_rate)
87 struct clk_fractional_divider *fd = to_clk_fd(hw);
88 unsigned long flags = 0;
92 rational_best_approximation(rate, parent_rate,
93 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
97 spin_lock_irqsave(fd->lock, flags);
101 val = clk_readl(fd->reg);
102 val &= ~(fd->mmask | fd->nmask);
103 val |= (m << fd->mshift) | (n << fd->nshift);
104 clk_writel(val, fd->reg);
107 spin_unlock_irqrestore(fd->lock, flags);
114 const struct clk_ops clk_fractional_divider_ops = {
115 .recalc_rate = clk_fd_recalc_rate,
116 .round_rate = clk_fd_round_rate,
117 .set_rate = clk_fd_set_rate,
119 EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
121 struct clk *clk_register_fractional_divider(struct device *dev,
122 const char *name, const char *parent_name, unsigned long flags,
123 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
124 u8 clk_divider_flags, spinlock_t *lock)
126 struct clk_fractional_divider *fd;
127 struct clk_init_data init;
130 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
132 return ERR_PTR(-ENOMEM);
135 init.ops = &clk_fractional_divider_ops;
136 init.flags = flags | CLK_IS_BASIC;
137 init.parent_names = parent_name ? &parent_name : NULL;
138 init.num_parents = parent_name ? 1 : 0;
143 fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
146 fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
147 fd->flags = clk_divider_flags;
151 clk = clk_register(dev, &fd->hw);
157 EXPORT_SYMBOL_GPL(clk_register_fractional_divider);