1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
15 #include <clk-uclass.h>
16 #include <dm/device.h>
17 #include <dm/uclass.h>
19 #include <dm/device-internal.h>
20 #include <linux/clk-provider.h>
21 #include <linux/log2.h>
26 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
28 static unsigned int _get_table_div(const struct clk_div_table *table,
31 const struct clk_div_table *clkt;
33 for (clkt = table; clkt->div; clkt++)
39 static unsigned int _get_div(const struct clk_div_table *table,
40 unsigned int val, unsigned long flags, u8 width)
42 if (flags & CLK_DIVIDER_ONE_BASED)
44 if (flags & CLK_DIVIDER_POWER_OF_TWO)
46 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
47 return val ? val : clk_div_mask(width) + 1;
49 return _get_table_div(table, val);
53 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
55 const struct clk_div_table *table,
56 unsigned long flags, unsigned long width)
60 div = _get_div(table, val, flags, width);
62 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
63 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
68 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
71 static ulong clk_divider_recalc_rate(struct clk *clk)
73 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
74 dev_get_clk_ptr(clk->dev) : clk);
75 unsigned long parent_rate = clk_get_parent_rate(clk);
78 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
79 val = divider->io_divider_val;
81 val = readl(divider->reg);
83 val >>= divider->shift;
84 val &= clk_div_mask(divider->width);
86 return divider_recalc_rate(clk, parent_rate, val, divider->table,
87 divider->flags, divider->width);
90 static bool _is_valid_table_div(const struct clk_div_table *table,
93 const struct clk_div_table *clkt;
95 for (clkt = table; clkt->div; clkt++)
101 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
104 if (flags & CLK_DIVIDER_POWER_OF_TWO)
105 return is_power_of_2(div);
107 return _is_valid_table_div(table, div);
111 static unsigned int _get_table_val(const struct clk_div_table *table,
114 const struct clk_div_table *clkt;
116 for (clkt = table; clkt->div; clkt++)
117 if (clkt->div == div)
122 static unsigned int _get_val(const struct clk_div_table *table,
123 unsigned int div, unsigned long flags, u8 width)
125 if (flags & CLK_DIVIDER_ONE_BASED)
127 if (flags & CLK_DIVIDER_POWER_OF_TWO)
129 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
130 return (div == clk_div_mask(width) + 1) ? 0 : div;
132 return _get_table_val(table, div);
135 int divider_get_val(unsigned long rate, unsigned long parent_rate,
136 const struct clk_div_table *table, u8 width,
139 unsigned int div, value;
141 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
143 if (!_is_valid_div(table, div, flags))
146 value = _get_val(table, div, flags, width);
148 return min_t(unsigned int, value, clk_div_mask(width));
151 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
153 struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
154 dev_get_clk_ptr(clk->dev) : clk);
155 unsigned long parent_rate = clk_get_parent_rate(clk);
159 value = divider_get_val(rate, parent_rate, divider->table,
160 divider->width, divider->flags);
164 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
165 val = clk_div_mask(divider->width) << (divider->shift + 16);
167 val = readl(divider->reg);
168 val &= ~(clk_div_mask(divider->width) << divider->shift);
170 val |= (u32)value << divider->shift;
171 writel(val, divider->reg);
173 return clk_get_rate(clk);
176 const struct clk_ops clk_divider_ops = {
177 .get_rate = clk_divider_recalc_rate,
178 .set_rate = clk_divider_set_rate,
181 static struct clk *_register_divider(struct device *dev, const char *name,
182 const char *parent_name, unsigned long flags,
183 void __iomem *reg, u8 shift, u8 width,
184 u8 clk_divider_flags, const struct clk_div_table *table)
186 struct clk_divider *div;
190 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
191 if (width + shift > 16) {
192 pr_warn("divider value exceeds LOWORD field\n");
193 return ERR_PTR(-EINVAL);
197 /* allocate the divider */
198 div = kzalloc(sizeof(*div), GFP_KERNEL);
200 return ERR_PTR(-ENOMEM);
202 /* struct clk_divider assignments */
206 div->flags = clk_divider_flags;
208 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
209 div->io_divider_val = *(u32 *)reg;
212 /* register the clock */
215 ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
224 struct clk *clk_register_divider(struct device *dev, const char *name,
225 const char *parent_name, unsigned long flags,
226 void __iomem *reg, u8 shift, u8 width,
227 u8 clk_divider_flags)
231 clk = _register_divider(dev, name, parent_name, flags, reg, shift,
232 width, clk_divider_flags, NULL);
234 return ERR_CAST(clk);
238 U_BOOT_DRIVER(ccf_clk_divider) = {
239 .name = UBOOT_DM_CLK_CCF_DIVIDER,
241 .ops = &clk_divider_ops,
242 .flags = DM_FLAG_PRE_RELOC,