1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
6 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
8 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
15 #include <clk-uclass.h>
16 #include <dm/device.h>
17 #include <dm/devres.h>
18 #include <dm/uclass.h>
20 #include <dm/device-internal.h>
21 #include <linux/bug.h>
22 #include <linux/clk-provider.h>
23 #include <linux/err.h>
24 #include <linux/log2.h>
29 #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
31 static unsigned int _get_table_div(const struct clk_div_table *table,
34 const struct clk_div_table *clkt;
36 for (clkt = table; clkt->div; clkt++)
42 static unsigned int _get_div(const struct clk_div_table *table,
43 unsigned int val, unsigned long flags, u8 width)
45 if (flags & CLK_DIVIDER_ONE_BASED)
47 if (flags & CLK_DIVIDER_POWER_OF_TWO)
49 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
50 return val ? val : clk_div_mask(width) + 1;
52 return _get_table_div(table, val);
56 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
58 const struct clk_div_table *table,
59 unsigned long flags, unsigned long width)
63 div = _get_div(table, val, flags, width);
65 WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
66 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
71 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
74 static ulong clk_divider_recalc_rate(struct clk *clk)
76 struct clk_divider *divider = to_clk_divider(clk);
77 unsigned long parent_rate = clk_get_parent_rate(clk);
80 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
81 val = divider->io_divider_val;
83 val = readl(divider->reg);
85 val >>= divider->shift;
86 val &= clk_div_mask(divider->width);
88 return divider_recalc_rate(clk, parent_rate, val, divider->table,
89 divider->flags, divider->width);
92 static bool _is_valid_table_div(const struct clk_div_table *table,
95 const struct clk_div_table *clkt;
97 for (clkt = table; clkt->div; clkt++)
103 static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
106 if (flags & CLK_DIVIDER_POWER_OF_TWO)
107 return is_power_of_2(div);
109 return _is_valid_table_div(table, div);
113 static unsigned int _get_table_val(const struct clk_div_table *table,
116 const struct clk_div_table *clkt;
118 for (clkt = table; clkt->div; clkt++)
119 if (clkt->div == div)
124 static unsigned int _get_val(const struct clk_div_table *table,
125 unsigned int div, unsigned long flags, u8 width)
127 if (flags & CLK_DIVIDER_ONE_BASED)
129 if (flags & CLK_DIVIDER_POWER_OF_TWO)
131 if (flags & CLK_DIVIDER_MAX_AT_ZERO)
132 return (div == clk_div_mask(width) + 1) ? 0 : div;
134 return _get_table_val(table, div);
137 int divider_get_val(unsigned long rate, unsigned long parent_rate,
138 const struct clk_div_table *table, u8 width,
141 unsigned int div, value;
143 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
145 if (!_is_valid_div(table, div, flags))
148 value = _get_val(table, div, flags, width);
150 return min_t(unsigned int, value, clk_div_mask(width));
153 static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
155 struct clk_divider *divider = to_clk_divider(clk);
156 unsigned long parent_rate = clk_get_parent_rate(clk);
160 value = divider_get_val(rate, parent_rate, divider->table,
161 divider->width, divider->flags);
165 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
166 val = clk_div_mask(divider->width) << (divider->shift + 16);
168 val = readl(divider->reg);
169 val &= ~(clk_div_mask(divider->width) << divider->shift);
171 val |= (u32)value << divider->shift;
172 writel(val, divider->reg);
174 return clk_get_rate(clk);
177 const struct clk_ops clk_divider_ops = {
178 .get_rate = clk_divider_recalc_rate,
179 .set_rate = clk_divider_set_rate,
182 static struct clk *_register_divider(struct device *dev, const char *name,
183 const char *parent_name, unsigned long flags,
184 void __iomem *reg, u8 shift, u8 width,
185 u8 clk_divider_flags, const struct clk_div_table *table)
187 struct clk_divider *div;
191 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
192 if (width + shift > 16) {
193 pr_warn("divider value exceeds LOWORD field\n");
194 return ERR_PTR(-EINVAL);
198 /* allocate the divider */
199 div = kzalloc(sizeof(*div), GFP_KERNEL);
201 return ERR_PTR(-ENOMEM);
203 /* struct clk_divider assignments */
207 div->flags = clk_divider_flags;
209 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
210 div->io_divider_val = *(u32 *)reg;
213 /* register the clock */
217 ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
226 struct clk *clk_register_divider(struct device *dev, const char *name,
227 const char *parent_name, unsigned long flags,
228 void __iomem *reg, u8 shift, u8 width,
229 u8 clk_divider_flags)
233 clk = _register_divider(dev, name, parent_name, flags, reg, shift,
234 width, clk_divider_flags, NULL);
236 return ERR_CAST(clk);
240 U_BOOT_DRIVER(ccf_clk_divider) = {
241 .name = UBOOT_DM_CLK_CCF_DIVIDER,
243 .ops = &clk_divider_ops,
244 .flags = DM_FLAG_PRE_RELOC,