1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
7 #define LOG_CATEGORY UCLASS_CLK
11 #include <clk-uclass.h>
15 #include <dm/device.h>
16 #include <dm/devres.h>
17 #include <linux/clk-provider.h>
18 #include <linux/err.h>
22 #define UBOOT_DM_CLK_COMPOSITE "clk_composite"
24 static u8 clk_composite_get_parent(struct clk *clk)
26 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
27 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
28 struct clk *mux = composite->mux;
31 return clk_mux_get_parent(mux);
36 static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
38 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
39 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
40 const struct clk_ops *mux_ops = composite->mux_ops;
41 struct clk *mux = composite->mux;
46 return mux_ops->set_parent(mux, parent);
49 static unsigned long clk_composite_recalc_rate(struct clk *clk)
51 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
52 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
53 const struct clk_ops *rate_ops = composite->rate_ops;
54 struct clk *rate = composite->rate;
57 return rate_ops->get_rate(rate);
59 return clk_get_parent_rate(clk);
62 static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
64 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
65 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
66 const struct clk_ops *rate_ops = composite->rate_ops;
67 struct clk *clk_rate = composite->rate;
70 return rate_ops->set_rate(clk_rate, rate);
72 return clk_get_rate(clk);
75 static int clk_composite_enable(struct clk *clk)
77 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
78 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
79 const struct clk_ops *gate_ops = composite->gate_ops;
80 struct clk *gate = composite->gate;
83 return gate_ops->enable(gate);
88 static int clk_composite_disable(struct clk *clk)
90 struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
91 (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
92 const struct clk_ops *gate_ops = composite->gate_ops;
93 struct clk *gate = composite->gate;
96 return gate_ops->disable(gate);
101 struct clk *clk_register_composite(struct device *dev, const char *name,
102 const char * const *parent_names,
103 int num_parents, struct clk *mux,
104 const struct clk_ops *mux_ops,
106 const struct clk_ops *rate_ops,
108 const struct clk_ops *gate_ops,
112 struct clk_composite *composite;
115 if (!num_parents || (num_parents != 1 && !mux))
116 return ERR_PTR(-EINVAL);
118 composite = kzalloc(sizeof(*composite), GFP_KERNEL);
120 return ERR_PTR(-ENOMEM);
122 if (mux && mux_ops) {
123 composite->mux = mux;
124 composite->mux_ops = mux_ops;
125 mux->data = (ulong)composite;
128 if (rate && rate_ops) {
129 if (!rate_ops->get_rate) {
130 clk = ERR_PTR(-EINVAL);
134 composite->rate = rate;
135 composite->rate_ops = rate_ops;
136 rate->data = (ulong)composite;
139 if (gate && gate_ops) {
140 if (!gate_ops->enable || !gate_ops->disable) {
141 clk = ERR_PTR(-EINVAL);
145 composite->gate = gate;
146 composite->gate_ops = gate_ops;
147 gate->data = (ulong)composite;
150 clk = &composite->clk;
152 ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
153 parent_names[clk_composite_get_parent(clk)]);
160 composite->mux->dev = clk->dev;
162 composite->rate->dev = clk->dev;
164 composite->gate->dev = clk->dev;
173 static const struct clk_ops clk_composite_ops = {
174 .set_parent = clk_composite_set_parent,
175 .get_rate = clk_composite_recalc_rate,
176 .set_rate = clk_composite_set_rate,
177 .enable = clk_composite_enable,
178 .disable = clk_composite_disable,
181 U_BOOT_DRIVER(clk_composite) = {
182 .name = UBOOT_DM_CLK_COMPOSITE,
184 .ops = &clk_composite_ops,
185 .flags = DM_FLAG_PRE_RELOC,