drivers/clk/clk-clps711x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Cirrus Logic CLPS711X CLK driver
   4  *
   5  *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/clkdev.h>
  10 #include <linux/io.h>
  11 #include <linux/ioport.h>
  12 #include <linux/of_address.h>
  13 #include <linux/slab.h>
  14 #include <linux/mfd/syscon/clps711x.h>
  15
  16 #include <dt-bindings/clock/clps711x-clock.h>
  17
  18 #define CLPS711X_SYSCON1        (0x0100)
  19 #define CLPS711X_SYSCON2        (0x1100)
  20 #define CLPS711X_SYSFLG2        (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
  21 #define CLPS711X_PLLR           (0xa5a8)
  22
  23 #define CLPS711X_EXT_FREQ       (13000000)
  24 #define CLPS711X_OSC_FREQ       (3686400)
  25
  26 static const struct clk_div_table spi_div_table[] = {
  27         { .val = 0, .div = 32, },
  28         { .val = 1, .div = 8, },
  29         { .val = 2, .div = 2, },
  30         { .val = 3, .div = 1, },
  31 };
  32
  33 static const struct clk_div_table timer_div_table[] = {
  34         { .val = 0, .div = 256, },
  35         { .val = 1, .div = 1, },
  36 };
  37
  38 struct clps711x_clk {
  39         spinlock_t                      lock;
  40         struct clk_hw_onecell_data      clk_data;
  41 };
  42
  43 static void __init clps711x_clk_init_dt(struct device_node *np)
  44 {
  45         u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
  46         struct clps711x_clk *clps711x_clk;
  47         void __iomem *base;
  48
  49         WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
  50
  51         base = of_iomap(np, 0);
  52         BUG_ON(!base);
  53
  54         clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
  55                                            CLPS711X_CLK_MAX),
  56                                GFP_KERNEL);
  57         BUG_ON(!clps711x_clk);
  58
  59         spin_lock_init(&clps711x_clk->lock);
  60
  61         /* Read PLL multiplier value and sanity check */
  62         tmp = readl(base + CLPS711X_PLLR) >> 24;
  63         if (((tmp >= 10) && (tmp <= 50)) || !fref)
  64                 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
  65         else
  66                 f_pll = fref;
  67
  68         tmp = readl(base + CLPS711X_SYSFLG2);
  69         if (tmp & SYSFLG2_CKMODE) {
  70                 f_cpu = CLPS711X_EXT_FREQ;
  71                 f_bus = CLPS711X_EXT_FREQ;
  72                 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
  73                 f_pll = 0;
  74                 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
  75         } else {
  76                 f_cpu = f_pll;
  77                 if (f_cpu > 36864000)
  78                         f_bus = DIV_ROUND_UP(f_cpu, 2);
  79                 else
  80                         f_bus = 36864000 / 2;
  81                 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
  82                 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
  83         }
  84
  85         if (tmp & SYSFLG2_CKMODE) {
  86                 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
  87                         f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
  88                 else
  89                         f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
  90         } else
  91                 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
  92
  93         tmp = readl(base + CLPS711X_SYSCON1);
  94         /* Timer1 in free running mode.
  95          * Counter will wrap around to 0xffff when it underflows
  96          * and will continue to count down.
  97          */
  98         tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
  99         /* Timer2 in prescale mode.
 100          * Value writen is automatically re-loaded when
 101          * the counter underflows.
 102          */
 103         tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
 104         writel(tmp, base + CLPS711X_SYSCON1);
 105
 106         clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
 107                 clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
 108         clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
 109                 clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
 110         clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
 111                 clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
 112         clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
 113                 clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
 114         clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
 115                 clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
 116         clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
 117                 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
 118                                            base + CLPS711X_SYSCON1, 5, 1, 0,
 119                                            timer_div_table, &clps711x_clk->lock);
 120         clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
 121                 clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
 122                                            base + CLPS711X_SYSCON1, 7, 1, 0,
 123                                            timer_div_table, &clps711x_clk->lock);
 124         clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
 125                 clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
 126         clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
 127                 clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
 128         clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
 129                 clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
 130                                            base + CLPS711X_SYSCON1, 16, 2, 0,
 131                                            spi_div_table, &clps711x_clk->lock);
 132         clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
 133                 clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
 134         clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
 135                 clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
 136         for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
 137                 if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
 138                         pr_err("clk %i: register failed with %ld\n",
 139                                tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
 140
 141         clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
 142         of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 143                                &clps711x_clk->clk_data);
 144 }
 145 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);