1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments CDCE913/925/937/949 clock synthesizer driver
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
8 * Based on Linux kernel clk-cdce925.c.
14 #include <clk-uclass.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
19 #define MAX_NUMBER_OF_PLLS 4
20 #define MAX_NUMER_OF_OUTPUTS 9
22 #define CDCE9XX_REG_GLOBAL1 0x01
23 #define CDCE9XX_REG_Y1SPIPDIVH 0x02
24 #define CDCE9XX_REG_PDIV1L 0x03
25 #define CDCE9XX_REG_XCSEL 0x05
27 #define CDCE9XX_PDIV1_H_MASK 0x3
29 #define CDCE9XX_REG_PDIV(clk) (0x16 + (((clk) - 1) & 1) + \
30 ((clk) - 1) / 2 * 0x10)
32 #define CDCE9XX_PDIV_MASK 0x7f
34 #define CDCE9XX_BYTE_TRANSFER BIT(7)
36 struct cdce9xx_chip_info {
41 struct cdce9xx_clk_data {
43 struct cdce9xx_chip_info *chip;
47 static const struct cdce9xx_chip_info cdce913_chip_info = {
48 .num_plls = 1, .num_outputs = 3,
51 static const struct cdce9xx_chip_info cdce925_chip_info = {
52 .num_plls = 2, .num_outputs = 5,
55 static const struct cdce9xx_chip_info cdce937_chip_info = {
56 .num_plls = 3, .num_outputs = 7,
59 static const struct cdce9xx_chip_info cdce949_chip_info = {
60 .num_plls = 4, .num_outputs = 9,
63 static int cdce9xx_reg_read(struct udevice *dev, u8 addr, u8 *buf)
65 struct cdce9xx_clk_data *data = dev_get_priv(dev);
68 ret = dm_i2c_read(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, buf, 1);
70 dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
76 static int cdce9xx_reg_write(struct udevice *dev, u8 addr, u8 val)
78 struct cdce9xx_clk_data *data = dev_get_priv(dev);
81 ret = dm_i2c_write(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, &val, 1);
83 dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
89 static int cdce9xx_clk_request(struct clk *clk)
91 struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
93 if (clk->id > data->chip->num_outputs)
99 static int cdce9xx_clk_probe(struct udevice *dev)
101 struct cdce9xx_clk_data *data = dev_get_priv(dev);
102 struct cdce9xx_chip_info *chip = (void *)dev_get_driver_data(dev);
107 val = (u32)dev_read_addr_ptr(dev);
109 ret = i2c_get_chip(dev->parent, val, 1, &data->i2c);
111 dev_err(dev, "I2C probe failed.\n");
117 ret = clk_get_by_index(dev, 0, &clk);
118 data->xtal_rate = clk_get_rate(&clk);
120 val = dev_read_u32_default(dev, "xtal-load-pf", -1);
122 cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3);
127 static u16 cdce9xx_clk_get_pdiv(struct clk *clk)
134 ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
138 pdiv = (val & CDCE9XX_PDIV1_H_MASK) << 8;
140 ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV1L, &val);
146 ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
151 pdiv = val & CDCE9XX_PDIV_MASK;
157 static u32 cdce9xx_clk_get_parent_rate(struct clk *clk)
159 struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
161 return data->xtal_rate;
164 static ulong cdce9xx_clk_get_rate(struct clk *clk)
169 parent_rate = cdce9xx_clk_get_parent_rate(clk);
171 pdiv = cdce9xx_clk_get_pdiv(clk);
173 return parent_rate / pdiv;
176 static ulong cdce9xx_clk_set_rate(struct clk *clk, ulong rate)
184 parent_rate = cdce9xx_clk_get_parent_rate(clk);
186 pdiv = parent_rate / rate;
188 diff = rate - parent_rate / pdiv;
190 if (rate - parent_rate / (pdiv + 1) < diff)
194 ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
198 val &= ~CDCE9XX_PDIV1_H_MASK;
202 ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, val);
206 ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV1L,
211 ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
216 val &= ~CDCE9XX_PDIV_MASK;
220 ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV(clk->id),
229 static const struct udevice_id cdce9xx_clk_of_match[] = {
230 { .compatible = "ti,cdce913", .data = (u32)&cdce913_chip_info },
231 { .compatible = "ti,cdce925", .data = (u32)&cdce925_chip_info },
232 { .compatible = "ti,cdce937", .data = (u32)&cdce937_chip_info },
233 { .compatible = "ti,cdce949", .data = (u32)&cdce949_chip_info },
237 static const struct clk_ops cdce9xx_clk_ops = {
238 .request = cdce9xx_clk_request,
239 .get_rate = cdce9xx_clk_get_rate,
240 .set_rate = cdce9xx_clk_set_rate,
243 U_BOOT_DRIVER(cdce9xx_clk) = {
244 .name = "cdce9xx-clk",
246 .of_match = cdce9xx_clk_of_match,
247 .probe = cdce9xx_clk_probe,
248 .priv_auto = sizeof(struct cdce9xx_clk_data),
249 .ops = &cdce9xx_clk_ops,