drivers/clk/bcm/clk-raspberrypi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Raspberry Pi driver for firmware controlled clocks
   4  *
   5  * Even though clk-bcm2835 provides an interface to the hardware registers for
   6  * the system clocks we've had to factor out 'pllb' as the firmware 'owns' it.
   7  * We're not allowed to change it directly as we might race with the
   8  * over-temperature and under-voltage protections provided by the firmware.
   9  *
  10  * Copyright (C) 2019 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
  11  */
  12
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <soc/bcm2835/raspberrypi-firmware.h>
  20
  21 #define RPI_FIRMWARE_ARM_CLK_ID         0x00000003
  22
  23 #define RPI_FIRMWARE_STATE_ENABLE_BIT   BIT(0)
  24 #define RPI_FIRMWARE_STATE_WAIT_BIT     BIT(1)
  25
  26 /*
  27  * Even though the firmware interface alters 'pllb' the frequencies are
  28  * provided as per 'pllb_arm'. We need to scale before passing them trough.
  29  */
  30 #define RPI_FIRMWARE_PLLB_ARM_DIV_RATE  2
  31
  32 #define A2W_PLL_FRAC_BITS               20
  33
  34 struct raspberrypi_clk {
  35         struct device *dev;
  36         struct rpi_firmware *firmware;
  37         struct platform_device *cpufreq;
  38 };
  39
  40 struct raspberrypi_clk_data {
  41         struct clk_hw hw;
  42         unsigned id;
  43
  44         unsigned long min_rate;
  45         unsigned long max_rate;
  46
  47         struct raspberrypi_clk *rpi;
  48 };
  49
  50 /*
  51  * Structure of the message passed to Raspberry Pi's firmware in order to
  52  * change clock rates. The 'disable_turbo' option is only available to the ARM
  53  * clock (pllb) which we enable by default as turbo mode will alter multiple
  54  * clocks at once.
  55  *
  56  * Even though we're able to access the clock registers directly we're bound to
  57  * use the firmware interface as the firmware ultimately takes care of
  58  * mitigating overheating/undervoltage situations and we would be changing
  59  * frequencies behind his back.
  60  *
  61  * For more information on the firmware interface check:
  62  * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
  63  */
  64 struct raspberrypi_firmware_prop {
  65         __le32 id;
  66         __le32 val;
  67         __le32 disable_turbo;
  68 } __packed;
  69
  70 static int raspberrypi_clock_property(struct rpi_firmware *firmware, u32 tag,
  71                                       u32 clk, u32 *val)
  72 {
  73         struct raspberrypi_firmware_prop msg = {
  74                 .id = cpu_to_le32(clk),
  75                 .val = cpu_to_le32(*val),
  76                 .disable_turbo = cpu_to_le32(1),
  77         };
  78         int ret;
  79
  80         ret = rpi_firmware_property(firmware, tag, &msg, sizeof(msg));
  81         if (ret)
  82                 return ret;
  83
  84         *val = le32_to_cpu(msg.val);
  85
  86         return 0;
  87 }
  88
  89 static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
  90 {
  91         struct raspberrypi_clk_data *data =
  92                 container_of(hw, struct raspberrypi_clk_data, hw);
  93         struct raspberrypi_clk *rpi = data->rpi;
  94         u32 val = 0;
  95         int ret;
  96
  97         ret = raspberrypi_clock_property(rpi->firmware,
  98                                          RPI_FIRMWARE_GET_CLOCK_STATE,
  99                                          data->id, &val);
 100         if (ret)
 101                 return 0;
 102
 103         return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT);
 104 }
 105
 106
 107 static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
 108                                                  unsigned long parent_rate)
 109 {
 110         struct raspberrypi_clk_data *data =
 111                 container_of(hw, struct raspberrypi_clk_data, hw);
 112         struct raspberrypi_clk *rpi = data->rpi;
 113         u32 val = 0;
 114         int ret;
 115
 116         ret = raspberrypi_clock_property(rpi->firmware,
 117                                          RPI_FIRMWARE_GET_CLOCK_RATE,
 118                                          data->id, &val);
 119         if (ret)
 120                 return ret;
 121
 122         return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
 123 }
 124
 125 static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 126                                        unsigned long parent_rate)
 127 {
 128         struct raspberrypi_clk_data *data =
 129                 container_of(hw, struct raspberrypi_clk_data, hw);
 130         struct raspberrypi_clk *rpi = data->rpi;
 131         u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
 132         int ret;
 133
 134         ret = raspberrypi_clock_property(rpi->firmware,
 135                                          RPI_FIRMWARE_SET_CLOCK_RATE,
 136                                          data->id, &new_rate);
 137         if (ret)
 138                 dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
 139                                     clk_hw_get_name(hw), ret);
 140
 141         return ret;
 142 }
 143
 144 /*
 145  * Sadly there is no firmware rate rounding interface. We borrowed it from
 146  * clk-bcm2835.
 147  */
 148 static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
 149                                           struct clk_rate_request *req)
 150 {
 151         struct raspberrypi_clk_data *data =
 152                 container_of(hw, struct raspberrypi_clk_data, hw);
 153         u64 div, final_rate;
 154         u32 ndiv, fdiv;
 155
 156         /* We can't use req->rate directly as it would overflow */
 157         final_rate = clamp(req->rate, data->min_rate, data->max_rate);
 158
 159         div = (u64)final_rate << A2W_PLL_FRAC_BITS;
 160         do_div(div, req->best_parent_rate);
 161
 162         ndiv = div >> A2W_PLL_FRAC_BITS;
 163         fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
 164
 165         final_rate = ((u64)req->best_parent_rate *
 166                                         ((ndiv << A2W_PLL_FRAC_BITS) + fdiv));
 167
 168         req->rate = final_rate >> A2W_PLL_FRAC_BITS;
 169
 170         return 0;
 171 }
 172
 173 static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
 174         .is_prepared = raspberrypi_fw_pll_is_on,
 175         .recalc_rate = raspberrypi_fw_pll_get_rate,
 176         .set_rate = raspberrypi_fw_pll_set_rate,
 177         .determine_rate = raspberrypi_pll_determine_rate,
 178 };
 179
 180 static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
 181 {
 182         struct raspberrypi_clk_data *data;
 183         struct clk_init_data init = {};
 184         u32 min_rate = 0, max_rate = 0;
 185         int ret;
 186
 187         data = devm_kzalloc(rpi->dev, sizeof(*data), GFP_KERNEL);
 188         if (!data)
 189                 return -ENOMEM;
 190         data->rpi = rpi;
 191         data->id = RPI_FIRMWARE_ARM_CLK_ID;
 192
 193         /* All of the PLLs derive from the external oscillator. */
 194         init.parent_names = (const char *[]){ "osc" };
 195         init.num_parents = 1;
 196         init.name = "pllb";
 197         init.ops = &raspberrypi_firmware_pll_clk_ops;
 198         init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
 199
 200         /* Get min & max rates set by the firmware */
 201         ret = raspberrypi_clock_property(rpi->firmware,
 202                                          RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
 203                                          data->id, &min_rate);
 204         if (ret) {
 205                 dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
 206                         init.name, ret);
 207                 return ret;
 208         }
 209
 210         ret = raspberrypi_clock_property(rpi->firmware,
 211                                          RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
 212                                          data->id, &max_rate);
 213         if (ret) {
 214                 dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
 215                         init.name, ret);
 216                 return ret;
 217         }
 218
 219         if (!min_rate || !max_rate) {
 220                 dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
 221                         min_rate, max_rate);
 222                 return -EINVAL;
 223         }
 224
 225         dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
 226                  min_rate, max_rate);
 227
 228         data->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
 229         data->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
 230
 231         data->hw.init = &init;
 232
 233         return devm_clk_hw_register(rpi->dev, &data->hw);
 234 }
 235
 236 static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
 237         .mult = 1,
 238         .div = 2,
 239         .hw.init = &(struct clk_init_data) {
 240                 .name           = "pllb_arm",
 241                 .parent_names   = (const char *[]){ "pllb" },
 242                 .num_parents    = 1,
 243                 .ops            = &clk_fixed_factor_ops,
 244                 .flags          = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 245         },
 246 };
 247
 248 static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
 249 {
 250         int ret;
 251
 252         ret = devm_clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
 253         if (ret) {
 254                 dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
 255                 return ret;
 256         }
 257
 258         ret = devm_clk_hw_register_clkdev(rpi->dev,
 259                                           &raspberrypi_clk_pllb_arm.hw,
 260                                           NULL, "cpu0");
 261         if (ret) {
 262                 dev_err(rpi->dev, "Failed to initialize clkdev\n");
 263                 return ret;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int raspberrypi_clk_probe(struct platform_device *pdev)
 270 {
 271         struct device_node *firmware_node;
 272         struct device *dev = &pdev->dev;
 273         struct rpi_firmware *firmware;
 274         struct raspberrypi_clk *rpi;
 275         int ret;
 276
 277         firmware_node = of_parse_phandle(dev->of_node, "raspberrypi,firmware", 0);
 278         if (!firmware_node) {
 279                 dev_err(dev, "Missing firmware node\n");
 280                 return -ENOENT;
 281         }
 282
 283         firmware = rpi_firmware_get(firmware_node);
 284         if (!firmware)
 285                 return -EPROBE_DEFER;
 286
 287         rpi = devm_kzalloc(dev, sizeof(*rpi), GFP_KERNEL);
 288         if (!rpi)
 289                 return -ENOMEM;
 290
 291         rpi->dev = dev;
 292         rpi->firmware = firmware;
 293         platform_set_drvdata(pdev, rpi);
 294
 295         ret = raspberrypi_register_pllb(rpi);
 296         if (ret) {
 297                 dev_err(dev, "Failed to initialize pllb, %d\n", ret);
 298                 return ret;
 299         }
 300
 301         ret = raspberrypi_register_pllb_arm(rpi);
 302         if (ret)
 303                 return ret;
 304
 305         rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
 306                                                      -1, NULL, 0);
 307
 308         return 0;
 309 }
 310
 311 static int raspberrypi_clk_remove(struct platform_device *pdev)
 312 {
 313         struct raspberrypi_clk *rpi = platform_get_drvdata(pdev);
 314
 315         platform_device_unregister(rpi->cpufreq);
 316
 317         return 0;
 318 }
 319
 320 static const struct of_device_id raspberrypi_clk_match[] = {
 321         { .compatible = "raspberrypi,firmware-clocks" },
 322         { },
 323 };
 324 MODULE_DEVICE_TABLE(of, raspberrypi_clk_match);
 325
 326 static struct platform_driver raspberrypi_clk_driver = {
 327         .driver = {
 328                 .name = "raspberrypi-clk",
 329                 .of_match_table = raspberrypi_clk_match,
 330         },
 331         .probe          = raspberrypi_clk_probe,
 332         .remove         = raspberrypi_clk_remove,
 333 };
 334 module_platform_driver(raspberrypi_clk_driver);
 335
 336 MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de>");
 337 MODULE_DESCRIPTION("Raspberry Pi firmware clock driver");
 338 MODULE_LICENSE("GPL");
 339 MODULE_ALIAS("platform:raspberrypi-clk");