1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010,2015 Broadcom
4 * Copyright (C) 2012 Stephen Warren
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
11 * oscillator running at 19.2Mhz. After the oscillator there are 5
12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
13 * and "HDMI displays". Those 5 PLLs each can divide their output to
14 * produce up to 4 channels. Finally, there is the level of clocks to
15 * be consumed by other hardware components (like "H264" or "HDMI
16 * state machine"), which divide off of some subset of the PLL
19 * All of the clocks in the tree are exposed in the DT, because the DT
20 * may want to make assignments of the final layer of clocks to the
21 * PLL channels, and some components of the hardware will actually
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
28 #include <linux/clkdev.h>
29 #include <linux/clk.h>
30 #include <linux/debugfs.h>
31 #include <linux/delay.h>
33 #include <linux/math.h>
34 #include <linux/module.h>
35 #include <linux/of_device.h>
36 #include <linux/platform_device.h>
37 #include <linux/slab.h>
38 #include <dt-bindings/clock/bcm2835.h>
40 #define CM_PASSWORD 0x5a000000
42 #define CM_GNRICCTL 0x000
43 #define CM_GNRICDIV 0x004
44 # define CM_DIV_FRAC_BITS 12
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
47 #define CM_VPUCTL 0x008
48 #define CM_VPUDIV 0x00c
49 #define CM_SYSCTL 0x010
50 #define CM_SYSDIV 0x014
51 #define CM_PERIACTL 0x018
52 #define CM_PERIADIV 0x01c
53 #define CM_PERIICTL 0x020
54 #define CM_PERIIDIV 0x024
55 #define CM_H264CTL 0x028
56 #define CM_H264DIV 0x02c
57 #define CM_ISPCTL 0x030
58 #define CM_ISPDIV 0x034
59 #define CM_V3DCTL 0x038
60 #define CM_V3DDIV 0x03c
61 #define CM_CAM0CTL 0x040
62 #define CM_CAM0DIV 0x044
63 #define CM_CAM1CTL 0x048
64 #define CM_CAM1DIV 0x04c
65 #define CM_CCP2CTL 0x050
66 #define CM_CCP2DIV 0x054
67 #define CM_DSI0ECTL 0x058
68 #define CM_DSI0EDIV 0x05c
69 #define CM_DSI0PCTL 0x060
70 #define CM_DSI0PDIV 0x064
71 #define CM_DPICTL 0x068
72 #define CM_DPIDIV 0x06c
73 #define CM_GP0CTL 0x070
74 #define CM_GP0DIV 0x074
75 #define CM_GP1CTL 0x078
76 #define CM_GP1DIV 0x07c
77 #define CM_GP2CTL 0x080
78 #define CM_GP2DIV 0x084
79 #define CM_HSMCTL 0x088
80 #define CM_HSMDIV 0x08c
81 #define CM_OTPCTL 0x090
82 #define CM_OTPDIV 0x094
83 #define CM_PCMCTL 0x098
84 #define CM_PCMDIV 0x09c
85 #define CM_PWMCTL 0x0a0
86 #define CM_PWMDIV 0x0a4
87 #define CM_SLIMCTL 0x0a8
88 #define CM_SLIMDIV 0x0ac
89 #define CM_SMICTL 0x0b0
90 #define CM_SMIDIV 0x0b4
91 /* no definition for 0x0b8 and 0x0bc */
92 #define CM_TCNTCTL 0x0c0
93 # define CM_TCNT_SRC1_SHIFT 12
94 #define CM_TCNTCNT 0x0c4
95 #define CM_TECCTL 0x0c8
96 #define CM_TECDIV 0x0cc
97 #define CM_TD0CTL 0x0d0
98 #define CM_TD0DIV 0x0d4
99 #define CM_TD1CTL 0x0d8
100 #define CM_TD1DIV 0x0dc
101 #define CM_TSENSCTL 0x0e0
102 #define CM_TSENSDIV 0x0e4
103 #define CM_TIMERCTL 0x0e8
104 #define CM_TIMERDIV 0x0ec
105 #define CM_UARTCTL 0x0f0
106 #define CM_UARTDIV 0x0f4
107 #define CM_VECCTL 0x0f8
108 #define CM_VECDIV 0x0fc
109 #define CM_PULSECTL 0x190
110 #define CM_PULSEDIV 0x194
111 #define CM_SDCCTL 0x1a8
112 #define CM_SDCDIV 0x1ac
113 #define CM_ARMCTL 0x1b0
114 #define CM_AVEOCTL 0x1b8
115 #define CM_AVEODIV 0x1bc
116 #define CM_EMMCCTL 0x1c0
117 #define CM_EMMCDIV 0x1c4
118 #define CM_EMMC2CTL 0x1d0
119 #define CM_EMMC2DIV 0x1d4
121 /* General bits for the CM_*CTL regs */
122 # define CM_ENABLE BIT(4)
123 # define CM_KILL BIT(5)
124 # define CM_GATE_BIT 6
125 # define CM_GATE BIT(CM_GATE_BIT)
126 # define CM_BUSY BIT(7)
127 # define CM_BUSYD BIT(8)
128 # define CM_FRAC BIT(9)
129 # define CM_SRC_SHIFT 0
130 # define CM_SRC_BITS 4
131 # define CM_SRC_MASK 0xf
132 # define CM_SRC_GND 0
133 # define CM_SRC_OSC 1
134 # define CM_SRC_TESTDEBUG0 2
135 # define CM_SRC_TESTDEBUG1 3
136 # define CM_SRC_PLLA_CORE 4
137 # define CM_SRC_PLLA_PER 4
138 # define CM_SRC_PLLC_CORE0 5
139 # define CM_SRC_PLLC_PER 5
140 # define CM_SRC_PLLC_CORE1 8
141 # define CM_SRC_PLLD_CORE 6
142 # define CM_SRC_PLLD_PER 6
143 # define CM_SRC_PLLH_AUX 7
144 # define CM_SRC_PLLC_CORE1 8
145 # define CM_SRC_PLLC_CORE2 9
147 #define CM_OSCCOUNT 0x100
149 #define CM_PLLA 0x104
150 # define CM_PLL_ANARST BIT(8)
151 # define CM_PLLA_HOLDPER BIT(7)
152 # define CM_PLLA_LOADPER BIT(6)
153 # define CM_PLLA_HOLDCORE BIT(5)
154 # define CM_PLLA_LOADCORE BIT(4)
155 # define CM_PLLA_HOLDCCP2 BIT(3)
156 # define CM_PLLA_LOADCCP2 BIT(2)
157 # define CM_PLLA_HOLDDSI0 BIT(1)
158 # define CM_PLLA_LOADDSI0 BIT(0)
160 #define CM_PLLC 0x108
161 # define CM_PLLC_HOLDPER BIT(7)
162 # define CM_PLLC_LOADPER BIT(6)
163 # define CM_PLLC_HOLDCORE2 BIT(5)
164 # define CM_PLLC_LOADCORE2 BIT(4)
165 # define CM_PLLC_HOLDCORE1 BIT(3)
166 # define CM_PLLC_LOADCORE1 BIT(2)
167 # define CM_PLLC_HOLDCORE0 BIT(1)
168 # define CM_PLLC_LOADCORE0 BIT(0)
170 #define CM_PLLD 0x10c
171 # define CM_PLLD_HOLDPER BIT(7)
172 # define CM_PLLD_LOADPER BIT(6)
173 # define CM_PLLD_HOLDCORE BIT(5)
174 # define CM_PLLD_LOADCORE BIT(4)
175 # define CM_PLLD_HOLDDSI1 BIT(3)
176 # define CM_PLLD_LOADDSI1 BIT(2)
177 # define CM_PLLD_HOLDDSI0 BIT(1)
178 # define CM_PLLD_LOADDSI0 BIT(0)
180 #define CM_PLLH 0x110
181 # define CM_PLLH_LOADRCAL BIT(2)
182 # define CM_PLLH_LOADAUX BIT(1)
183 # define CM_PLLH_LOADPIX BIT(0)
185 #define CM_LOCK 0x114
186 # define CM_LOCK_FLOCKH BIT(12)
187 # define CM_LOCK_FLOCKD BIT(11)
188 # define CM_LOCK_FLOCKC BIT(10)
189 # define CM_LOCK_FLOCKB BIT(9)
190 # define CM_LOCK_FLOCKA BIT(8)
192 #define CM_EVENT 0x118
193 #define CM_DSI1ECTL 0x158
194 #define CM_DSI1EDIV 0x15c
195 #define CM_DSI1PCTL 0x160
196 #define CM_DSI1PDIV 0x164
197 #define CM_DFTCTL 0x168
198 #define CM_DFTDIV 0x16c
200 #define CM_PLLB 0x170
201 # define CM_PLLB_HOLDARM BIT(1)
202 # define CM_PLLB_LOADARM BIT(0)
204 #define A2W_PLLA_CTRL 0x1100
205 #define A2W_PLLC_CTRL 0x1120
206 #define A2W_PLLD_CTRL 0x1140
207 #define A2W_PLLH_CTRL 0x1160
208 #define A2W_PLLB_CTRL 0x11e0
209 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
210 # define A2W_PLL_CTRL_PWRDN BIT(16)
211 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
212 # define A2W_PLL_CTRL_PDIV_SHIFT 12
213 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
214 # define A2W_PLL_CTRL_NDIV_SHIFT 0
216 #define A2W_PLLA_ANA0 0x1010
217 #define A2W_PLLC_ANA0 0x1030
218 #define A2W_PLLD_ANA0 0x1050
219 #define A2W_PLLH_ANA0 0x1070
220 #define A2W_PLLB_ANA0 0x10f0
222 #define A2W_PLL_KA_SHIFT 7
223 #define A2W_PLL_KA_MASK GENMASK(9, 7)
224 #define A2W_PLL_KI_SHIFT 19
225 #define A2W_PLL_KI_MASK GENMASK(21, 19)
226 #define A2W_PLL_KP_SHIFT 15
227 #define A2W_PLL_KP_MASK GENMASK(18, 15)
229 #define A2W_PLLH_KA_SHIFT 19
230 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
231 #define A2W_PLLH_KI_LOW_SHIFT 22
232 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
233 #define A2W_PLLH_KI_HIGH_SHIFT 0
234 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
235 #define A2W_PLLH_KP_SHIFT 1
236 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
238 #define A2W_XOSC_CTRL 0x1190
239 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
240 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
241 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
242 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
243 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
244 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
245 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
246 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
248 #define A2W_PLLA_FRAC 0x1200
249 #define A2W_PLLC_FRAC 0x1220
250 #define A2W_PLLD_FRAC 0x1240
251 #define A2W_PLLH_FRAC 0x1260
252 #define A2W_PLLB_FRAC 0x12e0
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
254 # define A2W_PLL_FRAC_BITS 20
256 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
257 #define A2W_PLL_DIV_BITS 8
258 #define A2W_PLL_DIV_SHIFT 0
260 #define A2W_PLLA_DSI0 0x1300
261 #define A2W_PLLA_CORE 0x1400
262 #define A2W_PLLA_PER 0x1500
263 #define A2W_PLLA_CCP2 0x1600
265 #define A2W_PLLC_CORE2 0x1320
266 #define A2W_PLLC_CORE1 0x1420
267 #define A2W_PLLC_PER 0x1520
268 #define A2W_PLLC_CORE0 0x1620
270 #define A2W_PLLD_DSI0 0x1340
271 #define A2W_PLLD_CORE 0x1440
272 #define A2W_PLLD_PER 0x1540
273 #define A2W_PLLD_DSI1 0x1640
275 #define A2W_PLLH_AUX 0x1360
276 #define A2W_PLLH_RCAL 0x1460
277 #define A2W_PLLH_PIX 0x1560
278 #define A2W_PLLH_STS 0x1660
280 #define A2W_PLLH_CTRLR 0x1960
281 #define A2W_PLLH_FRACR 0x1a60
282 #define A2W_PLLH_AUXR 0x1b60
283 #define A2W_PLLH_RCALR 0x1c60
284 #define A2W_PLLH_PIXR 0x1d60
285 #define A2W_PLLH_STSR 0x1e60
287 #define A2W_PLLB_ARM 0x13e0
288 #define A2W_PLLB_SP0 0x14e0
289 #define A2W_PLLB_SP1 0x15e0
290 #define A2W_PLLB_SP2 0x16e0
292 #define LOCK_TIMEOUT_NS 100000000
293 #define BCM2835_MAX_FB_RATE 1750000000u
295 #define SOC_BCM2835 BIT(0)
296 #define SOC_BCM2711 BIT(1)
297 #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
300 * Names of clocks used within the driver that need to be replaced
301 * with an external parent's name. This array is in the order that
302 * the clocks node in the DT references external clocks.
304 static const char *const cprman_parent_names[] = {
314 struct bcm2835_cprman {
317 spinlock_t regs_lock; /* spinlock for all clocks */
321 * Real names of cprman clock parents looked up through
322 * of_clk_get_parent_name(), which will be used in the
323 * parent_names[] arrays for clock registration.
325 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
328 struct clk_hw_onecell_data onecell;
331 struct cprman_plat_data {
335 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
337 writel(CM_PASSWORD | val, cprman->regs + reg);
340 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
342 return readl(cprman->regs + reg);
345 /* Does a cycle of measuring a clock through the TCNT clock, which may
346 * source from many other clocks in the system.
348 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
351 u32 osccount = 19200; /* 1ms */
355 spin_lock(&cprman->regs_lock);
357 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
359 cprman_write(cprman, CM_TCNTCTL,
360 (tcnt_mux & CM_SRC_MASK) |
361 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
363 cprman_write(cprman, CM_OSCCOUNT, osccount);
365 /* do a kind delay at the start */
368 /* Finish off whatever is left of OSCCOUNT */
369 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
370 while (cprman_read(cprman, CM_OSCCOUNT)) {
371 if (ktime_after(ktime_get(), timeout)) {
372 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
379 /* Wait for BUSY to clear. */
380 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
381 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
382 if (ktime_after(ktime_get(), timeout)) {
383 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
390 count = cprman_read(cprman, CM_TCNTCNT);
392 cprman_write(cprman, CM_TCNTCTL, 0);
395 spin_unlock(&cprman->regs_lock);
400 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
401 const struct debugfs_reg32 *regs,
402 size_t nregs, struct dentry *dentry)
404 struct debugfs_regset32 *regset;
406 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
411 regset->nregs = nregs;
412 regset->base = cprman->regs + base;
414 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
417 struct bcm2835_pll_data {
423 u32 reference_enable_mask;
424 /* Bit in CM_LOCK to indicate when the PLL has locked. */
428 const struct bcm2835_pll_ana_bits *ana;
430 unsigned long min_rate;
431 unsigned long max_rate;
433 * Highest rate for the VCO before we have to use the
436 unsigned long max_fb_rate;
439 struct bcm2835_pll_ana_bits {
449 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
452 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
453 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
454 .mask3 = A2W_PLL_KA_MASK,
455 .set3 = (2 << A2W_PLL_KA_SHIFT),
456 .fb_prediv_mask = BIT(14),
459 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
460 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
461 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
462 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
463 .set1 = (6 << A2W_PLLH_KP_SHIFT),
466 .fb_prediv_mask = BIT(11),
469 struct bcm2835_pll_divider_data {
471 const char *source_pll;
482 struct bcm2835_clock_data {
485 const char *const *parents;
488 /* Bitmap encoding which parents accept rate change propagation. */
489 unsigned int set_rate_parent;
494 /* Number of integer bits in the divider */
496 /* Number of fractional bits in the divider */
510 struct bcm2835_gate_data {
519 struct bcm2835_cprman *cprman;
520 const struct bcm2835_pll_data *data;
523 static int bcm2835_pll_is_on(struct clk_hw *hw)
525 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
526 struct bcm2835_cprman *cprman = pll->cprman;
527 const struct bcm2835_pll_data *data = pll->data;
529 return cprman_read(cprman, data->a2w_ctrl_reg) &
530 A2W_PLL_CTRL_PRST_DISABLE;
533 static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
534 const struct bcm2835_pll_data *data)
537 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
539 * for to for VCO RANGE bits.
541 if (cprman->soc & SOC_BCM2711)
544 return data->ana->fb_prediv_mask;
547 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
548 unsigned long parent_rate,
549 u32 *ndiv, u32 *fdiv)
553 div = (u64)rate << A2W_PLL_FRAC_BITS;
554 do_div(div, parent_rate);
556 *ndiv = div >> A2W_PLL_FRAC_BITS;
557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
560 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
561 u32 ndiv, u32 fdiv, u32 pdiv)
568 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
570 return rate >> A2W_PLL_FRAC_BITS;
573 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
574 unsigned long *parent_rate)
576 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
577 const struct bcm2835_pll_data *data = pll->data;
580 rate = clamp(rate, data->min_rate, data->max_rate);
582 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
584 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
587 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
588 unsigned long parent_rate)
590 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
591 struct bcm2835_cprman *cprman = pll->cprman;
592 const struct bcm2835_pll_data *data = pll->data;
593 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
594 u32 ndiv, pdiv, fdiv;
597 if (parent_rate == 0)
600 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
601 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
602 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
603 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
604 bcm2835_pll_get_prediv_mask(cprman, data);
611 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
614 static void bcm2835_pll_off(struct clk_hw *hw)
616 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
617 struct bcm2835_cprman *cprman = pll->cprman;
618 const struct bcm2835_pll_data *data = pll->data;
620 spin_lock(&cprman->regs_lock);
621 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
622 cprman_write(cprman, data->a2w_ctrl_reg,
623 cprman_read(cprman, data->a2w_ctrl_reg) |
625 spin_unlock(&cprman->regs_lock);
628 static int bcm2835_pll_on(struct clk_hw *hw)
630 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
631 struct bcm2835_cprman *cprman = pll->cprman;
632 const struct bcm2835_pll_data *data = pll->data;
635 cprman_write(cprman, data->a2w_ctrl_reg,
636 cprman_read(cprman, data->a2w_ctrl_reg) &
637 ~A2W_PLL_CTRL_PWRDN);
639 /* Take the PLL out of reset. */
640 spin_lock(&cprman->regs_lock);
641 cprman_write(cprman, data->cm_ctrl_reg,
642 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
643 spin_unlock(&cprman->regs_lock);
645 /* Wait for the PLL to lock. */
646 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
647 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
648 if (ktime_after(ktime_get(), timeout)) {
649 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
650 clk_hw_get_name(hw));
657 cprman_write(cprman, data->a2w_ctrl_reg,
658 cprman_read(cprman, data->a2w_ctrl_reg) |
659 A2W_PLL_CTRL_PRST_DISABLE);
665 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
670 * ANA register setup is done as a series of writes to
671 * ANA3-ANA0, in that order. This lets us write all 4
672 * registers as a single cycle of the serdes interface (taking
673 * 100 xosc clocks), whereas if we were to update ana0, 1, and
674 * 3 individually through their partial-write registers, each
675 * would be their own serdes cycle.
677 for (i = 3; i >= 0; i--)
678 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
681 static int bcm2835_pll_set_rate(struct clk_hw *hw,
682 unsigned long rate, unsigned long parent_rate)
684 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
685 struct bcm2835_cprman *cprman = pll->cprman;
686 const struct bcm2835_pll_data *data = pll->data;
687 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
688 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
689 u32 ndiv, fdiv, a2w_ctl;
693 if (rate > data->max_fb_rate) {
694 use_fb_prediv = true;
697 use_fb_prediv = false;
700 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
702 for (i = 3; i >= 0; i--)
703 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
705 was_using_prediv = ana[1] & prediv_mask;
707 ana[0] &= ~data->ana->mask0;
708 ana[0] |= data->ana->set0;
709 ana[1] &= ~data->ana->mask1;
710 ana[1] |= data->ana->set1;
711 ana[3] &= ~data->ana->mask3;
712 ana[3] |= data->ana->set3;
714 if (was_using_prediv && !use_fb_prediv) {
715 ana[1] &= ~prediv_mask;
716 do_ana_setup_first = true;
717 } else if (!was_using_prediv && use_fb_prediv) {
718 ana[1] |= prediv_mask;
719 do_ana_setup_first = false;
721 do_ana_setup_first = true;
724 /* Unmask the reference clock from the oscillator. */
725 spin_lock(&cprman->regs_lock);
726 cprman_write(cprman, A2W_XOSC_CTRL,
727 cprman_read(cprman, A2W_XOSC_CTRL) |
728 data->reference_enable_mask);
729 spin_unlock(&cprman->regs_lock);
731 if (do_ana_setup_first)
732 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
734 /* Set the PLL multiplier from the oscillator. */
735 cprman_write(cprman, data->frac_reg, fdiv);
737 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
738 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
739 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
740 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
741 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
742 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
744 if (!do_ana_setup_first)
745 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
750 static void bcm2835_pll_debug_init(struct clk_hw *hw,
751 struct dentry *dentry)
753 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
754 struct bcm2835_cprman *cprman = pll->cprman;
755 const struct bcm2835_pll_data *data = pll->data;
756 struct debugfs_reg32 *regs;
758 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
762 regs[0].name = "cm_ctrl";
763 regs[0].offset = data->cm_ctrl_reg;
764 regs[1].name = "a2w_ctrl";
765 regs[1].offset = data->a2w_ctrl_reg;
766 regs[2].name = "frac";
767 regs[2].offset = data->frac_reg;
768 regs[3].name = "ana0";
769 regs[3].offset = data->ana_reg_base + 0 * 4;
770 regs[4].name = "ana1";
771 regs[4].offset = data->ana_reg_base + 1 * 4;
772 regs[5].name = "ana2";
773 regs[5].offset = data->ana_reg_base + 2 * 4;
774 regs[6].name = "ana3";
775 regs[6].offset = data->ana_reg_base + 3 * 4;
777 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
780 static const struct clk_ops bcm2835_pll_clk_ops = {
781 .is_prepared = bcm2835_pll_is_on,
782 .prepare = bcm2835_pll_on,
783 .unprepare = bcm2835_pll_off,
784 .recalc_rate = bcm2835_pll_get_rate,
785 .set_rate = bcm2835_pll_set_rate,
786 .round_rate = bcm2835_pll_round_rate,
787 .debug_init = bcm2835_pll_debug_init,
790 struct bcm2835_pll_divider {
791 struct clk_divider div;
792 struct bcm2835_cprman *cprman;
793 const struct bcm2835_pll_divider_data *data;
796 static struct bcm2835_pll_divider *
797 bcm2835_pll_divider_from_hw(struct clk_hw *hw)
799 return container_of(hw, struct bcm2835_pll_divider, div.hw);
802 static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
804 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
805 struct bcm2835_cprman *cprman = divider->cprman;
806 const struct bcm2835_pll_divider_data *data = divider->data;
808 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
811 static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
812 struct clk_rate_request *req)
814 return clk_divider_ops.determine_rate(hw, req);
817 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
818 unsigned long parent_rate)
820 return clk_divider_ops.recalc_rate(hw, parent_rate);
823 static void bcm2835_pll_divider_off(struct clk_hw *hw)
825 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
826 struct bcm2835_cprman *cprman = divider->cprman;
827 const struct bcm2835_pll_divider_data *data = divider->data;
829 spin_lock(&cprman->regs_lock);
830 cprman_write(cprman, data->cm_reg,
831 (cprman_read(cprman, data->cm_reg) &
832 ~data->load_mask) | data->hold_mask);
833 cprman_write(cprman, data->a2w_reg,
834 cprman_read(cprman, data->a2w_reg) |
835 A2W_PLL_CHANNEL_DISABLE);
836 spin_unlock(&cprman->regs_lock);
839 static int bcm2835_pll_divider_on(struct clk_hw *hw)
841 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
842 struct bcm2835_cprman *cprman = divider->cprman;
843 const struct bcm2835_pll_divider_data *data = divider->data;
845 spin_lock(&cprman->regs_lock);
846 cprman_write(cprman, data->a2w_reg,
847 cprman_read(cprman, data->a2w_reg) &
848 ~A2W_PLL_CHANNEL_DISABLE);
850 cprman_write(cprman, data->cm_reg,
851 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
852 spin_unlock(&cprman->regs_lock);
857 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
859 unsigned long parent_rate)
861 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
862 struct bcm2835_cprman *cprman = divider->cprman;
863 const struct bcm2835_pll_divider_data *data = divider->data;
864 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
866 div = DIV_ROUND_UP_ULL(parent_rate, rate);
868 div = min(div, max_div);
872 cprman_write(cprman, data->a2w_reg, div);
873 cm = cprman_read(cprman, data->cm_reg);
874 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
875 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
880 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
881 struct dentry *dentry)
883 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
884 struct bcm2835_cprman *cprman = divider->cprman;
885 const struct bcm2835_pll_divider_data *data = divider->data;
886 struct debugfs_reg32 *regs;
888 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
893 regs[0].offset = data->cm_reg;
894 regs[1].name = "a2w";
895 regs[1].offset = data->a2w_reg;
897 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
900 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
901 .is_prepared = bcm2835_pll_divider_is_on,
902 .prepare = bcm2835_pll_divider_on,
903 .unprepare = bcm2835_pll_divider_off,
904 .recalc_rate = bcm2835_pll_divider_get_rate,
905 .set_rate = bcm2835_pll_divider_set_rate,
906 .determine_rate = bcm2835_pll_divider_determine_rate,
907 .debug_init = bcm2835_pll_divider_debug_init,
911 * The CM dividers do fixed-point division, so we can't use the
912 * generic integer divider code like the PLL dividers do (and we can't
913 * fake it by having some fixed shifts preceding it in the clock tree,
914 * because we'd run out of bits in a 32-bit unsigned long).
916 struct bcm2835_clock {
918 struct bcm2835_cprman *cprman;
919 const struct bcm2835_clock_data *data;
922 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
924 return container_of(hw, struct bcm2835_clock, hw);
927 static int bcm2835_clock_is_on(struct clk_hw *hw)
929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
930 struct bcm2835_cprman *cprman = clock->cprman;
931 const struct bcm2835_clock_data *data = clock->data;
933 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
936 static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
938 unsigned long parent_rate)
940 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
941 const struct bcm2835_clock_data *data = clock->data;
942 u32 unused_frac_mask =
943 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
944 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
946 u32 div, mindiv, maxdiv;
948 rem = do_div(temp, rate);
950 div &= ~unused_frac_mask;
952 /* different clamping limits apply for a mash clock */
953 if (data->is_mash_clock) {
954 /* clamp to min divider of 2 */
955 mindiv = 2 << CM_DIV_FRAC_BITS;
956 /* clamp to the highest possible integer divider */
957 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
959 /* clamp to min divider of 1 */
960 mindiv = 1 << CM_DIV_FRAC_BITS;
961 /* clamp to the highest possible fractional divider */
962 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
963 CM_DIV_FRAC_BITS - data->frac_bits);
966 /* apply the clamping limits */
967 div = max_t(u32, div, mindiv);
968 div = min_t(u32, div, maxdiv);
973 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
974 unsigned long parent_rate,
977 const struct bcm2835_clock_data *data = clock->data;
980 if (data->int_bits == 0 && data->frac_bits == 0)
984 * The divisor is a 12.12 fixed point field, but only some of
985 * the bits are populated in any given clock.
987 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
988 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
993 temp = (u64)parent_rate << data->frac_bits;
1000 static unsigned long bcm2835_round_rate(unsigned long rate)
1002 unsigned long scaler;
1003 unsigned long limit;
1005 limit = rate / 100000;
1008 while (scaler < limit)
1012 * If increasing a clock by less than 0.1% changes it
1013 * from ..999.. to ..000.., round up.
1015 if ((rate + scaler - 1) / scaler % 1000 == 0)
1016 rate = roundup(rate, scaler);
1021 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1022 unsigned long parent_rate)
1024 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1025 struct bcm2835_cprman *cprman = clock->cprman;
1026 const struct bcm2835_clock_data *data = clock->data;
1030 if (data->int_bits == 0 && data->frac_bits == 0)
1033 div = cprman_read(cprman, data->div_reg);
1035 rate = bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1038 rate = bcm2835_round_rate(rate);
1043 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1045 struct bcm2835_cprman *cprman = clock->cprman;
1046 const struct bcm2835_clock_data *data = clock->data;
1047 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1049 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1050 if (ktime_after(ktime_get(), timeout)) {
1051 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1052 clk_hw_get_name(&clock->hw));
1059 static void bcm2835_clock_off(struct clk_hw *hw)
1061 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1062 struct bcm2835_cprman *cprman = clock->cprman;
1063 const struct bcm2835_clock_data *data = clock->data;
1065 spin_lock(&cprman->regs_lock);
1066 cprman_write(cprman, data->ctl_reg,
1067 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1068 spin_unlock(&cprman->regs_lock);
1070 /* BUSY will remain high until the divider completes its cycle. */
1071 bcm2835_clock_wait_busy(clock);
1074 static int bcm2835_clock_on(struct clk_hw *hw)
1076 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1077 struct bcm2835_cprman *cprman = clock->cprman;
1078 const struct bcm2835_clock_data *data = clock->data;
1080 spin_lock(&cprman->regs_lock);
1081 cprman_write(cprman, data->ctl_reg,
1082 cprman_read(cprman, data->ctl_reg) |
1085 spin_unlock(&cprman->regs_lock);
1087 /* Debug code to measure the clock once it's turned on to see
1088 * if it's ticking at the rate we expect.
1090 if (data->tcnt_mux && false) {
1091 dev_info(cprman->dev,
1092 "clk %s: rate %ld, measure %ld\n",
1094 clk_hw_get_rate(hw),
1095 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1101 static int bcm2835_clock_set_rate(struct clk_hw *hw,
1102 unsigned long rate, unsigned long parent_rate)
1104 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1105 struct bcm2835_cprman *cprman = clock->cprman;
1106 const struct bcm2835_clock_data *data = clock->data;
1107 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
1110 spin_lock(&cprman->regs_lock);
1113 * Setting up frac support
1115 * In principle it is recommended to stop/start the clock first,
1116 * but as we set CLK_SET_RATE_GATE during registration of the
1117 * clock this requirement should be take care of by the
1120 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1121 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1122 cprman_write(cprman, data->ctl_reg, ctl);
1124 cprman_write(cprman, data->div_reg, div);
1126 spin_unlock(&cprman->regs_lock);
1132 bcm2835_clk_is_pllc(struct clk_hw *hw)
1137 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1140 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1144 unsigned long *prate,
1145 unsigned long *avgrate)
1147 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1148 struct bcm2835_cprman *cprman = clock->cprman;
1149 const struct bcm2835_clock_data *data = clock->data;
1150 unsigned long best_rate = 0;
1151 u32 curdiv, mindiv, maxdiv;
1152 struct clk_hw *parent;
1154 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1156 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1157 *prate = clk_hw_get_rate(parent);
1158 *div = bcm2835_clock_choose_div(hw, rate, *prate);
1160 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1162 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1163 unsigned long high, low;
1164 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1166 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1168 int_div += CM_DIV_FRAC_MASK + 1;
1169 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1173 * Return a value which is the maximum deviation
1174 * below the ideal rate, for use as a metric.
1176 return *avgrate - max(*avgrate - low, high - *avgrate);
1181 if (data->frac_bits)
1182 dev_warn(cprman->dev,
1183 "frac bits are not used when propagating rate change");
1185 /* clamp to min divider of 2 if we're dealing with a mash clock */
1186 mindiv = data->is_mash_clock ? 2 : 1;
1187 maxdiv = BIT(data->int_bits) - 1;
1189 /* TODO: Be smart, and only test a subset of the available divisors. */
1190 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1191 unsigned long tmp_rate;
1193 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1195 if (curdiv == mindiv ||
1196 (tmp_rate > best_rate && tmp_rate <= rate))
1197 best_rate = tmp_rate;
1199 if (best_rate == rate)
1203 *div = curdiv << CM_DIV_FRAC_BITS;
1204 *prate = curdiv * best_rate;
1205 *avgrate = best_rate;
1210 static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1211 struct clk_rate_request *req)
1213 struct clk_hw *parent, *best_parent = NULL;
1214 bool current_parent_is_pllc;
1215 unsigned long rate, best_rate = 0;
1216 unsigned long prate, best_prate = 0;
1217 unsigned long avgrate, best_avgrate = 0;
1221 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1224 * Select parent clock that results in the closest but lower rate
1226 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1227 parent = clk_hw_get_parent_by_index(hw, i);
1232 * Don't choose a PLLC-derived clock as our parent
1233 * unless it had been manually set that way. PLLC's
1234 * frequency gets adjusted by the firmware due to
1235 * over-temp or under-voltage conditions, without
1236 * prior notification to our clock consumer.
1238 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1241 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1244 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1245 best_parent = parent;
1248 best_avgrate = avgrate;
1255 req->best_parent_hw = best_parent;
1256 req->best_parent_rate = best_prate;
1258 req->rate = best_avgrate;
1263 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1265 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1266 struct bcm2835_cprman *cprman = clock->cprman;
1267 const struct bcm2835_clock_data *data = clock->data;
1268 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1270 cprman_write(cprman, data->ctl_reg, src);
1274 static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1276 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1277 struct bcm2835_cprman *cprman = clock->cprman;
1278 const struct bcm2835_clock_data *data = clock->data;
1279 u32 src = cprman_read(cprman, data->ctl_reg);
1281 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1284 static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1295 static void bcm2835_clock_debug_init(struct clk_hw *hw,
1296 struct dentry *dentry)
1298 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1299 struct bcm2835_cprman *cprman = clock->cprman;
1300 const struct bcm2835_clock_data *data = clock->data;
1302 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1303 bcm2835_debugfs_clock_reg32,
1304 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1308 static const struct clk_ops bcm2835_clock_clk_ops = {
1309 .is_prepared = bcm2835_clock_is_on,
1310 .prepare = bcm2835_clock_on,
1311 .unprepare = bcm2835_clock_off,
1312 .recalc_rate = bcm2835_clock_get_rate,
1313 .set_rate = bcm2835_clock_set_rate,
1314 .determine_rate = bcm2835_clock_determine_rate,
1315 .set_parent = bcm2835_clock_set_parent,
1316 .get_parent = bcm2835_clock_get_parent,
1317 .debug_init = bcm2835_clock_debug_init,
1320 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1326 * The VPU clock can never be disabled (it doesn't have an ENABLE
1327 * bit), so it gets its own set of clock ops.
1329 static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1330 .is_prepared = bcm2835_vpu_clock_is_on,
1331 .recalc_rate = bcm2835_clock_get_rate,
1332 .set_rate = bcm2835_clock_set_rate,
1333 .determine_rate = bcm2835_clock_determine_rate,
1334 .set_parent = bcm2835_clock_set_parent,
1335 .get_parent = bcm2835_clock_get_parent,
1336 .debug_init = bcm2835_clock_debug_init,
1339 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1342 const struct bcm2835_pll_data *pll_data = data;
1343 struct bcm2835_pll *pll;
1344 struct clk_init_data init;
1347 memset(&init, 0, sizeof(init));
1349 /* All of the PLLs derive from the external oscillator. */
1350 init.parent_names = &cprman->real_parent_names[0];
1351 init.num_parents = 1;
1352 init.name = pll_data->name;
1353 init.ops = &bcm2835_pll_clk_ops;
1354 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1356 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1360 pll->cprman = cprman;
1361 pll->data = pll_data;
1362 pll->hw.init = &init;
1364 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1372 static struct clk_hw *
1373 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1376 const struct bcm2835_pll_divider_data *divider_data = data;
1377 struct bcm2835_pll_divider *divider;
1378 struct clk_init_data init;
1379 const char *divider_name;
1382 if (divider_data->fixed_divider != 1) {
1383 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1384 "%s_prediv", divider_data->name);
1388 divider_name = divider_data->name;
1391 memset(&init, 0, sizeof(init));
1393 init.parent_names = ÷r_data->source_pll;
1394 init.num_parents = 1;
1395 init.name = divider_name;
1396 init.ops = &bcm2835_pll_divider_clk_ops;
1397 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1399 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1403 divider->div.reg = cprman->regs + divider_data->a2w_reg;
1404 divider->div.shift = A2W_PLL_DIV_SHIFT;
1405 divider->div.width = A2W_PLL_DIV_BITS;
1406 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1407 divider->div.lock = &cprman->regs_lock;
1408 divider->div.hw.init = &init;
1409 divider->div.table = NULL;
1411 divider->cprman = cprman;
1412 divider->data = divider_data;
1414 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1416 return ERR_PTR(ret);
1419 * PLLH's channels have a fixed divide by 10 afterwards, which
1420 * is what our consumers are actually using.
1422 if (divider_data->fixed_divider != 1) {
1423 return clk_hw_register_fixed_factor(cprman->dev,
1426 CLK_SET_RATE_PARENT,
1428 divider_data->fixed_divider);
1431 return ÷r->div.hw;
1434 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1437 const struct bcm2835_clock_data *clock_data = data;
1438 struct bcm2835_clock *clock;
1439 struct clk_init_data init;
1440 const char *parents[1 << CM_SRC_BITS];
1445 * Replace our strings referencing parent clocks with the
1446 * actual clock-output-name of the parent.
1448 for (i = 0; i < clock_data->num_mux_parents; i++) {
1449 parents[i] = clock_data->parents[i];
1451 ret = match_string(cprman_parent_names,
1452 ARRAY_SIZE(cprman_parent_names),
1455 parents[i] = cprman->real_parent_names[ret];
1458 memset(&init, 0, sizeof(init));
1459 init.parent_names = parents;
1460 init.num_parents = clock_data->num_mux_parents;
1461 init.name = clock_data->name;
1462 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1465 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1466 * rate changes on at least of the parents.
1468 if (clock_data->set_rate_parent)
1469 init.flags |= CLK_SET_RATE_PARENT;
1471 if (clock_data->is_vpu_clock) {
1472 init.ops = &bcm2835_vpu_clock_clk_ops;
1474 init.ops = &bcm2835_clock_clk_ops;
1475 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1477 /* If the clock wasn't actually enabled at boot, it's not
1480 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1481 init.flags &= ~CLK_IS_CRITICAL;
1484 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1488 clock->cprman = cprman;
1489 clock->data = clock_data;
1490 clock->hw.init = &init;
1492 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1494 return ERR_PTR(ret);
1498 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1501 const struct bcm2835_gate_data *gate_data = data;
1503 return clk_hw_register_gate(cprman->dev, gate_data->name,
1505 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1506 cprman->regs + gate_data->ctl_reg,
1507 CM_GATE_BIT, 0, &cprman->regs_lock);
1510 struct bcm2835_clk_desc {
1511 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1513 unsigned int supported;
1517 /* assignment helper macros for different clock types */
1518 #define _REGISTER(f, s, ...) { .clk_register = f, \
1520 .data = __VA_ARGS__ }
1521 #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1523 &(struct bcm2835_pll_data) \
1525 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1527 &(struct bcm2835_pll_divider_data) \
1529 #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1531 &(struct bcm2835_clock_data) \
1533 #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1535 &(struct bcm2835_gate_data) \
1538 /* parent mux arrays plus helper macros */
1540 /* main oscillator parent mux */
1541 static const char *const bcm2835_clock_osc_parents[] = {
1548 #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1550 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1551 .parents = bcm2835_clock_osc_parents, \
1554 /* main peripherial parent mux */
1555 static const char *const bcm2835_clock_per_parents[] = {
1566 #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1568 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1569 .parents = bcm2835_clock_per_parents, \
1573 * Restrict clock sources for the PCM peripheral to the oscillator and
1574 * PLLD_PER because other source may have varying rates or be switched
1577 * Prevent other sources from being selected by replacing their names in
1578 * the list of potential parents with dummy entries (entry index is
1581 static const char *const bcm2835_pcm_per_parents[] = {
1592 #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1594 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1595 .parents = bcm2835_pcm_per_parents, \
1598 /* main vpu parent mux */
1599 static const char *const bcm2835_clock_vpu_parents[] = {
1612 #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1614 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1615 .parents = bcm2835_clock_vpu_parents, \
1619 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1620 * analog PHY. The _inv variants are generated internally to cprman,
1621 * but we don't use them so they aren't hooked up.
1623 static const char *const bcm2835_clock_dsi0_parents[] = {
1636 static const char *const bcm2835_clock_dsi1_parents[] = {
1649 #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1651 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1652 .parents = bcm2835_clock_dsi0_parents, \
1655 #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1657 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1658 .parents = bcm2835_clock_dsi1_parents, \
1662 * the real definition of all the pll, pll_dividers and clocks
1663 * these make use of the above REGISTER_* macros
1665 static const struct bcm2835_clk_desc clk_desc_array[] = {
1666 /* the PLL + PLL dividers */
1669 * PLLA is the auxiliary PLL, used to drive the CCP2
1670 * (Compact Camera Port 2) transmitter clock.
1672 * It is in the PX LDO power domain, which is on when the
1673 * AUDIO domain is on.
1675 [BCM2835_PLLA] = REGISTER_PLL(
1678 .cm_ctrl_reg = CM_PLLA,
1679 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1680 .frac_reg = A2W_PLLA_FRAC,
1681 .ana_reg_base = A2W_PLLA_ANA0,
1682 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1683 .lock_mask = CM_LOCK_FLOCKA,
1685 .ana = &bcm2835_ana_default,
1687 .min_rate = 600000000u,
1688 .max_rate = 2400000000u,
1689 .max_fb_rate = BCM2835_MAX_FB_RATE),
1690 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1692 .name = "plla_core",
1693 .source_pll = "plla",
1695 .a2w_reg = A2W_PLLA_CORE,
1696 .load_mask = CM_PLLA_LOADCORE,
1697 .hold_mask = CM_PLLA_HOLDCORE,
1699 .flags = CLK_SET_RATE_PARENT),
1700 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1703 .source_pll = "plla",
1705 .a2w_reg = A2W_PLLA_PER,
1706 .load_mask = CM_PLLA_LOADPER,
1707 .hold_mask = CM_PLLA_HOLDPER,
1709 .flags = CLK_SET_RATE_PARENT),
1710 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1712 .name = "plla_dsi0",
1713 .source_pll = "plla",
1715 .a2w_reg = A2W_PLLA_DSI0,
1716 .load_mask = CM_PLLA_LOADDSI0,
1717 .hold_mask = CM_PLLA_HOLDDSI0,
1718 .fixed_divider = 1),
1719 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1721 .name = "plla_ccp2",
1722 .source_pll = "plla",
1724 .a2w_reg = A2W_PLLA_CCP2,
1725 .load_mask = CM_PLLA_LOADCCP2,
1726 .hold_mask = CM_PLLA_HOLDCCP2,
1728 .flags = CLK_SET_RATE_PARENT),
1730 /* PLLB is used for the ARM's clock. */
1731 [BCM2835_PLLB] = REGISTER_PLL(
1734 .cm_ctrl_reg = CM_PLLB,
1735 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1736 .frac_reg = A2W_PLLB_FRAC,
1737 .ana_reg_base = A2W_PLLB_ANA0,
1738 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1739 .lock_mask = CM_LOCK_FLOCKB,
1741 .ana = &bcm2835_ana_default,
1743 .min_rate = 600000000u,
1744 .max_rate = 3000000000u,
1745 .max_fb_rate = BCM2835_MAX_FB_RATE,
1746 .flags = CLK_GET_RATE_NOCACHE),
1747 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1750 .source_pll = "pllb",
1752 .a2w_reg = A2W_PLLB_ARM,
1753 .load_mask = CM_PLLB_LOADARM,
1754 .hold_mask = CM_PLLB_HOLDARM,
1756 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
1759 * PLLC is the core PLL, used to drive the core VPU clock.
1761 * It is in the PX LDO power domain, which is on when the
1762 * AUDIO domain is on.
1764 [BCM2835_PLLC] = REGISTER_PLL(
1767 .cm_ctrl_reg = CM_PLLC,
1768 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1769 .frac_reg = A2W_PLLC_FRAC,
1770 .ana_reg_base = A2W_PLLC_ANA0,
1771 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1772 .lock_mask = CM_LOCK_FLOCKC,
1774 .ana = &bcm2835_ana_default,
1776 .min_rate = 600000000u,
1777 .max_rate = 3000000000u,
1778 .max_fb_rate = BCM2835_MAX_FB_RATE),
1779 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1781 .name = "pllc_core0",
1782 .source_pll = "pllc",
1784 .a2w_reg = A2W_PLLC_CORE0,
1785 .load_mask = CM_PLLC_LOADCORE0,
1786 .hold_mask = CM_PLLC_HOLDCORE0,
1788 .flags = CLK_SET_RATE_PARENT),
1789 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1791 .name = "pllc_core1",
1792 .source_pll = "pllc",
1794 .a2w_reg = A2W_PLLC_CORE1,
1795 .load_mask = CM_PLLC_LOADCORE1,
1796 .hold_mask = CM_PLLC_HOLDCORE1,
1798 .flags = CLK_SET_RATE_PARENT),
1799 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1801 .name = "pllc_core2",
1802 .source_pll = "pllc",
1804 .a2w_reg = A2W_PLLC_CORE2,
1805 .load_mask = CM_PLLC_LOADCORE2,
1806 .hold_mask = CM_PLLC_HOLDCORE2,
1808 .flags = CLK_SET_RATE_PARENT),
1809 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1812 .source_pll = "pllc",
1814 .a2w_reg = A2W_PLLC_PER,
1815 .load_mask = CM_PLLC_LOADPER,
1816 .hold_mask = CM_PLLC_HOLDPER,
1818 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1821 * PLLD is the display PLL, used to drive DSI display panels.
1823 * It is in the PX LDO power domain, which is on when the
1824 * AUDIO domain is on.
1826 [BCM2835_PLLD] = REGISTER_PLL(
1829 .cm_ctrl_reg = CM_PLLD,
1830 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1831 .frac_reg = A2W_PLLD_FRAC,
1832 .ana_reg_base = A2W_PLLD_ANA0,
1833 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1834 .lock_mask = CM_LOCK_FLOCKD,
1836 .ana = &bcm2835_ana_default,
1838 .min_rate = 600000000u,
1839 .max_rate = 2400000000u,
1840 .max_fb_rate = BCM2835_MAX_FB_RATE),
1841 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1843 .name = "plld_core",
1844 .source_pll = "plld",
1846 .a2w_reg = A2W_PLLD_CORE,
1847 .load_mask = CM_PLLD_LOADCORE,
1848 .hold_mask = CM_PLLD_HOLDCORE,
1850 .flags = CLK_SET_RATE_PARENT),
1852 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1853 * Otherwise this could cause firmware lookups. That's why we mark
1856 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1859 .source_pll = "plld",
1861 .a2w_reg = A2W_PLLD_PER,
1862 .load_mask = CM_PLLD_LOADPER,
1863 .hold_mask = CM_PLLD_HOLDPER,
1865 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1866 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1868 .name = "plld_dsi0",
1869 .source_pll = "plld",
1871 .a2w_reg = A2W_PLLD_DSI0,
1872 .load_mask = CM_PLLD_LOADDSI0,
1873 .hold_mask = CM_PLLD_HOLDDSI0,
1874 .fixed_divider = 1),
1875 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1877 .name = "plld_dsi1",
1878 .source_pll = "plld",
1880 .a2w_reg = A2W_PLLD_DSI1,
1881 .load_mask = CM_PLLD_LOADDSI1,
1882 .hold_mask = CM_PLLD_HOLDDSI1,
1883 .fixed_divider = 1),
1886 * PLLH is used to supply the pixel clock or the AUX clock for the
1889 * It is in the HDMI power domain.
1891 [BCM2835_PLLH] = REGISTER_PLL(
1894 .cm_ctrl_reg = CM_PLLH,
1895 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1896 .frac_reg = A2W_PLLH_FRAC,
1897 .ana_reg_base = A2W_PLLH_ANA0,
1898 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1899 .lock_mask = CM_LOCK_FLOCKH,
1901 .ana = &bcm2835_ana_pllh,
1903 .min_rate = 600000000u,
1904 .max_rate = 3000000000u,
1905 .max_fb_rate = BCM2835_MAX_FB_RATE),
1906 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1908 .name = "pllh_rcal",
1909 .source_pll = "pllh",
1911 .a2w_reg = A2W_PLLH_RCAL,
1912 .load_mask = CM_PLLH_LOADRCAL,
1914 .fixed_divider = 10,
1915 .flags = CLK_SET_RATE_PARENT),
1916 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1919 .source_pll = "pllh",
1921 .a2w_reg = A2W_PLLH_AUX,
1922 .load_mask = CM_PLLH_LOADAUX,
1925 .flags = CLK_SET_RATE_PARENT),
1926 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1929 .source_pll = "pllh",
1931 .a2w_reg = A2W_PLLH_PIX,
1932 .load_mask = CM_PLLH_LOADPIX,
1934 .fixed_divider = 10,
1935 .flags = CLK_SET_RATE_PARENT),
1939 /* clocks with oscillator parent mux */
1941 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1942 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1945 .ctl_reg = CM_OTPCTL,
1946 .div_reg = CM_OTPDIV,
1951 * Used for a 1Mhz clock for the system clocksource, and also used
1952 * bythe watchdog timer and the camera pulse generator.
1954 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1957 .ctl_reg = CM_TIMERCTL,
1958 .div_reg = CM_TIMERDIV,
1962 * Clock for the temperature sensor.
1963 * Generally run at 2Mhz, max 5Mhz.
1965 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1968 .ctl_reg = CM_TSENSCTL,
1969 .div_reg = CM_TSENSDIV,
1972 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1975 .ctl_reg = CM_TECCTL,
1976 .div_reg = CM_TECDIV,
1980 /* clocks with vpu parent mux */
1981 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1984 .ctl_reg = CM_H264CTL,
1985 .div_reg = CM_H264DIV,
1989 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1992 .ctl_reg = CM_ISPCTL,
1993 .div_reg = CM_ISPDIV,
1999 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
2000 * in the SDRAM controller can't be used.
2002 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
2005 .ctl_reg = CM_SDCCTL,
2006 .div_reg = CM_SDCDIV,
2010 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
2013 .ctl_reg = CM_V3DCTL,
2014 .div_reg = CM_V3DDIV,
2019 * VPU clock. This doesn't have an enable bit, since it drives
2020 * the bus for everything else, and is special so it doesn't need
2021 * to be gated for rate changes. It is also known as "clk_audio"
2022 * in various hardware documentation.
2024 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
2027 .ctl_reg = CM_VPUCTL,
2028 .div_reg = CM_VPUDIV,
2031 .flags = CLK_IS_CRITICAL,
2032 .is_vpu_clock = true,
2035 /* clocks with per parent mux */
2036 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
2039 .ctl_reg = CM_AVEOCTL,
2040 .div_reg = CM_AVEODIV,
2044 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
2047 .ctl_reg = CM_CAM0CTL,
2048 .div_reg = CM_CAM0DIV,
2052 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
2055 .ctl_reg = CM_CAM1CTL,
2056 .div_reg = CM_CAM1DIV,
2060 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
2063 .ctl_reg = CM_DFTCTL,
2064 .div_reg = CM_DFTDIV,
2067 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
2070 .ctl_reg = CM_DPICTL,
2071 .div_reg = CM_DPIDIV,
2076 /* Arasan EMMC clock */
2077 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2080 .ctl_reg = CM_EMMCCTL,
2081 .div_reg = CM_EMMCDIV,
2086 /* EMMC2 clock (only available for BCM2711) */
2087 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2090 .ctl_reg = CM_EMMC2CTL,
2091 .div_reg = CM_EMMC2DIV,
2096 /* General purpose (GPIO) clocks */
2097 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2100 .ctl_reg = CM_GP0CTL,
2101 .div_reg = CM_GP0DIV,
2104 .is_mash_clock = true,
2106 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2109 .ctl_reg = CM_GP1CTL,
2110 .div_reg = CM_GP1DIV,
2113 .flags = CLK_IS_CRITICAL,
2114 .is_mash_clock = true,
2116 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2119 .ctl_reg = CM_GP2CTL,
2120 .div_reg = CM_GP2DIV,
2123 .flags = CLK_IS_CRITICAL),
2125 /* HDMI state machine */
2126 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2129 .ctl_reg = CM_HSMCTL,
2130 .div_reg = CM_HSMDIV,
2134 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2137 .ctl_reg = CM_PCMCTL,
2138 .div_reg = CM_PCMDIV,
2141 .is_mash_clock = true,
2144 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2147 .ctl_reg = CM_PWMCTL,
2148 .div_reg = CM_PWMDIV,
2151 .is_mash_clock = true,
2153 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2156 .ctl_reg = CM_SLIMCTL,
2157 .div_reg = CM_SLIMDIV,
2160 .is_mash_clock = true,
2162 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2165 .ctl_reg = CM_SMICTL,
2166 .div_reg = CM_SMIDIV,
2170 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2173 .ctl_reg = CM_UARTCTL,
2174 .div_reg = CM_UARTDIV,
2180 /* TV encoder clock. Only operating frequency is 108Mhz. */
2181 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2184 .ctl_reg = CM_VECCTL,
2185 .div_reg = CM_VECDIV,
2189 * Allow rate change propagation only on PLLH_AUX which is
2190 * assigned index 7 in the parent array.
2192 .set_rate_parent = BIT(7),
2196 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2199 .ctl_reg = CM_DSI0ECTL,
2200 .div_reg = CM_DSI0EDIV,
2204 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2207 .ctl_reg = CM_DSI1ECTL,
2208 .div_reg = CM_DSI1EDIV,
2212 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2215 .ctl_reg = CM_DSI0PCTL,
2216 .div_reg = CM_DSI0PDIV,
2220 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2223 .ctl_reg = CM_DSI1PCTL,
2224 .div_reg = CM_DSI1PDIV,
2232 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2233 * you have the debug bit set in the power manager, which we
2234 * don't bother exposing) are individual gates off of the
2235 * non-stop vpu clock.
2237 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2239 .name = "peri_image",
2241 .ctl_reg = CM_PERIICTL),
2245 * Permanently take a reference on the parent of the SDRAM clock.
2247 * While the SDRAM is being driven by its dedicated PLL most of the
2248 * time, there is a little loop running in the firmware that
2249 * periodically switches the SDRAM to using our CM clock to do PVT
2250 * recalibration, with the assumption that the previously configured
2251 * SDRAM parent is still enabled and running.
2253 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2255 struct clk *parent = clk_get_parent(sdc);
2258 return PTR_ERR(parent);
2260 return clk_prepare_enable(parent);
2263 static int bcm2835_clk_probe(struct platform_device *pdev)
2265 struct device *dev = &pdev->dev;
2266 struct clk_hw **hws;
2267 struct bcm2835_cprman *cprman;
2268 const struct bcm2835_clk_desc *desc;
2269 const size_t asize = ARRAY_SIZE(clk_desc_array);
2270 const struct cprman_plat_data *pdata;
2274 pdata = of_device_get_match_data(&pdev->dev);
2278 cprman = devm_kzalloc(dev,
2279 struct_size(cprman, onecell.hws, asize),
2284 spin_lock_init(&cprman->regs_lock);
2286 cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2287 if (IS_ERR(cprman->regs))
2288 return PTR_ERR(cprman->regs);
2290 memcpy(cprman->real_parent_names, cprman_parent_names,
2291 sizeof(cprman_parent_names));
2292 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2293 ARRAY_SIZE(cprman_parent_names));
2296 * Make sure the external oscillator has been registered.
2298 * The other (DSI) clocks are not present on older device
2299 * trees, which we still need to support for backwards
2302 if (!cprman->real_parent_names[0])
2305 platform_set_drvdata(pdev, cprman);
2307 cprman->onecell.num = asize;
2308 cprman->soc = pdata->soc;
2309 hws = cprman->onecell.hws;
2311 for (i = 0; i < asize; i++) {
2312 desc = &clk_desc_array[i];
2313 if (desc->clk_register && desc->data &&
2314 (desc->supported & pdata->soc)) {
2315 hws[i] = desc->clk_register(cprman, desc->data);
2319 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2323 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2327 static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2331 static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2335 static const struct of_device_id bcm2835_clk_of_match[] = {
2336 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2337 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2340 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2342 static struct platform_driver bcm2835_clk_driver = {
2344 .name = "bcm2835-clk",
2345 .of_match_table = bcm2835_clk_of_match,
2347 .probe = bcm2835_clk_probe,
2350 builtin_platform_driver(bcm2835_clk_driver);
2352 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2353 MODULE_DESCRIPTION("BCM2835 clock driver");
2354 MODULE_LICENSE("GPL");