drivers/clk/at91/sam9x60.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
   4  *
   5  * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
   6  *
   7  * Based on sam9x60.c on Linux.
   8  */
   9
  10 #include <common.h>
  11 #include <clk-uclass.h>
  12 #include <dm.h>
  13 #include <dt-bindings/clk/at91.h>
  14 #include <linux/clk-provider.h>
  15
  16 #include "pmc.h"
  17
  18 /**
  19  * Clock identifiers to be used in conjunction with macros like
  20  * AT91_TO_CLK_ID()
  21  *
  22  * @ID_MD_SLCK:                 TD slow clock identifier
  23  * @ID_TD_SLCK:                 MD slow clock identifier
  24  * @ID_MAIN_XTAL:               Main Xtal clock identifier
  25  * @ID_MAIN_RC:                 Main RC clock identifier
  26  * @ID_MAIN_RC_OSC:             Main RC Oscillator clock identifier
  27  * @ID_MAIN_OSC:                Main Oscillator clock identifier
  28  * @ID_MAINCK:                  MAINCK clock identifier
  29  * @ID_PLL_U_FRAC:              UPLL fractional clock identifier
  30  * @ID_PLL_U_DIV:               UPLL divider clock identifier
  31  * @ID_PLL_A_FRAC:              APLL fractional clock identifier
  32  * @ID_PLL_A_DIV:               APLL divider clock identifier
  33
  34  * @ID_MCK_DIV:                 MCK DIV clock identifier
  35
  36  * @ID_UTMI:                    UTMI clock identifier
  37
  38  * @ID_PROG0:                   Programmable 0 clock identifier
  39  * @ID_PROG1:                   Programmable 1 clock identifier
  40
  41  * @ID_PCK0:                    PCK0 system clock identifier
  42  * @ID_PCK1:                    PCK1 system clock identifier
  43  * @ID_DDR:                     DDR system clock identifier
  44  * @ID_QSPI:                    QSPI system clock identifier
  45  *
  46  * @ID_MCK_PRES:                MCK PRES clock identifier
  47  *
  48  * Note: if changing the values of this enums please sync them with
  49  *       device tree
  50  */
  51 enum pmc_clk_ids {
  52         ID_MD_SLCK              = 0,
  53         ID_TD_SLCK              = 1,
  54         ID_MAIN_XTAL            = 2,
  55         ID_MAIN_RC              = 3,
  56         ID_MAIN_RC_OSC          = 4,
  57         ID_MAIN_OSC             = 5,
  58         ID_MAINCK               = 6,
  59
  60         ID_PLL_U_FRAC           = 7,
  61         ID_PLL_U_DIV            = 8,
  62         ID_PLL_A_FRAC           = 9,
  63         ID_PLL_A_DIV            = 10,
  64
  65         ID_MCK_DIV              = 11,
  66
  67         ID_UTMI                 = 12,
  68
  69         ID_PROG0                = 13,
  70         ID_PROG1                = 14,
  71
  72         ID_PCK0                 = 15,
  73         ID_PCK1                 = 16,
  74
  75         ID_DDR                  = 17,
  76         ID_QSPI                 = 18,
  77
  78         ID_MCK_PRES             = 19,
  79
  80         ID_MAX,
  81 };
  82
  83 /**
  84  * PLL type identifiers
  85  * @PLL_TYPE_FRAC:      fractional PLL identifier
  86  * @PLL_TYPE_DIV:       divider PLL identifier
  87  */
  88 enum pll_type {
  89         PLL_TYPE_FRAC,
  90         PLL_TYPE_DIV,
  91 };
  92
  93 /* Clock names used as parents for multiple clocks. */
  94 static const char *clk_names[] = {
  95         [ID_MAIN_RC_OSC]        = "main_rc_osc",
  96         [ID_MAIN_OSC]           = "main_osc",
  97         [ID_MAINCK]             = "mainck",
  98         [ID_PLL_U_DIV]          = "upll_divpmcck",
  99         [ID_PLL_A_DIV]          = "plla_divpmcck",
 100         [ID_MCK_PRES]           = "mck_pres",
 101         [ID_MCK_DIV]            = "mck_div",
 102 };
 103
 104 /* Fractional PLL output range. */
 105 static const struct clk_range plla_outputs[] = {
 106         { .min = 2343750, .max = 1200000000 },
 107 };
 108
 109 static const struct clk_range upll_outputs[] = {
 110         { .min = 300000000, .max = 500000000 },
 111 };
 112
 113 /* PLL characteristics. */
 114 static const struct clk_pll_characteristics apll_characteristics = {
 115         .input = { .min = 12000000, .max = 48000000 },
 116         .num_output = ARRAY_SIZE(plla_outputs),
 117         .output = plla_outputs,
 118 };
 119
 120 static const struct clk_pll_characteristics upll_characteristics = {
 121         .input = { .min = 12000000, .max = 48000000 },
 122         .num_output = ARRAY_SIZE(upll_outputs),
 123         .output = upll_outputs,
 124         .upll = true,
 125 };
 126
 127 /* Layout for fractional PLLs. */
 128 static const struct clk_pll_layout pll_layout_frac = {
 129         .mul_mask = GENMASK(31, 24),
 130         .frac_mask = GENMASK(21, 0),
 131         .mul_shift = 24,
 132         .frac_shift = 0,
 133 };
 134
 135 /* Layout for DIV PLLs. */
 136 static const struct clk_pll_layout pll_layout_div = {
 137         .div_mask = GENMASK(7, 0),
 138         .endiv_mask = BIT(29),
 139         .div_shift = 0,
 140         .endiv_shift = 29,
 141 };
 142
 143 /* MCK characteristics. */
 144 static const struct clk_master_characteristics mck_characteristics = {
 145         .output = { .min = 140000000, .max = 200000000 },
 146         .divisors = { 1, 2, 4, 3 },
 147         .have_div3_pres = 1,
 148 };
 149
 150 /* MCK layout. */
 151 static const struct clk_master_layout mck_layout = {
 152         .mask = 0x373,
 153         .pres_shift = 4,
 154         .offset = 0x28,
 155 };
 156
 157 /* Programmable clock layout. */
 158 static const struct clk_programmable_layout programmable_layout = {
 159         .pres_mask = 0xff,
 160         .pres_shift = 8,
 161         .css_mask = 0x1f,
 162         .have_slck_mck = 0,
 163         .is_pres_direct = 1,
 164 };
 165
 166 /* Peripheral clock layout. */
 167 static const struct clk_pcr_layout pcr_layout = {
 168         .offset = 0x88,
 169         .cmd = BIT(31),
 170         .gckcss_mask = GENMASK(12, 8),
 171         .pid_mask = GENMASK(6, 0),
 172 };
 173
 174 /**
 175  * PLL clocks description
 176  * @n:          clock name
 177  * @p:          clock parent
 178  * @l:          clock layout
 179  * @t:          clock type
 180  * @f:          true if clock is fixed and not changeable by driver
 181  * @id:         clock id corresponding to PLL driver
 182  * @cid:        clock id corresponding to clock subsystem
 183  */
 184 static const struct {
 185         const char *n;
 186         const char *p;
 187         const struct clk_pll_layout *l;
 188         const struct clk_pll_characteristics *c;
 189         u8 t;
 190         u8 f;
 191         u8 id;
 192         u8 cid;
 193 } sam9x60_plls[] = {
 194         {
 195                 .n = "plla_fracck",
 196                 .p = "mainck",
 197                 .l = &pll_layout_frac,
 198                 .c = &apll_characteristics,
 199                 .t = PLL_TYPE_FRAC,
 200                 .f = 1,
 201                 .id = 0,
 202                 .cid = ID_PLL_A_FRAC,
 203         },
 204
 205         {
 206                 .n = "plla_divpmcck",
 207                 .p = "plla_fracck",
 208                 .l = &pll_layout_div,
 209                 .c = &apll_characteristics,
 210                 .t = PLL_TYPE_DIV,
 211                 .f = 1,
 212                 .id = 0,
 213                 .cid = ID_PLL_A_DIV,
 214         },
 215
 216         {
 217                 .n = "upll_fracck",
 218                 .p = "main_osc",
 219                 .l = &pll_layout_frac,
 220                 .c = &upll_characteristics,
 221                 .t = PLL_TYPE_FRAC,
 222                 .f = 1,
 223                 .id = 1,
 224                 .cid = ID_PLL_U_FRAC,
 225         },
 226
 227         {
 228                 .n = "upll_divpmcck",
 229                 .p = "upll_fracck",
 230                 .l = &pll_layout_div,
 231                 .c = &upll_characteristics,
 232                 .t = PLL_TYPE_DIV,
 233                 .f = 1,
 234                 .id = 1,
 235                 .cid = ID_PLL_U_DIV,
 236         },
 237 };
 238
 239 /**
 240  * Programmable clock description
 241  * @n:                  clock name
 242  * @cid:                clock id corresponding to clock subsystem
 243  */
 244 static const struct {
 245         const char *n;
 246         u8 cid;
 247 } sam9x60_prog[] = {
 248         { .n = "prog0", .cid = ID_PROG0, },
 249         { .n = "prog1", .cid = ID_PROG1, },
 250 };
 251
 252 /* Mux table for programmable clocks. */
 253 static u32 sam9x60_prog_mux_table[] = { 0, 1, 2, 3, 4, 5, };
 254
 255 /**
 256  * System clock description
 257  * @n:                  clock name
 258  * @p:                  parent clock name
 259  * @id:                 clock id corresponding to system clock driver
 260  * @cid:                clock id corresponding to clock subsystem
 261  */
 262 static const struct {
 263         const char *n;
 264         const char *p;
 265         u8 id;
 266         u8 cid;
 267 } sam9x60_systemck[] = {
 268         { .n = "ddrck",         .p = "mck_pres", .id = 2, .cid = ID_DDR, },
 269         { .n = "pck0",          .p = "prog0",    .id = 8, .cid = ID_PCK0, },
 270         { .n = "pck1",          .p = "prog1",    .id = 9, .cid = ID_PCK1, },
 271         { .n = "qspick",        .p = "mck_pres", .id = 19, .cid = ID_QSPI, },
 272 };
 273
 274 /**
 275  * Peripheral clock description
 276  * @n:          clock name
 277  * @id:         clock id
 278  */
 279 static const struct {
 280         const char *n;
 281         u8 id;
 282 } sam9x60_periphck[] = {
 283         { .n = "pioA_clk",   .id = 2, },
 284         { .n = "pioB_clk",   .id = 3, },
 285         { .n = "pioC_clk",   .id = 4, },
 286         { .n = "flex0_clk",  .id = 5, },
 287         { .n = "flex1_clk",  .id = 6, },
 288         { .n = "flex2_clk",  .id = 7, },
 289         { .n = "flex3_clk",  .id = 8, },
 290         { .n = "flex6_clk",  .id = 9, },
 291         { .n = "flex7_clk",  .id = 10, },
 292         { .n = "flex8_clk",  .id = 11, },
 293         { .n = "sdmmc0_clk", .id = 12, },
 294         { .n = "flex4_clk",  .id = 13, },
 295         { .n = "flex5_clk",  .id = 14, },
 296         { .n = "flex9_clk",  .id = 15, },
 297         { .n = "flex10_clk", .id = 16, },
 298         { .n = "tcb0_clk",   .id = 17, },
 299         { .n = "pwm_clk",    .id = 18, },
 300         { .n = "adc_clk",    .id = 19, },
 301         { .n = "dma0_clk",   .id = 20, },
 302         { .n = "matrix_clk", .id = 21, },
 303         { .n = "uhphs_clk",  .id = 22, },
 304         { .n = "udphs_clk",  .id = 23, },
 305         { .n = "macb0_clk",  .id = 24, },
 306         { .n = "lcd_clk",    .id = 25, },
 307         { .n = "sdmmc1_clk", .id = 26, },
 308         { .n = "macb1_clk",  .id = 27, },
 309         { .n = "ssc_clk",    .id = 28, },
 310         { .n = "can0_clk",   .id = 29, },
 311         { .n = "can1_clk",   .id = 30, },
 312         { .n = "flex11_clk", .id = 32, },
 313         { .n = "flex12_clk", .id = 33, },
 314         { .n = "i2s_clk",    .id = 34, },
 315         { .n = "qspi_clk",   .id = 35, },
 316         { .n = "gfx2d_clk",  .id = 36, },
 317         { .n = "pit64b_clk", .id = 37, },
 318         { .n = "trng_clk",   .id = 38, },
 319         { .n = "aes_clk",    .id = 39, },
 320         { .n = "tdes_clk",   .id = 40, },
 321         { .n = "sha_clk",    .id = 41, },
 322         { .n = "classd_clk", .id = 42, },
 323         { .n = "isi_clk",    .id = 43, },
 324         { .n = "pioD_clk",   .id = 44, },
 325         { .n = "tcb1_clk",   .id = 45, },
 326         { .n = "dbgu_clk",   .id = 47, },
 327         { .n = "mpddr_clk",  .id = 49, },
 328 };
 329
 330 /**
 331  * Generic clock description
 332  * @n:                  clock name
 333  * @ep:                 extra parents parents names
 334  * @ep_mux_table:       extra parents mux table
 335  * @ep_clk_mux_table:   extra parents clock mux table (for CCF)
 336  * @r:                  clock output range
 337  * @ep_count:           extra parents count
 338  * @id:                 clock id
 339  */
 340 static const struct {
 341         const char *n;
 342         struct clk_range r;
 343         u8 id;
 344 } sam9x60_gck[] = {
 345         { .n = "flex0_gclk",  .id = 5, },
 346         { .n = "flex1_gclk",  .id = 6, },
 347         { .n = "flex2_gclk",  .id = 7, },
 348         { .n = "flex3_gclk",  .id = 8, },
 349         { .n = "flex6_gclk",  .id = 9, },
 350         { .n = "flex7_gclk",  .id = 10, },
 351         { .n = "flex8_gclk",  .id = 11, },
 352         { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
 353         { .n = "flex4_gclk",  .id = 13, },
 354         { .n = "flex5_gclk",  .id = 14, },
 355         { .n = "flex9_gclk",  .id = 15, },
 356         { .n = "flex10_gclk", .id = 16, },
 357         { .n = "tcb0_gclk",   .id = 17, },
 358         { .n = "adc_gclk",    .id = 19, },
 359         { .n = "lcd_gclk",    .id = 25, .r = { .min = 0, .max = 140000000 }, },
 360         { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
 361         { .n = "flex11_gclk", .id = 32, },
 362         { .n = "flex12_gclk", .id = 33, },
 363         { .n = "i2s_gclk",    .id = 34, .r = { .min = 0, .max = 105000000 }, },
 364         { .n = "pit64b_gclk", .id = 37, },
 365         { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, },
 366         { .n = "tcb1_gclk",   .id = 45, },
 367         { .n = "dbgu_gclk",   .id = 47, },
 368 };
 369
 370 #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label)    \
 371         do {                                                            \
 372                 int _i;                                                 \
 373                 (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \
 374                 if (!(_dst)) {                                          \
 375                         ret = -ENOMEM;                                  \
 376                         goto _label;                                    \
 377                 }                                                       \
 378                 (_allocs)[(_index)++] = (_dst);                         \
 379                 for (_i = 0; _i < (_num); _i++)                         \
 380                         (_dst)[_i] = (_src)[_i];                        \
 381         } while (0)
 382
 383 static int sam9x60_clk_probe(struct udevice *dev)
 384 {
 385         void __iomem *base = (void *)devfdt_get_addr_ptr(dev);
 386         unsigned int *clkmuxallocs[64], *muxallocs[64];
 387         const char *p[10];
 388         unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
 389         struct clk clk, *c;
 390         int ret, muxallocindex = 0, clkmuxallocindex = 0, i;
 391         static const struct clk_range r = { 0, 0 };
 392
 393         if (!base)
 394                 return -EINVAL;
 395
 396         memset(muxallocs,    0, ARRAY_SIZE(muxallocs));
 397         memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs));
 398
 399         ret = clk_get_by_index(dev, 0, &clk);
 400         if (ret)
 401                 return ret;
 402
 403         ret = clk_get_by_id(clk.id, &c);
 404         if (ret)
 405                 return ret;
 406
 407         clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c),
 408                                         strlen(clk_hw_get_name(c)) + 1,
 409                                         GFP_KERNEL);
 410         if (!clk_names[ID_TD_SLCK])
 411                 return -ENOMEM;
 412
 413         ret = clk_get_by_index(dev, 1, &clk);
 414         if (ret)
 415                 return ret;
 416
 417         ret = clk_get_by_id(clk.id, &c);
 418         if (ret)
 419                 return ret;
 420
 421         clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c),
 422                                         strlen(clk_hw_get_name(c)) + 1,
 423                                         GFP_KERNEL);
 424         if (!clk_names[ID_MD_SLCK])
 425                 return -ENOMEM;
 426
 427         ret = clk_get_by_index(dev, 2, &clk);
 428         if (ret)
 429                 return ret;
 430
 431         clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk),
 432                                           strlen(clk_hw_get_name(&clk)) + 1,
 433                                           GFP_KERNEL);
 434         if (!clk_names[ID_MAIN_XTAL])
 435                 return -ENOMEM;
 436
 437         ret = clk_get_by_index(dev, 3, &clk);
 438         if (ret)
 439                 goto fail;
 440
 441         clk_names[ID_MAIN_RC] = kmemdup(clk_hw_get_name(&clk),
 442                                         strlen(clk_hw_get_name(&clk)) + 1,
 443                                         GFP_KERNEL);
 444         if (ret)
 445                 goto fail;
 446
 447         /* Register main rc oscillator. */
 448         c = at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC],
 449                              clk_names[ID_MAIN_RC]);
 450         if (IS_ERR(c)) {
 451                 ret = PTR_ERR(c);
 452                 goto fail;
 453         }
 454         clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), c);
 455
 456         /* Register main oscillator. */
 457         c = at91_clk_main_osc(base, clk_names[ID_MAIN_OSC],
 458                               clk_names[ID_MAIN_XTAL], false);
 459         if (IS_ERR(c)) {
 460                 ret = PTR_ERR(c);
 461                 goto fail;
 462         }
 463         clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), c);
 464
 465         /* Register mainck. */
 466         p[0] = clk_names[ID_MAIN_RC_OSC];
 467         p[1] = clk_names[ID_MAIN_OSC];
 468         cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC);
 469         cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC);
 470         prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
 471                           fail);
 472         c = at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p,
 473                                  2, tmpclkmux, PMC_TYPE_CORE);
 474         if (IS_ERR(c)) {
 475                 ret = PTR_ERR(c);
 476                 goto fail;
 477         }
 478         clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), c);
 479
 480         /* Register PLL fracs clocks. */
 481         for (i = 0; i < ARRAY_SIZE(sam9x60_plls); i++) {
 482                 if (sam9x60_plls[i].t != PLL_TYPE_FRAC)
 483                         continue;
 484
 485                 c = sam9x60_clk_register_frac_pll(base, sam9x60_plls[i].n,
 486                                                   sam9x60_plls[i].p,
 487                                                   sam9x60_plls[i].id,
 488                                                   sam9x60_plls[i].c,
 489                                                   sam9x60_plls[i].l,
 490                                                   sam9x60_plls[i].f);
 491                 if (IS_ERR(c)) {
 492                         ret = PTR_ERR(c);
 493                         goto fail;
 494                 }
 495                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
 496         }
 497
 498         /* Register PLL div clocks. */
 499         for (i = 0; i < ARRAY_SIZE(sam9x60_plls); i++) {
 500                 if (sam9x60_plls[i].t != PLL_TYPE_DIV)
 501                         continue;
 502
 503                 c = sam9x60_clk_register_div_pll(base, sam9x60_plls[i].n,
 504                                                  sam9x60_plls[i].p,
 505                                                  sam9x60_plls[i].id,
 506                                                  sam9x60_plls[i].c,
 507                                                  sam9x60_plls[i].l,
 508                                                  sam9x60_plls[i].f);
 509                 if (IS_ERR(c)) {
 510                         ret = PTR_ERR(c);
 511                         goto fail;
 512                 }
 513                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
 514         }
 515
 516         /* Register MCK pres clock. */
 517         p[0] = clk_names[ID_MD_SLCK];
 518         p[1] = clk_names[ID_MAINCK];
 519         p[2] = clk_names[ID_PLL_A_DIV];
 520         p[3] = clk_names[ID_PLL_U_DIV];
 521         cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
 522         cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
 523         cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
 524         cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
 525         prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4,
 526                           fail);
 527         c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4,
 528                                           &mck_layout, &mck_characteristics,
 529                                           tmpclkmux);
 530         if (IS_ERR(c)) {
 531                 ret = PTR_ERR(c);
 532                 goto fail;
 533         }
 534         clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c);
 535
 536         /* Register MCK div clock. */
 537         c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV],
 538                                          clk_names[ID_MCK_PRES],
 539                                          &mck_layout, &mck_characteristics);
 540         if (IS_ERR(c)) {
 541                 ret = PTR_ERR(c);
 542                 goto fail;
 543         }
 544         clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c);
 545
 546         /* Register programmable clocks. */
 547         p[0] = clk_names[ID_MD_SLCK];
 548         p[1] = clk_names[ID_TD_SLCK];
 549         p[2] = clk_names[ID_MAINCK];
 550         p[3] = clk_names[ID_MCK_DIV];
 551         p[4] = clk_names[ID_PLL_A_DIV];
 552         p[5] = clk_names[ID_PLL_U_DIV];
 553         cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
 554         cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
 555         cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
 556         cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
 557         cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
 558         cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
 559         for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) {
 560                 prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
 561                                   6, fail);
 562
 563                 c = at91_clk_register_programmable(base, sam9x60_prog[i].n, p,
 564                                                    10, i, &programmable_layout,
 565                                                    tmpclkmux,
 566                                                    sam9x60_prog_mux_table);
 567                 if (IS_ERR(c)) {
 568                         ret = PTR_ERR(c);
 569                         goto fail;
 570                 }
 571                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_prog[i].cid), c);
 572         }
 573
 574         /* System clocks. */
 575         for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
 576                 c = at91_clk_register_system(base, sam9x60_systemck[i].n,
 577                                              sam9x60_systemck[i].p,
 578                                              sam9x60_systemck[i].id);
 579                 if (IS_ERR(c)) {
 580                         ret = PTR_ERR(c);
 581                         goto fail;
 582                 }
 583                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sam9x60_systemck[i].cid),
 584                        c);
 585         }
 586
 587         /* Peripheral clocks. */
 588         for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
 589                 c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout,
 590                                                         sam9x60_periphck[i].n,
 591                                                         clk_names[ID_MCK_DIV],
 592                                                         sam9x60_periphck[i].id,
 593                                                         &r);
 594                 if (IS_ERR(c)) {
 595                         ret = PTR_ERR(c);
 596                         goto fail;
 597                 }
 598                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL,
 599                                       sam9x60_periphck[i].id), c);
 600         }
 601
 602         /* Generic clocks. */
 603         p[0] = clk_names[ID_MD_SLCK];
 604         p[1] = clk_names[ID_TD_SLCK];
 605         p[2] = clk_names[ID_MAINCK];
 606         p[3] = clk_names[ID_MCK_DIV];
 607         p[4] = clk_names[ID_PLL_A_DIV];
 608         p[5] = clk_names[ID_PLL_U_DIV];
 609         m[0] = 0;
 610         m[1] = 1;
 611         m[2] = 2;
 612         m[3] = 3;
 613         m[4] = 4;
 614         m[5] = 5;
 615         cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
 616         cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
 617         cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
 618         cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV);
 619         cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
 620         cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
 621         for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
 622                 prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
 623                                   6, fail);
 624                 prepare_mux_table(muxallocs, muxallocindex, tmpmux, m,
 625                                   6, fail);
 626
 627                 c = at91_clk_register_generic(base, &pcr_layout,
 628                                               sam9x60_gck[i].n, p, tmpclkmux,
 629                                               tmpmux, 6, sam9x60_gck[i].id,
 630                                               &sam9x60_gck[i].r);
 631                 if (IS_ERR(c)) {
 632                         ret = PTR_ERR(c);
 633                         goto fail;
 634                 }
 635                 clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c);
 636         }
 637
 638         return 0;
 639
 640 fail:
 641         for (i = 0; i < ARRAY_SIZE(muxallocs); i++)
 642                 kfree(muxallocs[i]);
 643
 644         for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++)
 645                 kfree(clkmuxallocs[i]);
 646
 647         return ret;
 648 }
 649
 650 static const struct udevice_id sam9x60_clk_ids[] = {
 651         { .compatible = "microchip,sam9x60-pmc" },
 652         { /* Sentinel. */ },
 653 };
 654
 655 U_BOOT_DRIVER(at91_sam9x60_pmc) = {
 656         .name = "at91-sam9x60-pmc",
 657         .id = UCLASS_CLK,
 658         .of_match = sam9x60_clk_ids,
 659         .ops = &at91_clk_ops,
 660         .probe = sam9x60_clk_probe,
 661         .flags = DM_FLAG_PRE_RELOC,
 662 };