drivers/clk/at91/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Atmel Corporation
   4  *               Wenyou.Yang <wenyou.yang@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <dm/lists.h>
  12 #include <dm/util.h>
  13 #include "pmc.h"
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 static const struct udevice_id at91_pmc_match[] = {
  18         { .compatible = "atmel,at91rm9200-pmc" },
  19         { .compatible = "atmel,at91sam9260-pmc" },
  20         { .compatible = "atmel,at91sam9g45-pmc" },
  21         { .compatible = "atmel,at91sam9n12-pmc" },
  22         { .compatible = "atmel,at91sam9x5-pmc" },
  23         { .compatible = "atmel,sama5d3-pmc" },
  24         { .compatible = "atmel,sama5d2-pmc" },
  25         {}
  26 };
  27
  28 U_BOOT_DRIVER(atmel_at91rm9200_pmc) = {
  29         .name = "atmel_at91rm9200_pmc",
  30         .id = UCLASS_SIMPLE_BUS,
  31         .of_match = at91_pmc_match,
  32 };
  33
  34 U_BOOT_DRIVER_ALIAS(atmel_at91rm9200_pmc, atmel_at91sam9260_pmc)
  35
  36 /*---------------------------------------------------------*/
  37
  38 int at91_pmc_core_probe(struct udevice *dev)
  39 {
  40         struct pmc_platdata *plat = dev_get_platdata(dev);
  41
  42         dev = dev_get_parent(dev);
  43
  44         plat->reg_base = dev_read_addr_ptr(dev);
  45
  46         return 0;
  47 }
  48
  49 /**
  50  * at91_clk_sub_device_bind() - for the at91 clock driver
  51  * Recursively bind its children as clk devices.
  52  *
  53  * @return: 0 on success, or negative error code on failure
  54  */
  55 int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  56 {
  57         const void *fdt = gd->fdt_blob;
  58         int offset = dev_of_offset(dev);
  59         bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  60         const char *name;
  61         int ret;
  62
  63         for (offset = fdt_first_subnode(fdt, offset);
  64              offset > 0;
  65              offset = fdt_next_subnode(fdt, offset)) {
  66                 if (pre_reloc_only &&
  67                     !ofnode_pre_reloc(offset_to_ofnode(offset)))
  68                         continue;
  69                 /*
  70                  * If this node has "compatible" property, this is not
  71                  * a clock sub-node, but a normal device. skip.
  72                  */
  73                 fdt_get_property(fdt, offset, "compatible", &ret);
  74                 if (ret >= 0)
  75                         continue;
  76
  77                 if (ret != -FDT_ERR_NOTFOUND)
  78                         return ret;
  79
  80                 name = fdt_get_name(fdt, offset, NULL);
  81                 if (!name)
  82                         return -EINVAL;
  83                 ret = device_bind_driver_to_node(dev, drv_name, name,
  84                                         offset_to_ofnode(offset), NULL);
  85                 if (ret)
  86                         return ret;
  87         }
  88
  89         return 0;
  90 }
  91
  92 int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  93 {
  94         int periph;
  95
  96         if (args->args_count) {
  97                 debug("Invalid args_count: %d\n", args->args_count);
  98                 return -EINVAL;
  99         }
 100
 101         periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
 102                                  -1);
 103         if (periph < 0)
 104                 return -EINVAL;
 105
 106         clk->id = periph;
 107
 108         return 0;
 109 }
 110
 111 int at91_clk_probe(struct udevice *dev)
 112 {
 113         struct udevice *dev_periph_container, *dev_pmc;
 114         struct pmc_platdata *plat = dev_get_platdata(dev);
 115
 116         dev_periph_container = dev_get_parent(dev);
 117         dev_pmc = dev_get_parent(dev_periph_container);
 118
 119         plat->reg_base = dev_read_addr_ptr(dev_pmc);
 120
 121         return 0;
 122 }