1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
11 #define MASTER_SOURCE_MAX 4
13 #define PERIPHERAL_AT91RM9200 0
14 #define PERIPHERAL_AT91SAM9X5 1
16 #define PERIPHERAL_MAX 64
18 #define PERIPHERAL_ID_MIN 2
20 #define PROG_SOURCE_MAX 5
23 #define SYSTEM_MAX_ID 31
25 #define GCK_INDEX_DT_AUDIO_PLL 5
27 static DEFINE_SPINLOCK(mck_lock);
29 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
30 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
33 const char *name = np->name;
34 const char *parent_name;
35 struct regmap *regmap;
36 struct device_node *parent_np;
38 parent_np = of_get_parent(np);
39 regmap = syscon_node_to_regmap(parent_np);
40 of_node_put(parent_np);
44 parent_name = of_clk_get_parent_name(np, 0);
46 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
50 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
52 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
53 "atmel,sama5d2-clk-audio-pll-frac",
54 of_sama5d2_clk_audio_pll_frac_setup);
56 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
59 const char *name = np->name;
60 const char *parent_name;
61 struct regmap *regmap;
62 struct device_node *parent_np;
64 parent_np = of_get_parent(np);
65 regmap = syscon_node_to_regmap(parent_np);
66 of_node_put(parent_np);
70 parent_name = of_clk_get_parent_name(np, 0);
72 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
76 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
78 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
79 "atmel,sama5d2-clk-audio-pll-pad",
80 of_sama5d2_clk_audio_pll_pad_setup);
82 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
85 const char *name = np->name;
86 const char *parent_name;
87 struct regmap *regmap;
88 struct device_node *parent_np;
90 parent_np = of_get_parent(np);
91 regmap = syscon_node_to_regmap(parent_np);
92 of_node_put(parent_np);
96 parent_name = of_clk_get_parent_name(np, 0);
98 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
102 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
104 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
105 "atmel,sama5d2-clk-audio-pll-pmc",
106 of_sama5d2_clk_audio_pll_pmc_setup);
107 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
109 static const struct clk_pcr_layout dt_pcr_layout = {
112 .pid_mask = GENMASK(5, 0),
113 .div_mask = GENMASK(17, 16),
114 .gckcss_mask = GENMASK(10, 8),
117 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
118 #define GENERATED_SOURCE_MAX 6
120 #define GCK_ID_I2S0 54
121 #define GCK_ID_I2S1 55
122 #define GCK_ID_CLASSD 59
124 static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
130 unsigned int num_parents;
131 const char *parent_names[GENERATED_SOURCE_MAX];
132 struct device_node *gcknp, *parent_np;
133 struct clk_range range = CLK_RANGE(0, 0);
134 struct regmap *regmap;
136 num_parents = of_clk_get_parent_count(np);
137 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
140 of_clk_parent_fill(np, parent_names, num_parents);
142 num = of_get_child_count(np);
143 if (!num || num > PERIPHERAL_MAX)
146 parent_np = of_get_parent(np);
147 regmap = syscon_node_to_regmap(parent_np);
148 of_node_put(parent_np);
152 for_each_child_of_node(np, gcknp) {
153 int chg_pid = INT_MIN;
155 if (of_property_read_u32(gcknp, "reg", &id))
158 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
161 if (of_property_read_string(np, "clock-output-names", &name))
164 of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
167 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
168 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
169 id == GCK_ID_CLASSD))
170 chg_pid = GCK_INDEX_DT_AUDIO_PLL;
172 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
173 &dt_pcr_layout, name,
175 num_parents, id, &range,
180 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
183 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
184 of_sama5d2_clk_generated_setup);
185 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
187 #ifdef CONFIG_HAVE_AT91_H32MX
188 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
191 const char *name = np->name;
192 const char *parent_name;
193 struct regmap *regmap;
194 struct device_node *parent_np;
196 parent_np = of_get_parent(np);
197 regmap = syscon_node_to_regmap(parent_np);
198 of_node_put(parent_np);
202 parent_name = of_clk_get_parent_name(np, 0);
204 hw = at91_clk_register_h32mx(regmap, name, parent_name);
208 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
210 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
211 of_sama5d4_clk_h32mx_setup);
212 #endif /* CONFIG_HAVE_AT91_H32MX */
214 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
217 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
219 struct regmap *regmap_sfr;
221 const char *parent_names[2];
222 struct device_node *i2s_mux_np;
226 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
227 if (IS_ERR(regmap_sfr))
230 for_each_child_of_node(np, i2s_mux_np) {
231 if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
234 if (bus_id > I2S_BUS_NR)
237 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
241 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
242 parent_names, 2, bus_id);
246 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
249 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
250 of_sama5d2_clk_i2s_mux_setup);
251 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
253 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
256 const char *name = np->name;
257 const char *parent_name;
258 struct regmap *regmap;
260 struct device_node *parent_np;
262 of_property_read_string(np, "clock-output-names", &name);
263 bypass = of_property_read_bool(np, "atmel,osc-bypass");
264 parent_name = of_clk_get_parent_name(np, 0);
266 parent_np = of_get_parent(np);
267 regmap = syscon_node_to_regmap(parent_np);
268 of_node_put(parent_np);
272 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
276 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
278 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
279 of_at91rm9200_clk_main_osc_setup);
281 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
286 const char *name = np->name;
287 struct regmap *regmap;
288 struct device_node *parent_np;
290 of_property_read_string(np, "clock-output-names", &name);
291 of_property_read_u32(np, "clock-frequency", &frequency);
292 of_property_read_u32(np, "clock-accuracy", &accuracy);
294 parent_np = of_get_parent(np);
295 regmap = syscon_node_to_regmap(parent_np);
296 of_node_put(parent_np);
300 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
304 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
306 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
307 of_at91sam9x5_clk_main_rc_osc_setup);
309 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
312 const char *parent_name;
313 const char *name = np->name;
314 struct regmap *regmap;
315 struct device_node *parent_np;
317 parent_name = of_clk_get_parent_name(np, 0);
318 of_property_read_string(np, "clock-output-names", &name);
320 parent_np = of_get_parent(np);
321 regmap = syscon_node_to_regmap(parent_np);
322 of_node_put(parent_np);
326 hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
330 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
332 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
333 of_at91rm9200_clk_main_setup);
335 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
338 const char *parent_names[2];
339 unsigned int num_parents;
340 const char *name = np->name;
341 struct regmap *regmap;
342 struct device_node *parent_np;
344 num_parents = of_clk_get_parent_count(np);
345 if (num_parents == 0 || num_parents > 2)
348 of_clk_parent_fill(np, parent_names, num_parents);
349 parent_np = of_get_parent(np);
350 regmap = syscon_node_to_regmap(parent_np);
351 of_node_put(parent_np);
355 of_property_read_string(np, "clock-output-names", &name);
357 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
362 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
364 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
365 of_at91sam9x5_clk_main_setup);
367 static struct clk_master_characteristics * __init
368 of_at91_clk_master_get_characteristics(struct device_node *np)
370 struct clk_master_characteristics *characteristics;
372 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
373 if (!characteristics)
376 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
377 goto out_free_characteristics;
379 of_property_read_u32_array(np, "atmel,clk-divisors",
380 characteristics->divisors, 4);
382 characteristics->have_div3_pres =
383 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
385 return characteristics;
387 out_free_characteristics:
388 kfree(characteristics);
393 of_at91_clk_master_setup(struct device_node *np,
394 const struct clk_master_layout *layout)
397 unsigned int num_parents;
398 const char *parent_names[MASTER_SOURCE_MAX];
399 const char *name = np->name;
400 struct clk_master_characteristics *characteristics;
401 struct regmap *regmap;
402 struct device_node *parent_np;
404 num_parents = of_clk_get_parent_count(np);
405 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
408 of_clk_parent_fill(np, parent_names, num_parents);
410 of_property_read_string(np, "clock-output-names", &name);
412 characteristics = of_at91_clk_master_get_characteristics(np);
413 if (!characteristics)
416 parent_np = of_get_parent(np);
417 regmap = syscon_node_to_regmap(parent_np);
418 of_node_put(parent_np);
422 hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents,
423 parent_names, layout,
424 characteristics, &mck_lock);
426 goto out_free_characteristics;
428 hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
429 layout, characteristics,
430 &mck_lock, CLK_SET_RATE_GATE, 0);
432 goto out_free_characteristics;
434 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
437 out_free_characteristics:
438 kfree(characteristics);
441 static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
443 of_at91_clk_master_setup(np, &at91rm9200_master_layout);
445 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
446 of_at91rm9200_clk_master_setup);
448 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
450 of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
452 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
453 of_at91sam9x5_clk_master_setup);
456 of_at91_clk_periph_setup(struct device_node *np, u8 type)
461 const char *parent_name;
463 struct device_node *periphclknp;
464 struct regmap *regmap;
465 struct device_node *parent_np;
467 parent_name = of_clk_get_parent_name(np, 0);
471 num = of_get_child_count(np);
472 if (!num || num > PERIPHERAL_MAX)
475 parent_np = of_get_parent(np);
476 regmap = syscon_node_to_regmap(parent_np);
477 of_node_put(parent_np);
481 for_each_child_of_node(np, periphclknp) {
482 if (of_property_read_u32(periphclknp, "reg", &id))
485 if (id >= PERIPHERAL_MAX)
488 if (of_property_read_string(np, "clock-output-names", &name))
489 name = periphclknp->name;
491 if (type == PERIPHERAL_AT91RM9200) {
492 hw = at91_clk_register_peripheral(regmap, name,
495 struct clk_range range = CLK_RANGE(0, 0);
497 of_at91_get_clk_range(periphclknp,
498 "atmel,clk-output-range",
501 hw = at91_clk_register_sam9x5_peripheral(regmap,
513 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
517 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
519 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
521 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
522 of_at91rm9200_clk_periph_setup);
524 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
526 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
528 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
529 of_at91sam9x5_clk_periph_setup);
531 static struct clk_pll_characteristics * __init
532 of_at91_clk_pll_get_characteristics(struct device_node *np)
539 struct clk_range input;
540 struct clk_range *output;
543 struct clk_pll_characteristics *characteristics;
545 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
548 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
552 if (num_cells < 2 || num_cells > 4)
555 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
557 num_output = tmp / (sizeof(u32) * num_cells);
559 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
560 if (!characteristics)
563 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
565 goto out_free_characteristics;
568 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
570 goto out_free_output;
574 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
576 goto out_free_output;
579 for (i = 0; i < num_output; i++) {
580 offset = i * num_cells;
581 if (of_property_read_u32_index(np,
582 "atmel,pll-clk-output-ranges",
584 goto out_free_output;
586 if (of_property_read_u32_index(np,
587 "atmel,pll-clk-output-ranges",
589 goto out_free_output;
595 if (of_property_read_u32_index(np,
596 "atmel,pll-clk-output-ranges",
598 goto out_free_output;
604 if (of_property_read_u32_index(np,
605 "atmel,pll-clk-output-ranges",
607 goto out_free_output;
611 characteristics->input = input;
612 characteristics->num_output = num_output;
613 characteristics->output = output;
614 characteristics->out = out;
615 characteristics->icpll = icpll;
616 return characteristics;
622 out_free_characteristics:
623 kfree(characteristics);
628 of_at91_clk_pll_setup(struct device_node *np,
629 const struct clk_pll_layout *layout)
633 struct regmap *regmap;
634 const char *parent_name;
635 const char *name = np->name;
636 struct device_node *parent_np;
637 struct clk_pll_characteristics *characteristics;
639 if (of_property_read_u32(np, "reg", &id))
642 parent_name = of_clk_get_parent_name(np, 0);
644 of_property_read_string(np, "clock-output-names", &name);
646 parent_np = of_get_parent(np);
647 regmap = syscon_node_to_regmap(parent_np);
648 of_node_put(parent_np);
652 characteristics = of_at91_clk_pll_get_characteristics(np);
653 if (!characteristics)
656 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
659 goto out_free_characteristics;
661 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
664 out_free_characteristics:
665 kfree(characteristics);
668 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
670 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
672 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
673 of_at91rm9200_clk_pll_setup);
675 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
677 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
679 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
680 of_at91sam9g45_clk_pll_setup);
682 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
684 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
686 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
687 of_at91sam9g20_clk_pllb_setup);
689 static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
691 of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
693 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
694 of_sama5d3_clk_pll_setup);
697 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
700 const char *parent_name;
701 const char *name = np->name;
702 struct regmap *regmap;
703 struct device_node *parent_np;
705 parent_name = of_clk_get_parent_name(np, 0);
707 of_property_read_string(np, "clock-output-names", &name);
709 parent_np = of_get_parent(np);
710 regmap = syscon_node_to_regmap(parent_np);
711 of_node_put(parent_np);
715 hw = at91_clk_register_plldiv(regmap, name, parent_name);
719 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
721 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
722 of_at91sam9x5_clk_plldiv_setup);
725 of_at91_clk_prog_setup(struct device_node *np,
726 const struct clk_programmable_layout *layout,
732 unsigned int num_parents;
733 const char *parent_names[PROG_SOURCE_MAX];
735 struct device_node *progclknp, *parent_np;
736 struct regmap *regmap;
738 num_parents = of_clk_get_parent_count(np);
739 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
742 of_clk_parent_fill(np, parent_names, num_parents);
744 num = of_get_child_count(np);
745 if (!num || num > (PROG_ID_MAX + 1))
748 parent_np = of_get_parent(np);
749 regmap = syscon_node_to_regmap(parent_np);
750 of_node_put(parent_np);
754 for_each_child_of_node(np, progclknp) {
755 if (of_property_read_u32(progclknp, "reg", &id))
758 if (of_property_read_string(np, "clock-output-names", &name))
759 name = progclknp->name;
761 hw = at91_clk_register_programmable(regmap, name,
762 parent_names, num_parents,
763 id, layout, mux_table);
767 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
771 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
773 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL);
775 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
776 of_at91rm9200_clk_prog_setup);
778 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
780 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL);
782 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
783 of_at91sam9g45_clk_prog_setup);
785 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
787 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL);
789 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
790 of_at91sam9x5_clk_prog_setup);
792 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
795 const char *parent_names[2];
796 unsigned int num_parents;
797 const char *name = np->name;
798 struct regmap *regmap;
799 struct device_node *parent_np;
801 num_parents = of_clk_get_parent_count(np);
802 if (num_parents != 2)
805 of_clk_parent_fill(np, parent_names, num_parents);
806 parent_np = of_get_parent(np);
807 regmap = syscon_node_to_regmap(parent_np);
808 of_node_put(parent_np);
812 of_property_read_string(np, "clock-output-names", &name);
814 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
819 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
821 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
822 of_at91sam9260_clk_slow_setup);
824 #ifdef CONFIG_HAVE_AT91_SMD
825 #define SMD_SOURCE_MAX 2
827 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
830 unsigned int num_parents;
831 const char *parent_names[SMD_SOURCE_MAX];
832 const char *name = np->name;
833 struct regmap *regmap;
834 struct device_node *parent_np;
836 num_parents = of_clk_get_parent_count(np);
837 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
840 of_clk_parent_fill(np, parent_names, num_parents);
842 of_property_read_string(np, "clock-output-names", &name);
844 parent_np = of_get_parent(np);
845 regmap = syscon_node_to_regmap(parent_np);
846 of_node_put(parent_np);
850 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
855 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
857 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
858 of_at91sam9x5_clk_smd_setup);
859 #endif /* CONFIG_HAVE_AT91_SMD */
861 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
867 struct device_node *sysclknp, *parent_np;
868 const char *parent_name;
869 struct regmap *regmap;
871 num = of_get_child_count(np);
872 if (num > (SYSTEM_MAX_ID + 1))
875 parent_np = of_get_parent(np);
876 regmap = syscon_node_to_regmap(parent_np);
877 of_node_put(parent_np);
881 for_each_child_of_node(np, sysclknp) {
882 if (of_property_read_u32(sysclknp, "reg", &id))
885 if (of_property_read_string(np, "clock-output-names", &name))
886 name = sysclknp->name;
888 parent_name = of_clk_get_parent_name(sysclknp, 0);
890 hw = at91_clk_register_system(regmap, name, parent_name, id);
894 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
897 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
898 of_at91rm9200_clk_sys_setup);
900 #ifdef CONFIG_HAVE_AT91_USB_CLK
901 #define USB_SOURCE_MAX 2
903 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
906 unsigned int num_parents;
907 const char *parent_names[USB_SOURCE_MAX];
908 const char *name = np->name;
909 struct regmap *regmap;
910 struct device_node *parent_np;
912 num_parents = of_clk_get_parent_count(np);
913 if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
916 of_clk_parent_fill(np, parent_names, num_parents);
918 of_property_read_string(np, "clock-output-names", &name);
920 parent_np = of_get_parent(np);
921 regmap = syscon_node_to_regmap(parent_np);
922 of_node_put(parent_np);
926 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
931 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
933 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
934 of_at91sam9x5_clk_usb_setup);
936 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
939 const char *parent_name;
940 const char *name = np->name;
941 struct regmap *regmap;
942 struct device_node *parent_np;
944 parent_name = of_clk_get_parent_name(np, 0);
948 of_property_read_string(np, "clock-output-names", &name);
950 parent_np = of_get_parent(np);
951 regmap = syscon_node_to_regmap(parent_np);
952 of_node_put(parent_np);
956 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
960 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
962 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
963 of_at91sam9n12_clk_usb_setup);
965 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
968 const char *parent_name;
969 const char *name = np->name;
970 u32 divisors[4] = {0, 0, 0, 0};
971 struct regmap *regmap;
972 struct device_node *parent_np;
974 parent_name = of_clk_get_parent_name(np, 0);
978 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
982 of_property_read_string(np, "clock-output-names", &name);
984 parent_np = of_get_parent(np);
985 regmap = syscon_node_to_regmap(parent_np);
986 of_node_put(parent_np);
989 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
993 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
995 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
996 of_at91rm9200_clk_usb_setup);
997 #endif /* CONFIG_HAVE_AT91_USB_CLK */
999 #ifdef CONFIG_HAVE_AT91_UTMI
1000 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
1003 const char *parent_name;
1004 const char *name = np->name;
1005 struct regmap *regmap_pmc, *regmap_sfr;
1006 struct device_node *parent_np;
1008 parent_name = of_clk_get_parent_name(np, 0);
1010 of_property_read_string(np, "clock-output-names", &name);
1012 parent_np = of_get_parent(np);
1013 regmap_pmc = syscon_node_to_regmap(parent_np);
1014 of_node_put(parent_np);
1015 if (IS_ERR(regmap_pmc))
1019 * If the device supports different mainck rates, this value has to be
1020 * set in the UTMI Clock Trimming register.
1021 * - 9x5: mainck supports several rates but it is indicated that a
1022 * 12 MHz is needed in case of USB.
1023 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
1024 * the FREQ field of the UTMI Clock Trimming register is mandatory.
1025 * - sama5d4: mainck is at 12 MHz.
1027 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
1029 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
1030 if (IS_ERR(regmap_sfr)) {
1031 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
1032 if (IS_ERR(regmap_sfr))
1036 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
1040 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
1042 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
1043 of_at91sam9x5_clk_utmi_setup);
1044 #endif /* CONFIG_HAVE_AT91_UTMI */