drivers/clk/at91/compat.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Compatible code for non CCF AT91 platforms.
   4  *
   5  * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
   8  */
   9 #include <common.h>
  10 #include <clk-uclass.h>
  11 #include <dm.h>
  12 #include <dm/lists.h>
  13 #include <dm/util.h>
  14 #include <mach/at91_pmc.h>
  15 #include <mach/at91_sfr.h>
  16 #include <regmap.h>
  17 #include <syscon.h>
  18
  19 #include "pmc.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct pmc_platdata {
  24         struct at91_pmc *reg_base;
  25         struct regmap *regmap_sfr;
  26 };
  27
  28 static const struct udevice_id at91_pmc_match[] = {
  29         { .compatible = "atmel,at91rm9200-pmc" },
  30         { .compatible = "atmel,at91sam9260-pmc" },
  31         { .compatible = "atmel,at91sam9g45-pmc" },
  32         { .compatible = "atmel,at91sam9n12-pmc" },
  33         { .compatible = "atmel,at91sam9x5-pmc" },
  34         { .compatible = "atmel,sama5d3-pmc" },
  35         { .compatible = "atmel,sama5d2-pmc" },
  36         {}
  37 };
  38
  39 U_BOOT_DRIVER(at91_pmc) = {
  40         .name = "at91-pmc",
  41         .id = UCLASS_SIMPLE_BUS,
  42         .of_match = at91_pmc_match,
  43 };
  44
  45 static int at91_pmc_core_probe(struct udevice *dev)
  46 {
  47         struct pmc_platdata *plat = dev_get_platdata(dev);
  48
  49         dev = dev_get_parent(dev);
  50
  51         plat->reg_base = dev_read_addr_ptr(dev);
  52
  53         return 0;
  54 }
  55
  56 /**
  57  * at91_clk_sub_device_bind() - for the at91 clock driver
  58  * Recursively bind its children as clk devices.
  59  *
  60  * @return: 0 on success, or negative error code on failure
  61  */
  62 int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  63 {
  64         const void *fdt = gd->fdt_blob;
  65         int offset = dev_of_offset(dev);
  66         bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  67         const char *name;
  68         int ret;
  69
  70         for (offset = fdt_first_subnode(fdt, offset);
  71              offset > 0;
  72              offset = fdt_next_subnode(fdt, offset)) {
  73                 if (pre_reloc_only &&
  74                     !ofnode_pre_reloc(offset_to_ofnode(offset)))
  75                         continue;
  76                 /*
  77                  * If this node has "compatible" property, this is not
  78                  * a clock sub-node, but a normal device. skip.
  79                  */
  80                 fdt_get_property(fdt, offset, "compatible", &ret);
  81                 if (ret >= 0)
  82                         continue;
  83
  84                 if (ret != -FDT_ERR_NOTFOUND)
  85                         return ret;
  86
  87                 name = fdt_get_name(fdt, offset, NULL);
  88                 if (!name)
  89                         return -EINVAL;
  90                 ret = device_bind_driver_to_node(dev, drv_name, name,
  91                                         offset_to_ofnode(offset), NULL);
  92                 if (ret)
  93                         return ret;
  94         }
  95
  96         return 0;
  97 }
  98
  99 int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 100 {
 101         int periph;
 102
 103         if (args->args_count) {
 104                 debug("Invalid args_count: %d\n", args->args_count);
 105                 return -EINVAL;
 106         }
 107
 108         periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
 109                                  -1);
 110         if (periph < 0)
 111                 return -EINVAL;
 112
 113         clk->id = periph;
 114
 115         return 0;
 116 }
 117
 118 int at91_clk_probe(struct udevice *dev)
 119 {
 120         struct udevice *dev_periph_container, *dev_pmc;
 121         struct pmc_platdata *plat = dev_get_platdata(dev);
 122
 123         dev_periph_container = dev_get_parent(dev);
 124         dev_pmc = dev_get_parent(dev_periph_container);
 125
 126         plat->reg_base = dev_read_addr_ptr(dev_pmc);
 127
 128         return 0;
 129 }
 130
 131 /* SCKC specific code. */
 132 static const struct udevice_id at91_sckc_match[] = {
 133         { .compatible = "atmel,at91sam9x5-sckc" },
 134         {}
 135 };
 136
 137 U_BOOT_DRIVER(at91_sckc) = {
 138         .name = "at91-sckc",
 139         .id = UCLASS_SIMPLE_BUS,
 140         .of_match = at91_sckc_match,
 141 };
 142
 143 /* Slow clock specific code. */
 144 static int at91_slow_clk_enable(struct clk *clk)
 145 {
 146         return 0;
 147 }
 148
 149 static ulong at91_slow_clk_get_rate(struct clk *clk)
 150 {
 151         return CONFIG_SYS_AT91_SLOW_CLOCK;
 152 }
 153
 154 static struct clk_ops at91_slow_clk_ops = {
 155         .enable = at91_slow_clk_enable,
 156         .get_rate = at91_slow_clk_get_rate,
 157 };
 158
 159 static const struct udevice_id at91_slow_clk_match[] = {
 160         { .compatible = "atmel,at91sam9x5-clk-slow" },
 161         {}
 162 };
 163
 164 U_BOOT_DRIVER(at91_slow_clk) = {
 165         .name = "at91-slow-clk",
 166         .id = UCLASS_CLK,
 167         .of_match = at91_slow_clk_match,
 168         .ops = &at91_slow_clk_ops,
 169 };
 170
 171 /* Master clock specific code. */
 172 static ulong at91_master_clk_get_rate(struct clk *clk)
 173 {
 174         return gd->arch.mck_rate_hz;
 175 }
 176
 177 static struct clk_ops at91_master_clk_ops = {
 178         .get_rate = at91_master_clk_get_rate,
 179 };
 180
 181 static const struct udevice_id at91_master_clk_match[] = {
 182         { .compatible = "atmel,at91rm9200-clk-master" },
 183         { .compatible = "atmel,at91sam9x5-clk-master" },
 184         {}
 185 };
 186
 187 U_BOOT_DRIVER(at91_master_clk) = {
 188         .name = "at91-master-clk",
 189         .id = UCLASS_CLK,
 190         .of_match = at91_master_clk_match,
 191         .ops = &at91_master_clk_ops,
 192 };
 193
 194 /* Main osc clock specific code. */
 195 static int main_osc_clk_enable(struct clk *clk)
 196 {
 197         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 198         struct at91_pmc *pmc = plat->reg_base;
 199
 200         if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
 201                 return 0;
 202
 203         return -EINVAL;
 204 }
 205
 206 static ulong main_osc_clk_get_rate(struct clk *clk)
 207 {
 208         return gd->arch.main_clk_rate_hz;
 209 }
 210
 211 static struct clk_ops main_osc_clk_ops = {
 212         .enable = main_osc_clk_enable,
 213         .get_rate = main_osc_clk_get_rate,
 214 };
 215
 216 static int main_osc_clk_probe(struct udevice *dev)
 217 {
 218         return at91_pmc_core_probe(dev);
 219 }
 220
 221 static const struct udevice_id main_osc_clk_match[] = {
 222         { .compatible = "atmel,at91sam9x5-clk-main" },
 223         {}
 224 };
 225
 226 U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
 227         .name = "at91sam9x5-main-osc-clk",
 228         .id = UCLASS_CLK,
 229         .of_match = main_osc_clk_match,
 230         .probe = main_osc_clk_probe,
 231         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 232         .ops = &main_osc_clk_ops,
 233 };
 234
 235 /* PLLA clock specific code. */
 236 static int plla_clk_enable(struct clk *clk)
 237 {
 238         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 239         struct at91_pmc *pmc = plat->reg_base;
 240
 241         if (readl(&pmc->sr) & AT91_PMC_LOCKA)
 242                 return 0;
 243
 244         return -EINVAL;
 245 }
 246
 247 static ulong plla_clk_get_rate(struct clk *clk)
 248 {
 249         return gd->arch.plla_rate_hz;
 250 }
 251
 252 static struct clk_ops plla_clk_ops = {
 253         .enable = plla_clk_enable,
 254         .get_rate = plla_clk_get_rate,
 255 };
 256
 257 static int plla_clk_probe(struct udevice *dev)
 258 {
 259         return at91_pmc_core_probe(dev);
 260 }
 261
 262 static const struct udevice_id plla_clk_match[] = {
 263         { .compatible = "atmel,sama5d3-clk-pll" },
 264         {}
 265 };
 266
 267 U_BOOT_DRIVER(at91_plla_clk) = {
 268         .name = "at91-plla-clk",
 269         .id = UCLASS_CLK,
 270         .of_match = plla_clk_match,
 271         .probe = plla_clk_probe,
 272         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 273         .ops = &plla_clk_ops,
 274 };
 275
 276 /* PLLA DIV clock specific code. */
 277 static int at91_plladiv_clk_enable(struct clk *clk)
 278 {
 279         return 0;
 280 }
 281
 282 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
 283 {
 284         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 285         struct at91_pmc *pmc = plat->reg_base;
 286         struct clk source;
 287         ulong clk_rate;
 288         int ret;
 289
 290         ret = clk_get_by_index(clk->dev, 0, &source);
 291         if (ret)
 292                 return -EINVAL;
 293
 294         clk_rate = clk_get_rate(&source);
 295         if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
 296                 clk_rate /= 2;
 297
 298         return clk_rate;
 299 }
 300
 301 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
 302 {
 303         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 304         struct at91_pmc *pmc = plat->reg_base;
 305         struct clk source;
 306         ulong parent_rate;
 307         int ret;
 308
 309         ret = clk_get_by_index(clk->dev, 0, &source);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         parent_rate = clk_get_rate(&source);
 314         if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
 315                 return -EINVAL;
 316
 317         if (parent_rate != rate) {
 318                 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
 319                        &pmc->mckr);
 320         }
 321
 322         return 0;
 323 }
 324
 325 static struct clk_ops at91_plladiv_clk_ops = {
 326         .enable = at91_plladiv_clk_enable,
 327         .get_rate = at91_plladiv_clk_get_rate,
 328         .set_rate = at91_plladiv_clk_set_rate,
 329 };
 330
 331 static int at91_plladiv_clk_probe(struct udevice *dev)
 332 {
 333         return at91_pmc_core_probe(dev);
 334 }
 335
 336 static const struct udevice_id at91_plladiv_clk_match[] = {
 337         { .compatible = "atmel,at91sam9x5-clk-plldiv" },
 338         {}
 339 };
 340
 341 U_BOOT_DRIVER(at91_plladiv_clk) = {
 342         .name = "at91-plladiv-clk",
 343         .id = UCLASS_CLK,
 344         .of_match = at91_plladiv_clk_match,
 345         .probe = at91_plladiv_clk_probe,
 346         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 347         .ops = &at91_plladiv_clk_ops,
 348 };
 349
 350 /* System clock specific code. */
 351 #define SYSTEM_MAX_ID           31
 352
 353 /**
 354  * at91_system_clk_bind() - for the system clock driver
 355  * Recursively bind its children as clk devices.
 356  *
 357  * @return: 0 on success, or negative error code on failure
 358  */
 359 static int at91_system_clk_bind(struct udevice *dev)
 360 {
 361         return at91_clk_sub_device_bind(dev, "system-clk");
 362 }
 363
 364 static const struct udevice_id at91_system_clk_match[] = {
 365         { .compatible = "atmel,at91rm9200-clk-system" },
 366         {}
 367 };
 368
 369 U_BOOT_DRIVER(at91_system_clk) = {
 370         .name = "at91-system-clk",
 371         .id = UCLASS_MISC,
 372         .of_match = at91_system_clk_match,
 373         .bind = at91_system_clk_bind,
 374 };
 375
 376 static inline int is_pck(int id)
 377 {
 378         return (id >= 8) && (id <= 15);
 379 }
 380
 381 static ulong system_clk_get_rate(struct clk *clk)
 382 {
 383         struct clk clk_dev;
 384         int ret;
 385
 386         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
 387         if (ret)
 388                 return -EINVAL;
 389
 390         return clk_get_rate(&clk_dev);
 391 }
 392
 393 static ulong system_clk_set_rate(struct clk *clk, ulong rate)
 394 {
 395         struct clk clk_dev;
 396         int ret;
 397
 398         ret = clk_get_by_index(clk->dev, 0, &clk_dev);
 399         if (ret)
 400                 return -EINVAL;
 401
 402         return clk_set_rate(&clk_dev, rate);
 403 }
 404
 405 static int system_clk_enable(struct clk *clk)
 406 {
 407         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 408         struct at91_pmc *pmc = plat->reg_base;
 409         u32 mask;
 410
 411         if (clk->id > SYSTEM_MAX_ID)
 412                 return -EINVAL;
 413
 414         mask = BIT(clk->id);
 415
 416         writel(mask, &pmc->scer);
 417
 418         /**
 419          * For the programmable clocks the Ready status in the PMC
 420          * status register should be checked after enabling.
 421          * For other clocks this is unnecessary.
 422          */
 423         if (!is_pck(clk->id))
 424                 return 0;
 425
 426         while (!(readl(&pmc->sr) & mask))
 427                 ;
 428
 429         return 0;
 430 }
 431
 432 static struct clk_ops system_clk_ops = {
 433         .of_xlate = at91_clk_of_xlate,
 434         .get_rate = system_clk_get_rate,
 435         .set_rate = system_clk_set_rate,
 436         .enable = system_clk_enable,
 437 };
 438
 439 U_BOOT_DRIVER(system_clk) = {
 440         .name = "system-clk",
 441         .id = UCLASS_CLK,
 442         .probe = at91_clk_probe,
 443         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 444         .ops = &system_clk_ops,
 445 };
 446
 447 /* Peripheral clock specific code. */
 448 #define PERIPHERAL_ID_MIN       2
 449 #define PERIPHERAL_ID_MAX       31
 450 #define PERIPHERAL_MASK(id)     (1 << ((id) & PERIPHERAL_ID_MAX))
 451
 452 enum periph_clk_type {
 453         CLK_PERIPH_AT91RM9200 = 0,
 454         CLK_PERIPH_AT91SAM9X5,
 455 };
 456
 457 /**
 458  * sam9x5_periph_clk_bind() - for the periph clock driver
 459  * Recursively bind its children as clk devices.
 460  *
 461  * @return: 0 on success, or negative error code on failure
 462  */
 463 static int sam9x5_periph_clk_bind(struct udevice *dev)
 464 {
 465         return at91_clk_sub_device_bind(dev, "periph-clk");
 466 }
 467
 468 static const struct udevice_id sam9x5_periph_clk_match[] = {
 469         {
 470                 .compatible = "atmel,at91rm9200-clk-peripheral",
 471                 .data = CLK_PERIPH_AT91RM9200,
 472         },
 473         {
 474                 .compatible = "atmel,at91sam9x5-clk-peripheral",
 475                 .data = CLK_PERIPH_AT91SAM9X5,
 476         },
 477         {}
 478 };
 479
 480 U_BOOT_DRIVER(sam9x5_periph_clk) = {
 481         .name = "sam9x5-periph-clk",
 482         .id = UCLASS_MISC,
 483         .of_match = sam9x5_periph_clk_match,
 484         .bind = sam9x5_periph_clk_bind,
 485 };
 486
 487 static int periph_clk_enable(struct clk *clk)
 488 {
 489         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 490         struct at91_pmc *pmc = plat->reg_base;
 491         enum periph_clk_type clk_type;
 492         void *addr;
 493
 494         if (clk->id < PERIPHERAL_ID_MIN)
 495                 return -1;
 496
 497         clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
 498         if (clk_type == CLK_PERIPH_AT91RM9200) {
 499                 addr = &pmc->pcer;
 500                 if (clk->id > PERIPHERAL_ID_MAX)
 501                         addr = &pmc->pcer1;
 502
 503                 setbits_le32(addr, PERIPHERAL_MASK(clk->id));
 504         } else {
 505                 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 506                 setbits_le32(&pmc->pcr,
 507                              AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
 508         }
 509
 510         return 0;
 511 }
 512
 513 static ulong periph_get_rate(struct clk *clk)
 514 {
 515         struct udevice *dev;
 516         struct clk clk_dev;
 517         ulong clk_rate;
 518         int ret;
 519
 520         dev = dev_get_parent(clk->dev);
 521
 522         ret = clk_get_by_index(dev, 0, &clk_dev);
 523         if (ret)
 524                 return ret;
 525
 526         clk_rate = clk_get_rate(&clk_dev);
 527
 528         clk_free(&clk_dev);
 529
 530         return clk_rate;
 531 }
 532
 533 static struct clk_ops periph_clk_ops = {
 534         .of_xlate = at91_clk_of_xlate,
 535         .enable = periph_clk_enable,
 536         .get_rate = periph_get_rate,
 537 };
 538
 539 U_BOOT_DRIVER(clk_periph) = {
 540         .name   = "periph-clk",
 541         .id     = UCLASS_CLK,
 542         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 543         .probe = at91_clk_probe,
 544         .ops    = &periph_clk_ops,
 545 };
 546
 547 /* UTMI clock specific code. */
 548 #ifdef CONFIG_AT91_UTMI
 549
 550 /*
 551  * The purpose of this clock is to generate a 480 MHz signal. A different
 552  * rate can't be configured.
 553  */
 554 #define UTMI_RATE       480000000
 555
 556 static int utmi_clk_enable(struct clk *clk)
 557 {
 558         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 559         struct at91_pmc *pmc = plat->reg_base;
 560         struct clk clk_dev;
 561         ulong clk_rate;
 562         u32 utmi_ref_clk_freq;
 563         u32 tmp;
 564         int err;
 565         int timeout = 2000000;
 566
 567         if (readl(&pmc->sr) & AT91_PMC_LOCKU)
 568                 return 0;
 569
 570         /*
 571          * If mainck rate is different from 12 MHz, we have to configure the
 572          * FREQ field of the SFR_UTMICKTRIM register to generate properly
 573          * the utmi clock.
 574          */
 575         err = clk_get_by_index(clk->dev, 0, &clk_dev);
 576         if (err)
 577                 return -EINVAL;
 578
 579         clk_rate = clk_get_rate(&clk_dev);
 580         switch (clk_rate) {
 581         case 12000000:
 582                 utmi_ref_clk_freq = 0;
 583                 break;
 584         case 16000000:
 585                 utmi_ref_clk_freq = 1;
 586                 break;
 587         case 24000000:
 588                 utmi_ref_clk_freq = 2;
 589                 break;
 590         /*
 591          * Not supported on SAMA5D2 but it's not an issue since MAINCK
 592          * maximum value is 24 MHz.
 593          */
 594         case 48000000:
 595                 utmi_ref_clk_freq = 3;
 596                 break;
 597         default:
 598                 printf("UTMICK: unsupported mainck rate\n");
 599                 return -EINVAL;
 600         }
 601
 602         if (plat->regmap_sfr) {
 603                 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
 604                 if (err)
 605                         return -EINVAL;
 606
 607                 tmp &= ~AT91_UTMICKTRIM_FREQ;
 608                 tmp |= utmi_ref_clk_freq;
 609                 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
 610                 if (err)
 611                         return -EINVAL;
 612         } else if (utmi_ref_clk_freq) {
 613                 printf("UTMICK: sfr node required\n");
 614                 return -EINVAL;
 615         }
 616
 617         tmp = readl(&pmc->uckr);
 618         tmp |= AT91_PMC_UPLLEN |
 619                AT91_PMC_UPLLCOUNT |
 620                AT91_PMC_BIASEN;
 621         writel(tmp, &pmc->uckr);
 622
 623         while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
 624                 ;
 625         if (!timeout) {
 626                 printf("UTMICK: timeout waiting for UPLL lock\n");
 627                 return -ETIMEDOUT;
 628         }
 629
 630         return 0;
 631 }
 632
 633 static ulong utmi_clk_get_rate(struct clk *clk)
 634 {
 635         /* UTMI clk rate is fixed. */
 636         return UTMI_RATE;
 637 }
 638
 639 static struct clk_ops utmi_clk_ops = {
 640         .enable = utmi_clk_enable,
 641         .get_rate = utmi_clk_get_rate,
 642 };
 643
 644 static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
 645 {
 646         struct pmc_platdata *plat = dev_get_platdata(dev);
 647         struct udevice *syscon;
 648
 649         uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 650                                      "regmap-sfr", &syscon);
 651
 652         if (syscon)
 653                 plat->regmap_sfr = syscon_get_regmap(syscon);
 654
 655         return 0;
 656 }
 657
 658 static int utmi_clk_probe(struct udevice *dev)
 659 {
 660         return at91_pmc_core_probe(dev);
 661 }
 662
 663 static const struct udevice_id utmi_clk_match[] = {
 664         { .compatible = "atmel,at91sam9x5-clk-utmi" },
 665         {}
 666 };
 667
 668 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
 669         .name = "at91sam9x5-utmi-clk",
 670         .id = UCLASS_CLK,
 671         .of_match = utmi_clk_match,
 672         .probe = utmi_clk_probe,
 673         .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
 674         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 675         .ops = &utmi_clk_ops,
 676 };
 677
 678 #endif /* CONFIG_AT91_UTMI */
 679
 680 /* H32MX clock specific code. */
 681 #ifdef CONFIG_AT91_H32MX
 682
 683 #define H32MX_MAX_FREQ  90000000
 684
 685 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
 686 {
 687         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 688         struct at91_pmc *pmc = plat->reg_base;
 689         ulong rate = gd->arch.mck_rate_hz;
 690
 691         if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
 692                 rate /= 2;
 693
 694         if (rate > H32MX_MAX_FREQ)
 695                 dev_dbg(clk->dev, "H32MX clock is too fast\n");
 696
 697         return rate;
 698 }
 699
 700 static struct clk_ops sama5d4_h32mx_clk_ops = {
 701         .get_rate = sama5d4_h32mx_clk_get_rate,
 702 };
 703
 704 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
 705 {
 706         return at91_pmc_core_probe(dev);
 707 }
 708
 709 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
 710         { .compatible = "atmel,sama5d4-clk-h32mx" },
 711         {}
 712 };
 713
 714 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
 715         .name = "sama5d4-h32mx-clk",
 716         .id = UCLASS_CLK,
 717         .of_match = sama5d4_h32mx_clk_match,
 718         .probe = sama5d4_h32mx_clk_probe,
 719         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 720         .ops = &sama5d4_h32mx_clk_ops,
 721 };
 722
 723 #endif /* CONFIG_AT91_H32MX */
 724
 725 /* Generic clock specific code. */
 726 #ifdef CONFIG_AT91_GENERIC_CLK
 727
 728 #define GENERATED_SOURCE_MAX    6
 729 #define GENERATED_MAX_DIV       255
 730
 731 /**
 732  * generated_clk_bind() - for the generated clock driver
 733  * Recursively bind its children as clk devices.
 734  *
 735  * @return: 0 on success, or negative error code on failure
 736  */
 737 static int generated_clk_bind(struct udevice *dev)
 738 {
 739         return at91_clk_sub_device_bind(dev, "generic-clk");
 740 }
 741
 742 static const struct udevice_id generated_clk_match[] = {
 743         { .compatible = "atmel,sama5d2-clk-generated" },
 744         {}
 745 };
 746
 747 U_BOOT_DRIVER(generated_clk) = {
 748         .name = "generated-clk",
 749         .id = UCLASS_MISC,
 750         .of_match = generated_clk_match,
 751         .bind = generated_clk_bind,
 752 };
 753
 754 struct generic_clk_priv {
 755         u32 num_parents;
 756 };
 757
 758 static ulong generic_clk_get_rate(struct clk *clk)
 759 {
 760         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 761         struct at91_pmc *pmc = plat->reg_base;
 762         struct clk parent;
 763         ulong clk_rate;
 764         u32 tmp, gckdiv;
 765         u8 clock_source, parent_index;
 766         int ret;
 767
 768         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 769         tmp = readl(&pmc->pcr);
 770         clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
 771                     AT91_PMC_PCR_GCKCSS_MASK;
 772         gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
 773
 774         parent_index = clock_source - 1;
 775         ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
 776         if (ret)
 777                 return 0;
 778
 779         clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
 780
 781         clk_free(&parent);
 782
 783         return clk_rate;
 784 }
 785
 786 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
 787 {
 788         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 789         struct at91_pmc *pmc = plat->reg_base;
 790         struct generic_clk_priv *priv = dev_get_priv(clk->dev);
 791         struct clk parent, best_parent;
 792         ulong tmp_rate, best_rate = rate, parent_rate;
 793         int tmp_diff, best_diff = -1;
 794         u32 div, best_div = 0;
 795         u8 best_parent_index, best_clock_source = 0;
 796         u8 i;
 797         u32 tmp;
 798         int ret;
 799
 800         for (i = 0; i < priv->num_parents; i++) {
 801                 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
 802                 if (ret)
 803                         return ret;
 804
 805                 parent_rate = clk_get_rate(&parent);
 806                 if (IS_ERR_VALUE(parent_rate))
 807                         return parent_rate;
 808
 809                 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
 810                         tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
 811                         tmp_diff = abs(rate - tmp_rate);
 812
 813                         if (best_diff < 0 || best_diff > tmp_diff) {
 814                                 best_rate = tmp_rate;
 815                                 best_diff = tmp_diff;
 816
 817                                 best_div = div - 1;
 818                                 best_parent = parent;
 819                                 best_parent_index = i;
 820                                 best_clock_source = best_parent_index + 1;
 821                         }
 822
 823                         if (!best_diff || tmp_rate < rate)
 824                                 break;
 825                 }
 826
 827                 if (!best_diff)
 828                         break;
 829         }
 830
 831         debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
 832               best_parent.dev->name, best_rate, best_div);
 833
 834         ret = clk_enable(&best_parent);
 835         if (ret)
 836                 return ret;
 837
 838         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 839         tmp = readl(&pmc->pcr);
 840         tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
 841         tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
 842                AT91_PMC_PCR_CMD_WRITE |
 843                AT91_PMC_PCR_GCKDIV_(best_div) |
 844                AT91_PMC_PCR_GCKEN;
 845         writel(tmp, &pmc->pcr);
 846
 847         while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
 848                 ;
 849
 850         return 0;
 851 }
 852
 853 static struct clk_ops generic_clk_ops = {
 854         .of_xlate = at91_clk_of_xlate,
 855         .get_rate = generic_clk_get_rate,
 856         .set_rate = generic_clk_set_rate,
 857 };
 858
 859 static int generic_clk_ofdata_to_platdata(struct udevice *dev)
 860 {
 861         struct generic_clk_priv *priv = dev_get_priv(dev);
 862         u32 cells[GENERATED_SOURCE_MAX];
 863         u32 num_parents;
 864
 865         num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
 866                         dev_of_offset(dev_get_parent(dev)), "clocks", cells,
 867                         GENERATED_SOURCE_MAX);
 868
 869         if (!num_parents)
 870                 return -1;
 871
 872         priv->num_parents = num_parents;
 873
 874         return 0;
 875 }
 876
 877 U_BOOT_DRIVER(generic_clk) = {
 878         .name = "generic-clk",
 879         .id = UCLASS_CLK,
 880         .probe = at91_clk_probe,
 881         .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
 882         .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
 883         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 884         .ops = &generic_clk_ops,
 885 };
 886
 887 #endif /* CONFIG_AT91_GENERIC_CLK */
 888
 889 /* USB clock specific code. */
 890 #ifdef CONFIG_AT91_USB_CLK
 891
 892 #define AT91_USB_CLK_SOURCE_MAX 2
 893 #define AT91_USB_CLK_MAX_DIV    15
 894
 895 struct at91_usb_clk_priv {
 896         u32 num_clksource;
 897 };
 898
 899 static ulong at91_usb_clk_get_rate(struct clk *clk)
 900 {
 901         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 902         struct at91_pmc *pmc = plat->reg_base;
 903         struct clk source;
 904         u32 tmp, usbdiv;
 905         u8 source_index;
 906         int ret;
 907
 908         tmp = readl(&pmc->pcr);
 909         source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
 910                         AT91_PMC_USB_USBS_MASK;
 911         usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
 912
 913         ret = clk_get_by_index(clk->dev, source_index, &source);
 914         if (ret)
 915                 return 0;
 916
 917         return clk_get_rate(&source) / (usbdiv + 1);
 918 }
 919
 920 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
 921 {
 922         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
 923         struct at91_pmc *pmc = plat->reg_base;
 924         struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
 925         struct clk source, best_source;
 926         ulong tmp_rate, best_rate = rate, source_rate;
 927         int tmp_diff, best_diff = -1;
 928         u32 div, best_div = 0;
 929         u8 best_source_index = 0;
 930         u8 i;
 931         u32 tmp;
 932         int ret;
 933
 934         for (i = 0; i < priv->num_clksource; i++) {
 935                 ret = clk_get_by_index(clk->dev, i, &source);
 936                 if (ret)
 937                         return ret;
 938
 939                 source_rate = clk_get_rate(&source);
 940                 if (IS_ERR_VALUE(source_rate))
 941                         return source_rate;
 942
 943                 for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
 944                         tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
 945                         tmp_diff = abs(rate - tmp_rate);
 946
 947                         if (best_diff < 0 || best_diff > tmp_diff) {
 948                                 best_rate = tmp_rate;
 949                                 best_diff = tmp_diff;
 950
 951                                 best_div = div - 1;
 952                                 best_source = source;
 953                                 best_source_index = i;
 954                         }
 955
 956                         if (!best_diff || tmp_rate < rate)
 957                                 break;
 958                 }
 959
 960                 if (!best_diff)
 961                         break;
 962         }
 963
 964         debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
 965               best_source.dev->name, best_rate, best_div);
 966
 967         ret = clk_enable(&best_source);
 968         if (ret)
 969                 return ret;
 970
 971         tmp = AT91_PMC_USB_USBS_(best_source_index) |
 972               AT91_PMC_USB_DIV_(best_div);
 973         writel(tmp, &pmc->usb);
 974
 975         return 0;
 976 }
 977
 978 static struct clk_ops at91_usb_clk_ops = {
 979         .get_rate = at91_usb_clk_get_rate,
 980         .set_rate = at91_usb_clk_set_rate,
 981 };
 982
 983 static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
 984 {
 985         struct at91_usb_clk_priv *priv = dev_get_priv(dev);
 986         u32 cells[AT91_USB_CLK_SOURCE_MAX];
 987         u32 num_clksource;
 988
 989         num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
 990                                                    dev_of_offset(dev),
 991                                                    "clocks", cells,
 992                                                    AT91_USB_CLK_SOURCE_MAX);
 993
 994         if (!num_clksource)
 995                 return -1;
 996
 997         priv->num_clksource = num_clksource;
 998
 999         return 0;
1000 }
1001
1002 static int at91_usb_clk_probe(struct udevice *dev)
1003 {
1004         return at91_pmc_core_probe(dev);
1005 }
1006
1007 static const struct udevice_id at91_usb_clk_match[] = {
1008         { .compatible = "atmel,at91sam9x5-clk-usb" },
1009         {}
1010 };
1011
1012 U_BOOT_DRIVER(at91_usb_clk) = {
1013         .name = "at91-usb-clk",
1014         .id = UCLASS_CLK,
1015         .of_match = at91_usb_clk_match,
1016         .probe = at91_usb_clk_probe,
1017         .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
1018         .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
1019         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
1020         .ops = &at91_usb_clk_ops,
1021 };
1022
1023 #endif /* CONFIG_AT91_USB_CLK */