1 // SPDX-License-Identifier: GPL-2.0+
3 * Compatible code for non CCF AT91 platforms.
5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
10 #include <clk-uclass.h>
12 #include <dm/device_compat.h>
15 #include <mach/at91_pmc.h>
16 #include <mach/at91_sfr.h>
22 DECLARE_GLOBAL_DATA_PTR;
25 struct at91_pmc *reg_base;
26 struct regmap *regmap_sfr;
29 static const struct udevice_id at91_pmc_match[] = {
30 { .compatible = "atmel,at91rm9200-pmc" },
31 { .compatible = "atmel,at91sam9260-pmc" },
32 { .compatible = "atmel,at91sam9g45-pmc" },
33 { .compatible = "atmel,at91sam9n12-pmc" },
34 { .compatible = "atmel,at91sam9x5-pmc" },
35 { .compatible = "atmel,sama5d3-pmc" },
36 { .compatible = "atmel,sama5d2-pmc" },
40 U_BOOT_DRIVER(at91_pmc) = {
42 .id = UCLASS_SIMPLE_BUS,
43 .of_match = at91_pmc_match,
46 static int at91_pmc_core_probe(struct udevice *dev)
48 struct pmc_platdata *plat = dev_get_plat(dev);
50 dev = dev_get_parent(dev);
52 plat->reg_base = dev_read_addr_ptr(dev);
58 * at91_clk_sub_device_bind() - for the at91 clock driver
59 * Recursively bind its children as clk devices.
61 * @return: 0 on success, or negative error code on failure
63 int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
65 ofnode parent = dev_ofnode(dev);
67 bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
71 ofnode_for_each_subnode(node, parent) {
72 if (pre_reloc_only && !ofnode_pre_reloc(node))
75 * If this node has "compatible" property, this is not
76 * a clock sub-node, but a normal device. skip.
78 if (ofnode_read_prop(node, "compatible", NULL))
81 if (ret != -FDT_ERR_NOTFOUND)
84 name = ofnode_get_name(node);
87 ret = device_bind_driver_to_node(dev, drv_name, name, node,
96 int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
100 if (args->args_count) {
101 debug("Invalid args_count: %d\n", args->args_count);
105 periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
115 int at91_clk_probe(struct udevice *dev)
117 struct udevice *dev_periph_container, *dev_pmc;
118 struct pmc_platdata *plat = dev_get_plat(dev);
120 dev_periph_container = dev_get_parent(dev);
121 dev_pmc = dev_get_parent(dev_periph_container);
123 plat->reg_base = dev_read_addr_ptr(dev_pmc);
128 /* SCKC specific code. */
129 static const struct udevice_id at91_sckc_match[] = {
130 { .compatible = "atmel,at91sam9x5-sckc" },
134 U_BOOT_DRIVER(at91_sckc) = {
136 .id = UCLASS_SIMPLE_BUS,
137 .of_match = at91_sckc_match,
140 /* Slow clock specific code. */
141 static int at91_slow_clk_enable(struct clk *clk)
146 static ulong at91_slow_clk_get_rate(struct clk *clk)
148 return CONFIG_SYS_AT91_SLOW_CLOCK;
151 static struct clk_ops at91_slow_clk_ops = {
152 .enable = at91_slow_clk_enable,
153 .get_rate = at91_slow_clk_get_rate,
156 static const struct udevice_id at91_slow_clk_match[] = {
157 { .compatible = "atmel,at91sam9x5-clk-slow" },
161 U_BOOT_DRIVER(at91_slow_clk) = {
162 .name = "at91-slow-clk",
164 .of_match = at91_slow_clk_match,
165 .ops = &at91_slow_clk_ops,
168 /* Master clock specific code. */
169 static ulong at91_master_clk_get_rate(struct clk *clk)
171 return gd->arch.mck_rate_hz;
174 static struct clk_ops at91_master_clk_ops = {
175 .get_rate = at91_master_clk_get_rate,
178 static const struct udevice_id at91_master_clk_match[] = {
179 { .compatible = "atmel,at91rm9200-clk-master" },
180 { .compatible = "atmel,at91sam9x5-clk-master" },
184 U_BOOT_DRIVER(at91_master_clk) = {
185 .name = "at91-master-clk",
187 .of_match = at91_master_clk_match,
188 .ops = &at91_master_clk_ops,
191 /* Main osc clock specific code. */
192 static int main_osc_clk_enable(struct clk *clk)
194 struct pmc_platdata *plat = dev_get_plat(clk->dev);
195 struct at91_pmc *pmc = plat->reg_base;
197 if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
203 static ulong main_osc_clk_get_rate(struct clk *clk)
205 return gd->arch.main_clk_rate_hz;
208 static struct clk_ops main_osc_clk_ops = {
209 .enable = main_osc_clk_enable,
210 .get_rate = main_osc_clk_get_rate,
213 static int main_osc_clk_probe(struct udevice *dev)
215 return at91_pmc_core_probe(dev);
218 static const struct udevice_id main_osc_clk_match[] = {
219 { .compatible = "atmel,at91sam9x5-clk-main" },
223 U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
224 .name = "at91sam9x5-main-osc-clk",
226 .of_match = main_osc_clk_match,
227 .probe = main_osc_clk_probe,
228 .plat_auto = sizeof(struct pmc_platdata),
229 .ops = &main_osc_clk_ops,
232 /* PLLA clock specific code. */
233 static int plla_clk_enable(struct clk *clk)
235 struct pmc_platdata *plat = dev_get_plat(clk->dev);
236 struct at91_pmc *pmc = plat->reg_base;
238 if (readl(&pmc->sr) & AT91_PMC_LOCKA)
244 static ulong plla_clk_get_rate(struct clk *clk)
246 return gd->arch.plla_rate_hz;
249 static struct clk_ops plla_clk_ops = {
250 .enable = plla_clk_enable,
251 .get_rate = plla_clk_get_rate,
254 static int plla_clk_probe(struct udevice *dev)
256 return at91_pmc_core_probe(dev);
259 static const struct udevice_id plla_clk_match[] = {
260 { .compatible = "atmel,sama5d3-clk-pll" },
264 U_BOOT_DRIVER(at91_plla_clk) = {
265 .name = "at91-plla-clk",
267 .of_match = plla_clk_match,
268 .probe = plla_clk_probe,
269 .plat_auto = sizeof(struct pmc_platdata),
270 .ops = &plla_clk_ops,
273 /* PLLA DIV clock specific code. */
274 static int at91_plladiv_clk_enable(struct clk *clk)
279 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
281 struct pmc_platdata *plat = dev_get_plat(clk->dev);
282 struct at91_pmc *pmc = plat->reg_base;
287 ret = clk_get_by_index(clk->dev, 0, &source);
291 clk_rate = clk_get_rate(&source);
292 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
298 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
300 struct pmc_platdata *plat = dev_get_plat(clk->dev);
301 struct at91_pmc *pmc = plat->reg_base;
306 ret = clk_get_by_index(clk->dev, 0, &source);
310 parent_rate = clk_get_rate(&source);
311 if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
314 if (parent_rate != rate) {
315 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
322 static struct clk_ops at91_plladiv_clk_ops = {
323 .enable = at91_plladiv_clk_enable,
324 .get_rate = at91_plladiv_clk_get_rate,
325 .set_rate = at91_plladiv_clk_set_rate,
328 static int at91_plladiv_clk_probe(struct udevice *dev)
330 return at91_pmc_core_probe(dev);
333 static const struct udevice_id at91_plladiv_clk_match[] = {
334 { .compatible = "atmel,at91sam9x5-clk-plldiv" },
338 U_BOOT_DRIVER(at91_plladiv_clk) = {
339 .name = "at91-plladiv-clk",
341 .of_match = at91_plladiv_clk_match,
342 .probe = at91_plladiv_clk_probe,
343 .plat_auto = sizeof(struct pmc_platdata),
344 .ops = &at91_plladiv_clk_ops,
347 /* System clock specific code. */
348 #define SYSTEM_MAX_ID 31
351 * at91_system_clk_bind() - for the system clock driver
352 * Recursively bind its children as clk devices.
354 * @return: 0 on success, or negative error code on failure
356 static int at91_system_clk_bind(struct udevice *dev)
358 return at91_clk_sub_device_bind(dev, "system-clk");
361 static const struct udevice_id at91_system_clk_match[] = {
362 { .compatible = "atmel,at91rm9200-clk-system" },
366 U_BOOT_DRIVER(at91_system_clk) = {
367 .name = "at91-system-clk",
369 .of_match = at91_system_clk_match,
370 .bind = at91_system_clk_bind,
373 static inline int is_pck(int id)
375 return (id >= 8) && (id <= 15);
378 static ulong system_clk_get_rate(struct clk *clk)
383 ret = clk_get_by_index(clk->dev, 0, &clk_dev);
387 return clk_get_rate(&clk_dev);
390 static ulong system_clk_set_rate(struct clk *clk, ulong rate)
395 ret = clk_get_by_index(clk->dev, 0, &clk_dev);
399 return clk_set_rate(&clk_dev, rate);
402 static int system_clk_enable(struct clk *clk)
404 struct pmc_platdata *plat = dev_get_plat(clk->dev);
405 struct at91_pmc *pmc = plat->reg_base;
408 if (clk->id > SYSTEM_MAX_ID)
413 writel(mask, &pmc->scer);
416 * For the programmable clocks the Ready status in the PMC
417 * status register should be checked after enabling.
418 * For other clocks this is unnecessary.
420 if (!is_pck(clk->id))
423 while (!(readl(&pmc->sr) & mask))
429 static struct clk_ops system_clk_ops = {
430 .of_xlate = at91_clk_of_xlate,
431 .get_rate = system_clk_get_rate,
432 .set_rate = system_clk_set_rate,
433 .enable = system_clk_enable,
436 U_BOOT_DRIVER(system_clk) = {
437 .name = "system-clk",
439 .probe = at91_clk_probe,
440 .plat_auto = sizeof(struct pmc_platdata),
441 .ops = &system_clk_ops,
444 /* Peripheral clock specific code. */
445 #define PERIPHERAL_ID_MIN 2
446 #define PERIPHERAL_ID_MAX 31
447 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
449 enum periph_clk_type {
450 CLK_PERIPH_AT91RM9200 = 0,
451 CLK_PERIPH_AT91SAM9X5,
455 * sam9x5_periph_clk_bind() - for the periph clock driver
456 * Recursively bind its children as clk devices.
458 * @return: 0 on success, or negative error code on failure
460 static int sam9x5_periph_clk_bind(struct udevice *dev)
462 return at91_clk_sub_device_bind(dev, "periph-clk");
465 static const struct udevice_id sam9x5_periph_clk_match[] = {
467 .compatible = "atmel,at91rm9200-clk-peripheral",
468 .data = CLK_PERIPH_AT91RM9200,
471 .compatible = "atmel,at91sam9x5-clk-peripheral",
472 .data = CLK_PERIPH_AT91SAM9X5,
477 U_BOOT_DRIVER(sam9x5_periph_clk) = {
478 .name = "sam9x5-periph-clk",
480 .of_match = sam9x5_periph_clk_match,
481 .bind = sam9x5_periph_clk_bind,
484 static int periph_clk_enable(struct clk *clk)
486 struct pmc_platdata *plat = dev_get_plat(clk->dev);
487 struct at91_pmc *pmc = plat->reg_base;
488 enum periph_clk_type clk_type;
491 if (clk->id < PERIPHERAL_ID_MIN)
494 clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
495 if (clk_type == CLK_PERIPH_AT91RM9200) {
497 if (clk->id > PERIPHERAL_ID_MAX)
500 setbits_le32(addr, PERIPHERAL_MASK(clk->id));
502 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
503 setbits_le32(&pmc->pcr,
504 AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
510 static ulong periph_get_rate(struct clk *clk)
517 dev = dev_get_parent(clk->dev);
519 ret = clk_get_by_index(dev, 0, &clk_dev);
523 clk_rate = clk_get_rate(&clk_dev);
530 static struct clk_ops periph_clk_ops = {
531 .of_xlate = at91_clk_of_xlate,
532 .enable = periph_clk_enable,
533 .get_rate = periph_get_rate,
536 U_BOOT_DRIVER(clk_periph) = {
537 .name = "periph-clk",
539 .plat_auto = sizeof(struct pmc_platdata),
540 .probe = at91_clk_probe,
541 .ops = &periph_clk_ops,
544 /* UTMI clock specific code. */
545 #ifdef CONFIG_AT91_UTMI
548 * The purpose of this clock is to generate a 480 MHz signal. A different
549 * rate can't be configured.
551 #define UTMI_RATE 480000000
553 static int utmi_clk_enable(struct clk *clk)
555 struct pmc_platdata *plat = dev_get_plat(clk->dev);
556 struct at91_pmc *pmc = plat->reg_base;
559 u32 utmi_ref_clk_freq;
562 int timeout = 2000000;
564 if (readl(&pmc->sr) & AT91_PMC_LOCKU)
568 * If mainck rate is different from 12 MHz, we have to configure the
569 * FREQ field of the SFR_UTMICKTRIM register to generate properly
572 err = clk_get_by_index(clk->dev, 0, &clk_dev);
576 clk_rate = clk_get_rate(&clk_dev);
579 utmi_ref_clk_freq = 0;
582 utmi_ref_clk_freq = 1;
585 utmi_ref_clk_freq = 2;
588 * Not supported on SAMA5D2 but it's not an issue since MAINCK
589 * maximum value is 24 MHz.
592 utmi_ref_clk_freq = 3;
595 printf("UTMICK: unsupported mainck rate\n");
599 if (plat->regmap_sfr) {
600 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
604 tmp &= ~AT91_UTMICKTRIM_FREQ;
605 tmp |= utmi_ref_clk_freq;
606 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
609 } else if (utmi_ref_clk_freq) {
610 printf("UTMICK: sfr node required\n");
614 tmp = readl(&pmc->uckr);
615 tmp |= AT91_PMC_UPLLEN |
618 writel(tmp, &pmc->uckr);
620 while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
623 printf("UTMICK: timeout waiting for UPLL lock\n");
630 static ulong utmi_clk_get_rate(struct clk *clk)
632 /* UTMI clk rate is fixed. */
636 static struct clk_ops utmi_clk_ops = {
637 .enable = utmi_clk_enable,
638 .get_rate = utmi_clk_get_rate,
641 static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
643 struct pmc_platdata *plat = dev_get_plat(dev);
644 struct udevice *syscon;
646 uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
647 "regmap-sfr", &syscon);
650 plat->regmap_sfr = syscon_get_regmap(syscon);
655 static int utmi_clk_probe(struct udevice *dev)
657 return at91_pmc_core_probe(dev);
660 static const struct udevice_id utmi_clk_match[] = {
661 { .compatible = "atmel,at91sam9x5-clk-utmi" },
665 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
666 .name = "at91sam9x5-utmi-clk",
668 .of_match = utmi_clk_match,
669 .probe = utmi_clk_probe,
670 .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
671 .plat_auto = sizeof(struct pmc_platdata),
672 .ops = &utmi_clk_ops,
675 #endif /* CONFIG_AT91_UTMI */
677 /* H32MX clock specific code. */
678 #ifdef CONFIG_AT91_H32MX
680 #define H32MX_MAX_FREQ 90000000
682 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
684 struct pmc_platdata *plat = dev_get_plat(clk->dev);
685 struct at91_pmc *pmc = plat->reg_base;
686 ulong rate = gd->arch.mck_rate_hz;
688 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
691 if (rate > H32MX_MAX_FREQ)
692 dev_dbg(clk->dev, "H32MX clock is too fast\n");
697 static struct clk_ops sama5d4_h32mx_clk_ops = {
698 .get_rate = sama5d4_h32mx_clk_get_rate,
701 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
703 return at91_pmc_core_probe(dev);
706 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
707 { .compatible = "atmel,sama5d4-clk-h32mx" },
711 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
712 .name = "sama5d4-h32mx-clk",
714 .of_match = sama5d4_h32mx_clk_match,
715 .probe = sama5d4_h32mx_clk_probe,
716 .plat_auto = sizeof(struct pmc_platdata),
717 .ops = &sama5d4_h32mx_clk_ops,
720 #endif /* CONFIG_AT91_H32MX */
722 /* Generic clock specific code. */
723 #ifdef CONFIG_AT91_GENERIC_CLK
725 #define GENERATED_SOURCE_MAX 6
726 #define GENERATED_MAX_DIV 255
729 * generated_clk_bind() - for the generated clock driver
730 * Recursively bind its children as clk devices.
732 * @return: 0 on success, or negative error code on failure
734 static int generated_clk_bind(struct udevice *dev)
736 return at91_clk_sub_device_bind(dev, "generic-clk");
739 static const struct udevice_id generated_clk_match[] = {
740 { .compatible = "atmel,sama5d2-clk-generated" },
744 U_BOOT_DRIVER(generated_clk) = {
745 .name = "generated-clk",
747 .of_match = generated_clk_match,
748 .bind = generated_clk_bind,
751 struct generic_clk_priv {
755 static ulong generic_clk_get_rate(struct clk *clk)
757 struct pmc_platdata *plat = dev_get_plat(clk->dev);
758 struct at91_pmc *pmc = plat->reg_base;
762 u8 clock_source, parent_index;
765 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
766 tmp = readl(&pmc->pcr);
767 clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
768 AT91_PMC_PCR_GCKCSS_MASK;
769 gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
771 parent_index = clock_source - 1;
772 ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
776 clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
783 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
785 struct pmc_platdata *plat = dev_get_plat(clk->dev);
786 struct at91_pmc *pmc = plat->reg_base;
787 struct generic_clk_priv *priv = dev_get_priv(clk->dev);
788 struct clk parent, best_parent;
789 ulong tmp_rate, best_rate = rate, parent_rate;
790 int tmp_diff, best_diff = -1;
791 u32 div, best_div = 0;
792 u8 best_parent_index, best_clock_source = 0;
797 for (i = 0; i < priv->num_parents; i++) {
798 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
802 parent_rate = clk_get_rate(&parent);
803 if (IS_ERR_VALUE(parent_rate))
806 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
807 tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
808 tmp_diff = abs(rate - tmp_rate);
810 if (best_diff < 0 || best_diff > tmp_diff) {
811 best_rate = tmp_rate;
812 best_diff = tmp_diff;
815 best_parent = parent;
816 best_parent_index = i;
817 best_clock_source = best_parent_index + 1;
820 if (!best_diff || tmp_rate < rate)
828 debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
829 best_parent.dev->name, best_rate, best_div);
831 ret = clk_enable(&best_parent);
835 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
836 tmp = readl(&pmc->pcr);
837 tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
838 tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
839 AT91_PMC_PCR_CMD_WRITE |
840 AT91_PMC_PCR_GCKDIV_(best_div) |
842 writel(tmp, &pmc->pcr);
844 while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
850 static struct clk_ops generic_clk_ops = {
851 .of_xlate = at91_clk_of_xlate,
852 .get_rate = generic_clk_get_rate,
853 .set_rate = generic_clk_set_rate,
856 static int generic_clk_ofdata_to_platdata(struct udevice *dev)
858 struct generic_clk_priv *priv = dev_get_priv(dev);
859 u32 cells[GENERATED_SOURCE_MAX];
862 num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
863 dev_of_offset(dev_get_parent(dev)), "clocks", cells,
864 GENERATED_SOURCE_MAX);
869 priv->num_parents = num_parents;
874 U_BOOT_DRIVER(generic_clk) = {
875 .name = "generic-clk",
877 .probe = at91_clk_probe,
878 .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
879 .priv_auto = sizeof(struct generic_clk_priv),
880 .plat_auto = sizeof(struct pmc_platdata),
881 .ops = &generic_clk_ops,
884 #endif /* CONFIG_AT91_GENERIC_CLK */
886 /* USB clock specific code. */
887 #ifdef CONFIG_AT91_USB_CLK
889 #define AT91_USB_CLK_SOURCE_MAX 2
890 #define AT91_USB_CLK_MAX_DIV 15
892 struct at91_usb_clk_priv {
896 static ulong at91_usb_clk_get_rate(struct clk *clk)
898 struct pmc_platdata *plat = dev_get_plat(clk->dev);
899 struct at91_pmc *pmc = plat->reg_base;
905 tmp = readl(&pmc->pcr);
906 source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
907 AT91_PMC_USB_USBS_MASK;
908 usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
910 ret = clk_get_by_index(clk->dev, source_index, &source);
914 return clk_get_rate(&source) / (usbdiv + 1);
917 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
919 struct pmc_platdata *plat = dev_get_plat(clk->dev);
920 struct at91_pmc *pmc = plat->reg_base;
921 struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
922 struct clk source, best_source;
923 ulong tmp_rate, best_rate = rate, source_rate;
924 int tmp_diff, best_diff = -1;
925 u32 div, best_div = 0;
926 u8 best_source_index = 0;
931 for (i = 0; i < priv->num_clksource; i++) {
932 ret = clk_get_by_index(clk->dev, i, &source);
936 source_rate = clk_get_rate(&source);
937 if (IS_ERR_VALUE(source_rate))
940 for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
941 tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
942 tmp_diff = abs(rate - tmp_rate);
944 if (best_diff < 0 || best_diff > tmp_diff) {
945 best_rate = tmp_rate;
946 best_diff = tmp_diff;
949 best_source = source;
950 best_source_index = i;
953 if (!best_diff || tmp_rate < rate)
961 debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
962 best_source.dev->name, best_rate, best_div);
964 ret = clk_enable(&best_source);
968 tmp = AT91_PMC_USB_USBS_(best_source_index) |
969 AT91_PMC_USB_DIV_(best_div);
970 writel(tmp, &pmc->usb);
975 static struct clk_ops at91_usb_clk_ops = {
976 .get_rate = at91_usb_clk_get_rate,
977 .set_rate = at91_usb_clk_set_rate,
980 static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
982 struct at91_usb_clk_priv *priv = dev_get_priv(dev);
983 u32 cells[AT91_USB_CLK_SOURCE_MAX];
986 num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
989 AT91_USB_CLK_SOURCE_MAX);
994 priv->num_clksource = num_clksource;
999 static int at91_usb_clk_probe(struct udevice *dev)
1001 return at91_pmc_core_probe(dev);
1004 static const struct udevice_id at91_usb_clk_match[] = {
1005 { .compatible = "atmel,at91sam9x5-clk-usb" },
1009 U_BOOT_DRIVER(at91_usb_clk) = {
1010 .name = "at91-usb-clk",
1012 .of_match = at91_usb_clk_match,
1013 .probe = at91_usb_clk_probe,
1014 .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
1015 .priv_auto = sizeof(struct at91_usb_clk_priv),
1016 .plat_auto = sizeof(struct pmc_platdata),
1017 .ops = &at91_usb_clk_ops,
1020 #endif /* CONFIG_AT91_USB_CLK */