1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Microchip Technology Inc.
7 #include <linux/bitfield.h>
9 #include <linux/clk-provider.h>
10 #include <linux/clkdev.h>
11 #include <linux/clk/at91_pmc.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/regmap.h>
18 #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
19 #define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
20 #define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
22 #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
24 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
26 #define FCORE_MIN (600000000)
27 #define FCORE_MAX (1200000000)
31 struct sam9x60_pll_core {
32 struct regmap *regmap;
34 const struct clk_pll_characteristics *characteristics;
35 const struct clk_pll_layout *layout;
41 struct sam9x60_pll_core core;
42 struct at91_clk_pms pms;
48 struct sam9x60_pll_core core;
49 struct at91_clk_pms pms;
54 #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
55 #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
56 #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
58 static struct sam9x60_div *notifier_div;
60 static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
64 regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
66 return !!(status & BIT(id));
69 static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
71 return sam9x60_pll_ready(regmap, id);
74 static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
75 unsigned long parent_rate)
77 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
78 struct sam9x60_frac *frac = to_sam9x60_frac(core);
80 return parent_rate * (frac->mul + 1) +
81 DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
84 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
86 struct sam9x60_frac *frac = to_sam9x60_frac(core);
87 struct regmap *regmap = core->regmap;
88 unsigned int val, cfrac, cmul;
91 spin_lock_irqsave(core->lock, flags);
93 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
94 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
95 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
96 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
97 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
99 if (sam9x60_frac_pll_ready(regmap, core->id) &&
100 (cmul == frac->mul && cfrac == frac->frac))
103 /* Recommended value for PMC_PLL_ACR */
104 if (core->characteristics->upll)
105 val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
107 val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
108 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
110 regmap_write(regmap, AT91_PMC_PLL_CTRL1,
111 (frac->mul << core->layout->mul_shift) |
112 (frac->frac << core->layout->frac_shift));
114 if (core->characteristics->upll) {
115 /* Enable the UTMI internal bandgap */
116 val |= AT91_PMC_PLL_ACR_UTMIBG;
117 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
121 /* Enable the UTMI internal regulator */
122 val |= AT91_PMC_PLL_ACR_UTMIVR;
123 regmap_write(regmap, AT91_PMC_PLL_ACR, val);
128 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
129 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
130 AT91_PMC_PLL_UPDT_UPDATE | core->id);
132 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
133 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
134 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
136 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
137 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
138 AT91_PMC_PLL_UPDT_UPDATE | core->id);
140 while (!sam9x60_pll_ready(regmap, core->id))
144 spin_unlock_irqrestore(core->lock, flags);
149 static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
151 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
153 return sam9x60_frac_pll_set(core);
156 static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
158 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
159 struct regmap *regmap = core->regmap;
162 spin_lock_irqsave(core->lock, flags);
164 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
165 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
167 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
169 if (core->characteristics->upll)
170 regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
171 AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
173 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
174 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
175 AT91_PMC_PLL_UPDT_UPDATE | core->id);
177 spin_unlock_irqrestore(core->lock, flags);
180 static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw)
182 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
184 return sam9x60_pll_ready(core->regmap, core->id);
187 static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
189 unsigned long parent_rate,
192 struct sam9x60_frac *frac = to_sam9x60_frac(core);
193 unsigned long tmprate, remainder;
194 unsigned long nmul = 0;
195 unsigned long nfrac = 0;
197 if (rate < FCORE_MIN || rate > FCORE_MAX)
201 * Calculate the multiplier associated with the current
202 * divider that provide the closest rate to the requested one.
204 nmul = mult_frac(rate, 1, parent_rate);
205 tmprate = mult_frac(parent_rate, nmul, 1);
206 remainder = rate - tmprate;
209 nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
212 tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
216 /* Check if resulted rate is a valid. */
217 if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
221 frac->mul = nmul - 1;
228 static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
229 unsigned long *parent_rate)
231 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
233 return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
236 static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
237 unsigned long parent_rate)
239 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
241 return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
244 static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
245 unsigned long parent_rate)
247 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
248 struct sam9x60_frac *frac = to_sam9x60_frac(core);
249 struct regmap *regmap = core->regmap;
250 unsigned long irqflags;
251 unsigned int val, cfrac, cmul;
254 ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
258 spin_lock_irqsave(core->lock, irqflags);
260 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
262 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
263 cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
264 cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
266 if (cmul == frac->mul && cfrac == frac->frac)
269 regmap_write(regmap, AT91_PMC_PLL_CTRL1,
270 (frac->mul << core->layout->mul_shift) |
271 (frac->frac << core->layout->frac_shift));
273 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
274 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
275 AT91_PMC_PLL_UPDT_UPDATE | core->id);
277 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
278 AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
279 AT91_PMC_PLL_CTRL0_ENLOCK |
280 AT91_PMC_PLL_CTRL0_ENPLL);
282 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
283 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
284 AT91_PMC_PLL_UPDT_UPDATE | core->id);
286 while (!sam9x60_pll_ready(regmap, core->id))
290 spin_unlock_irqrestore(core->lock, irqflags);
295 static int sam9x60_frac_pll_save_context(struct clk_hw *hw)
297 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
298 struct sam9x60_frac *frac = to_sam9x60_frac(core);
300 frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);
305 static void sam9x60_frac_pll_restore_context(struct clk_hw *hw)
307 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
308 struct sam9x60_frac *frac = to_sam9x60_frac(core);
310 if (frac->pms.status)
311 sam9x60_frac_pll_set(core);
314 static const struct clk_ops sam9x60_frac_pll_ops = {
315 .prepare = sam9x60_frac_pll_prepare,
316 .unprepare = sam9x60_frac_pll_unprepare,
317 .is_prepared = sam9x60_frac_pll_is_prepared,
318 .recalc_rate = sam9x60_frac_pll_recalc_rate,
319 .round_rate = sam9x60_frac_pll_round_rate,
320 .set_rate = sam9x60_frac_pll_set_rate,
321 .save_context = sam9x60_frac_pll_save_context,
322 .restore_context = sam9x60_frac_pll_restore_context,
325 static const struct clk_ops sam9x60_frac_pll_ops_chg = {
326 .prepare = sam9x60_frac_pll_prepare,
327 .unprepare = sam9x60_frac_pll_unprepare,
328 .is_prepared = sam9x60_frac_pll_is_prepared,
329 .recalc_rate = sam9x60_frac_pll_recalc_rate,
330 .round_rate = sam9x60_frac_pll_round_rate,
331 .set_rate = sam9x60_frac_pll_set_rate_chg,
332 .save_context = sam9x60_frac_pll_save_context,
333 .restore_context = sam9x60_frac_pll_restore_context,
336 /* This function should be called with spinlock acquired. */
337 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
340 struct regmap *regmap = core->regmap;
341 u32 ena_msk = enable ? core->layout->endiv_mask : 0;
342 u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
344 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
345 core->layout->div_mask | ena_msk,
346 (div << core->layout->div_shift) | ena_val);
348 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
349 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
350 AT91_PMC_PLL_UPDT_UPDATE | core->id);
352 while (!sam9x60_pll_ready(regmap, core->id))
356 static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
358 struct sam9x60_div *div = to_sam9x60_div(core);
359 struct regmap *regmap = core->regmap;
361 unsigned int val, cdiv;
363 spin_lock_irqsave(core->lock, flags);
364 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
365 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
366 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
369 /* Stop if enabled an nothing changed. */
370 if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
373 sam9x60_div_pll_set_div(core, div->div, 1);
376 spin_unlock_irqrestore(core->lock, flags);
381 static int sam9x60_div_pll_prepare(struct clk_hw *hw)
383 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
385 return sam9x60_div_pll_set(core);
388 static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
390 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
391 struct regmap *regmap = core->regmap;
394 spin_lock_irqsave(core->lock, flags);
396 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
397 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
399 regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
400 core->layout->endiv_mask, 0);
402 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
403 AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
404 AT91_PMC_PLL_UPDT_UPDATE | core->id);
406 spin_unlock_irqrestore(core->lock, flags);
409 static int sam9x60_div_pll_is_prepared(struct clk_hw *hw)
411 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
412 struct regmap *regmap = core->regmap;
416 spin_lock_irqsave(core->lock, flags);
418 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
419 AT91_PMC_PLL_UPDT_ID_MSK, core->id);
420 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
422 spin_unlock_irqrestore(core->lock, flags);
424 return !!(val & core->layout->endiv_mask);
427 static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
428 unsigned long parent_rate)
430 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
431 struct sam9x60_div *div = to_sam9x60_div(core);
433 return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
436 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
437 unsigned long *parent_rate,
440 const struct clk_pll_characteristics *characteristics =
441 core->characteristics;
442 struct clk_hw *parent = clk_hw_get_parent(&core->hw);
443 unsigned long tmp_rate, tmp_parent_rate, tmp_diff;
444 long best_diff = -1, best_rate = -EINVAL;
450 if (rate < characteristics->output[0].min ||
451 rate > characteristics->output[0].max)
454 for (divid = 1; divid < core->layout->div_mask; divid++) {
455 tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
456 if (!tmp_parent_rate)
459 tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid);
460 tmp_diff = abs(rate - tmp_rate);
462 if (best_diff < 0 || best_diff > tmp_diff) {
463 *parent_rate = tmp_parent_rate;
464 best_rate = tmp_rate;
465 best_diff = tmp_diff;
472 if (best_rate < characteristics->output[0].min ||
473 best_rate > characteristics->output[0].max)
479 static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
480 unsigned long *parent_rate)
482 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
484 return sam9x60_div_pll_compute_div(core, parent_rate, rate);
487 static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
488 unsigned long parent_rate)
490 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
491 struct sam9x60_div *div = to_sam9x60_div(core);
493 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
498 static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
499 unsigned long parent_rate)
501 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
502 struct sam9x60_div *div = to_sam9x60_div(core);
503 struct regmap *regmap = core->regmap;
504 unsigned long irqflags;
505 unsigned int val, cdiv;
507 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
509 spin_lock_irqsave(core->lock, irqflags);
510 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
512 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
515 /* Stop if nothing changed. */
516 if (cdiv == div->div)
519 sam9x60_div_pll_set_div(core, div->div, 0);
522 spin_unlock_irqrestore(core->lock, irqflags);
527 static int sam9x60_div_pll_save_context(struct clk_hw *hw)
529 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
530 struct sam9x60_div *div = to_sam9x60_div(core);
532 div->pms.status = sam9x60_div_pll_is_prepared(hw);
537 static void sam9x60_div_pll_restore_context(struct clk_hw *hw)
539 struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
540 struct sam9x60_div *div = to_sam9x60_div(core);
543 sam9x60_div_pll_set(core);
546 static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
547 unsigned long code, void *data)
549 struct sam9x60_div *div = notifier_div;
550 struct sam9x60_pll_core core = div->core;
551 struct regmap *regmap = core.regmap;
552 unsigned long irqflags;
554 int ret = NOTIFY_DONE;
556 if (code != PRE_RATE_CHANGE)
560 * We switch to safe divider to avoid overclocking of other domains
561 * feed by us while the frac PLL (our parent) is changed.
563 div->div = div->safe_div;
565 spin_lock_irqsave(core.lock, irqflags);
566 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
568 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
571 /* Stop if nothing changed. */
572 if (cdiv == div->safe_div)
575 sam9x60_div_pll_set_div(&core, div->div, 0);
579 spin_unlock_irqrestore(core.lock, irqflags);
584 static struct notifier_block sam9x60_div_pll_notifier = {
585 .notifier_call = sam9x60_div_pll_notifier_fn,
588 static const struct clk_ops sam9x60_div_pll_ops = {
589 .prepare = sam9x60_div_pll_prepare,
590 .unprepare = sam9x60_div_pll_unprepare,
591 .is_prepared = sam9x60_div_pll_is_prepared,
592 .recalc_rate = sam9x60_div_pll_recalc_rate,
593 .round_rate = sam9x60_div_pll_round_rate,
594 .set_rate = sam9x60_div_pll_set_rate,
595 .save_context = sam9x60_div_pll_save_context,
596 .restore_context = sam9x60_div_pll_restore_context,
599 static const struct clk_ops sam9x60_div_pll_ops_chg = {
600 .prepare = sam9x60_div_pll_prepare,
601 .unprepare = sam9x60_div_pll_unprepare,
602 .is_prepared = sam9x60_div_pll_is_prepared,
603 .recalc_rate = sam9x60_div_pll_recalc_rate,
604 .round_rate = sam9x60_div_pll_round_rate,
605 .set_rate = sam9x60_div_pll_set_rate_chg,
606 .save_context = sam9x60_div_pll_save_context,
607 .restore_context = sam9x60_div_pll_restore_context,
610 struct clk_hw * __init
611 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
612 const char *name, const char *parent_name,
613 struct clk_hw *parent_hw, u8 id,
614 const struct clk_pll_characteristics *characteristics,
615 const struct clk_pll_layout *layout, u32 flags)
617 struct sam9x60_frac *frac;
619 struct clk_init_data init;
620 unsigned long parent_rate, irqflags;
624 if (id > PLL_MAX_ID || !lock || !parent_hw)
625 return ERR_PTR(-EINVAL);
627 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
629 return ERR_PTR(-ENOMEM);
632 init.parent_names = &parent_name;
633 init.num_parents = 1;
634 if (flags & CLK_SET_RATE_GATE)
635 init.ops = &sam9x60_frac_pll_ops;
637 init.ops = &sam9x60_frac_pll_ops_chg;
642 frac->core.hw.init = &init;
643 frac->core.characteristics = characteristics;
644 frac->core.layout = layout;
645 frac->core.regmap = regmap;
646 frac->core.lock = lock;
648 spin_lock_irqsave(frac->core.lock, irqflags);
649 if (sam9x60_pll_ready(regmap, id)) {
650 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
651 AT91_PMC_PLL_UPDT_ID_MSK, id);
652 regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
653 frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
654 frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
657 * This means the PLL is not setup by bootloaders. In this
658 * case we need to set the minimum rate for it. Otherwise
659 * a clock child of this PLL may be enabled before setting
660 * its rate leading to enabling this PLL with unsupported
661 * rate. This will lead to PLL not being locked at all.
663 parent_rate = clk_hw_get_rate(parent_hw);
665 hw = ERR_PTR(-EINVAL);
669 ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
676 spin_unlock_irqrestore(frac->core.lock, irqflags);
679 ret = clk_hw_register(NULL, hw);
688 spin_unlock_irqrestore(frac->core.lock, irqflags);
693 struct clk_hw * __init
694 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
695 const char *name, const char *parent_name, u8 id,
696 const struct clk_pll_characteristics *characteristics,
697 const struct clk_pll_layout *layout, u32 flags,
700 struct sam9x60_div *div;
702 struct clk_init_data init;
703 unsigned long irqflags;
707 /* We only support one changeable PLL. */
708 if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))
709 return ERR_PTR(-EINVAL);
711 if (safe_div >= PLL_DIV_MAX)
712 safe_div = PLL_DIV_MAX - 1;
714 div = kzalloc(sizeof(*div), GFP_KERNEL);
716 return ERR_PTR(-ENOMEM);
719 init.parent_names = &parent_name;
720 init.num_parents = 1;
721 if (flags & CLK_SET_RATE_GATE)
722 init.ops = &sam9x60_div_pll_ops;
724 init.ops = &sam9x60_div_pll_ops_chg;
728 div->core.hw.init = &init;
729 div->core.characteristics = characteristics;
730 div->core.layout = layout;
731 div->core.regmap = regmap;
732 div->core.lock = lock;
733 div->safe_div = safe_div;
735 spin_lock_irqsave(div->core.lock, irqflags);
737 regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
738 AT91_PMC_PLL_UPDT_ID_MSK, id);
739 regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
740 div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
742 spin_unlock_irqrestore(div->core.lock, irqflags);
745 ret = clk_hw_register(NULL, hw);
749 } else if (div->safe_div) {
751 clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);