1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
8 #include <clk-uclass.h>
10 #include <dm/device_compat.h>
13 #include <mach/at91_pmc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #define H32MX_MAX_FREQ 90000000
20 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
22 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
23 struct at91_pmc *pmc = plat->reg_base;
24 ulong rate = gd->arch.mck_rate_hz;
26 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
29 if (rate > H32MX_MAX_FREQ)
30 dev_dbg(clk->dev, "H32MX clock is too fast\n");
35 static struct clk_ops sama5d4_h32mx_clk_ops = {
36 .get_rate = sama5d4_h32mx_clk_get_rate,
39 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
41 return at91_pmc_core_probe(dev);
44 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
45 { .compatible = "atmel,sama5d4-clk-h32mx" },
49 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
50 .name = "sama5d4-h32mx-clk",
52 .of_match = sama5d4_h32mx_clk_match,
53 .probe = sama5d4_h32mx_clk_probe,
54 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
55 .ops = &sama5d4_h32mx_clk_ops,