drivers/clk/at91/clk-generated.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Atmel Corporation
   4  *               Wenyou.Yang <wenyou.yang@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <malloc.h>
  11 #include <linux/err.h>
  12 #include <linux/io.h>
  13 #include <mach/at91_pmc.h>
  14 #include "pmc.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 #define GENERATED_SOURCE_MAX    6
  19 #define GENERATED_MAX_DIV       255
  20
  21 /**
  22  * generated_clk_bind() - for the generated clock driver
  23  * Recursively bind its children as clk devices.
  24  *
  25  * @return: 0 on success, or negative error code on failure
  26  */
  27 static int generated_clk_bind(struct udevice *dev)
  28 {
  29         return at91_clk_sub_device_bind(dev, "generic-clk");
  30 }
  31
  32 static const struct udevice_id generated_clk_match[] = {
  33         { .compatible = "atmel,sama5d2-clk-generated" },
  34         {}
  35 };
  36
  37 U_BOOT_DRIVER(generated_clk) = {
  38         .name = "generated-clk",
  39         .id = UCLASS_MISC,
  40         .of_match = generated_clk_match,
  41         .bind = generated_clk_bind,
  42 };
  43
  44 /*-------------------------------------------------------------*/
  45
  46 struct generic_clk_priv {
  47         u32 num_parents;
  48 };
  49
  50 static ulong generic_clk_get_rate(struct clk *clk)
  51 {
  52         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  53         struct at91_pmc *pmc = plat->reg_base;
  54         struct clk parent;
  55         ulong clk_rate;
  56         u32 tmp, gckdiv;
  57         u8 clock_source, parent_index;
  58         int ret;
  59
  60         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  61         tmp = readl(&pmc->pcr);
  62         clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
  63                     AT91_PMC_PCR_GCKCSS_MASK;
  64         gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
  65
  66         parent_index = clock_source - 1;
  67         ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
  68         if (ret)
  69                 return 0;
  70
  71         clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
  72
  73         clk_free(&parent);
  74
  75         return clk_rate;
  76 }
  77
  78 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
  79 {
  80         struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  81         struct at91_pmc *pmc = plat->reg_base;
  82         struct generic_clk_priv *priv = dev_get_priv(clk->dev);
  83         struct clk parent, best_parent;
  84         ulong tmp_rate, best_rate = rate, parent_rate;
  85         int tmp_diff, best_diff = -1;
  86         u32 div, best_div = 0;
  87         u8 best_parent_index, best_clock_source = 0;
  88         u8 i;
  89         u32 tmp;
  90         int ret;
  91
  92         for (i = 0; i < priv->num_parents; i++) {
  93                 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
  94                 if (ret)
  95                         return ret;
  96
  97                 parent_rate = clk_get_rate(&parent);
  98                 if (IS_ERR_VALUE(parent_rate))
  99                         return parent_rate;
 100
 101                 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
 102                         tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
 103                         tmp_diff = abs(rate - tmp_rate);
 104
 105                         if (best_diff < 0 || best_diff > tmp_diff) {
 106                                 best_rate = tmp_rate;
 107                                 best_diff = tmp_diff;
 108
 109                                 best_div = div - 1;
 110                                 best_parent = parent;
 111                                 best_parent_index = i;
 112                                 best_clock_source = best_parent_index + 1;
 113                         }
 114
 115                         if (!best_diff || tmp_rate < rate)
 116                                 break;
 117                 }
 118
 119                 if (!best_diff)
 120                         break;
 121         }
 122
 123         debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
 124               best_parent.dev->name, best_rate, best_div);
 125
 126         ret = clk_enable(&best_parent);
 127         if (ret)
 128                 return ret;
 129
 130         writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
 131         tmp = readl(&pmc->pcr);
 132         tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
 133         tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
 134                AT91_PMC_PCR_CMD_WRITE |
 135                AT91_PMC_PCR_GCKDIV_(best_div) |
 136                AT91_PMC_PCR_GCKEN;
 137         writel(tmp, &pmc->pcr);
 138
 139         while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
 140                 ;
 141
 142         return 0;
 143 }
 144
 145 static struct clk_ops generic_clk_ops = {
 146         .of_xlate = at91_clk_of_xlate,
 147         .get_rate = generic_clk_get_rate,
 148         .set_rate = generic_clk_set_rate,
 149 };
 150
 151 static int generic_clk_ofdata_to_platdata(struct udevice *dev)
 152 {
 153         struct generic_clk_priv *priv = dev_get_priv(dev);
 154         u32 cells[GENERATED_SOURCE_MAX];
 155         u32 num_parents;
 156
 157         num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
 158                         dev_of_offset(dev_get_parent(dev)), "clocks", cells,
 159                         GENERATED_SOURCE_MAX);
 160
 161         if (!num_parents)
 162                 return -1;
 163
 164         priv->num_parents = num_parents;
 165
 166         return 0;
 167 }
 168
 169 U_BOOT_DRIVER(generic_clk) = {
 170         .name = "generic-clk",
 171         .id = UCLASS_CLK,
 172         .probe = at91_clk_probe,
 173         .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
 174         .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
 175         .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
 176         .ops = &generic_clk_ops,
 177 };