1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
7 thus are a key power management tool on many systems.
9 config HAVE_CLK_PREPARE
12 config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
16 Select this option when the clock API in <linux/clk.h> is implemented
17 by platform/architecture code. This method is deprecated. Modern
18 code should select COMMON_CLK instead and not define a custom
22 bool "Common Clock Framework"
23 depends on !HAVE_LEGACY_CLK
24 select HAVE_CLK_PREPARE
28 The common clock framework is a single definition of struct
29 clk, useful across many platforms, as well as an
30 implementation of the clock API in include/linux/clk.h.
31 Architectures utilizing the common struct clk should select
36 config COMMON_CLK_WM831X
37 tristate "Clock driver for WM831x/2x PMICs"
40 Supports the clocking subsystem of the WM831x/2x series of
41 PMICs from Wolfson Microelectronics.
43 source "drivers/clk/versatile/Kconfig"
46 bool "PLL Driver for HSDK platform"
47 depends on ARC_SOC_HSDK || COMPILE_TEST
50 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
58 Say yes here to build support for Texas Instruments' LMK04832 Ultra
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
61 config COMMON_CLK_APPLE_NCO
62 tristate "Clock driver for Apple SoC NCOs"
63 depends on ARCH_APPLE || COMPILE_TEST
66 This driver supports NCO (Numerically Controlled Oscillator) blocks
67 found on Apple SoCs such as t8103 (M1). The blocks are typically
68 generators of audio clocks.
70 config COMMON_CLK_MAX77686
71 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
72 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
74 This driver supports Maxim 77620/77686/77802 crystal oscillator
77 config COMMON_CLK_MAX9485
78 tristate "Maxim 9485 Programmable Clock Generator"
81 This driver supports Maxim 9485 Programmable Audio Clock Generator
83 config COMMON_CLK_RK808
84 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
87 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
89 Clkout1 is always on, Clkout2 can off by control register.
92 tristate "Raspberry Pi RP1-based clock support"
93 depends on PCI || COMPILE_TEST
96 Enable common clock framework support for Raspberry Pi RP1
98 config COMMON_CLK_RP1_SDIO
99 tristate "Clock driver for the RP1 SDIO interfaces"
102 SDIO clock driver for the RP1 support chip
104 config COMMON_CLK_HI655X
105 tristate "Clock driver for Hi655x" if EXPERT
106 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
108 default MFD_HI655X_PMIC
110 This driver supports the hi655x PMIC clock. This
111 multi-function device has one fixed-rate oscillator, clocked
114 config COMMON_CLK_HIFIBERRY_DACPLUSHD
117 config COMMON_CLK_HIFIBERRY_DACPRO
120 config COMMON_CLK_SCMI
121 tristate "Clock driver controlled via SCMI interface"
122 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
124 This driver provides support for clocks that are controlled
125 by firmware that implements the SCMI interface.
127 This driver uses SCMI Message Protocol to interact with the
128 firmware providing all the clock controls.
130 config COMMON_CLK_SCPI
131 tristate "Clock driver controlled via SCPI interface"
132 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
134 This driver provides support for clocks that are controlled
135 by firmware that implements the SCPI interface.
137 This driver uses SCPI Message Protocol to interact with the
138 firmware providing all the clock controls.
140 config COMMON_CLK_SI5341
141 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
145 This driver supports Silicon Labs Si5341 and Si5340 programmable clock
146 generators. Not all features of these chips are currently supported
147 by the driver, in particular it only supports XTAL input. The chip can
148 be pre-programmed to support other configurations and features not yet
149 implemented in the driver.
151 config COMMON_CLK_SI5351
152 tristate "Clock driver for SiLabs 5351A/B/C"
156 This driver supports Silicon Labs 5351A/B/C programmable clock
159 config COMMON_CLK_SI514
160 tristate "Clock driver for SiLabs 514 devices"
165 This driver supports the Silicon Labs 514 programmable clock
168 config COMMON_CLK_SI544
169 tristate "Clock driver for SiLabs 544 devices"
173 This driver supports the Silicon Labs 544 programmable clock
176 config COMMON_CLK_SI570
177 tristate "Clock driver for SiLabs 570 and compatible devices"
182 This driver supports Silicon Labs 570/571/598/599 programmable
185 config COMMON_CLK_BM1880
186 bool "Clock driver for Bitmain BM1880 SoC"
187 depends on ARCH_BITMAIN || COMPILE_TEST
190 This driver supports the clocks on Bitmain BM1880 SoC.
192 config COMMON_CLK_CDCE706
193 tristate "Clock driver for TI CDCE706 clock synthesizer"
197 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
199 config COMMON_CLK_TPS68470
200 tristate "Clock Driver for TI TPS68470 PMIC"
202 depends on INTEL_SKL_INT3472 || COMPILE_TEST
205 This driver supports the clocks provided by the TPS68470 PMIC.
207 config COMMON_CLK_CDCE925
208 tristate "Clock driver for TI CDCE913/925/937/949 devices"
213 This driver supports the TI CDCE913/925/937/949 programmable clock
214 synthesizer. Each chip has different number of PLLs and outputs.
215 For example, the CDCE925 contains two PLLs with spread-spectrum
216 clocking support and five output dividers. The driver only supports
217 the following setup, and uses a fixed setting for the output muxes.
218 Y1 is derived from the input clock
219 Y2 and Y3 derive from PLL1
220 Y4 and Y5 derive from PLL2
221 Given a target output frequency, the driver will set the PLL and
222 divider to best approximate the desired output.
224 config COMMON_CLK_CS2000_CP
225 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
229 If you say yes here you get support for the CS2000 clock multiplier.
231 config COMMON_CLK_EN7523
232 bool "Clock driver for Airoha EN7523 SoC system clocks"
234 depends on ARCH_AIROHA || COMPILE_TEST
237 This driver provides the fixed clocks and gates present on Airoha
240 config COMMON_CLK_FSL_FLEXSPI
241 tristate "Clock driver for FlexSPI on Layerscape SoCs"
242 depends on ARCH_LAYERSCAPE || COMPILE_TEST
243 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
245 On Layerscape SoCs there is a special clock for the FlexSPI
248 config COMMON_CLK_FSL_SAI
249 bool "Clock driver for BCLK of Freescale SAI cores"
250 depends on ARCH_LAYERSCAPE || COMPILE_TEST
252 This driver supports the Freescale SAI (Synchronous Audio Interface)
253 to be used as a generic clock output. Some SoCs have restrictions
254 regarding the possible pin multiplexer settings. Eg. on some SoCs
255 two SAI interfaces can only be enabled together. If just one is
256 needed, the BCLK pin of the second one can be used as general
257 purpose clock output. Ideally, it can be used to drive an audio
258 codec (sometimes known as MCLK).
260 config COMMON_CLK_GEMINI
261 bool "Clock driver for Cortina Systems Gemini SoC"
262 depends on ARCH_GEMINI || COMPILE_TEST
264 select RESET_CONTROLLER
266 This driver supports the SoC clocks on the Cortina Systems Gemini
267 platform, also known as SL3516 or CS3516.
269 config COMMON_CLK_LAN966X
270 tristate "Generic Clock Controller driver for LAN966X SoC"
273 depends on SOC_LAN966 || COMPILE_TEST
275 This driver provides support for Generic Clock Controller(GCK) on
276 LAN966X SoC. GCK generates and supplies clock to various peripherals
279 config COMMON_CLK_ASPEED
280 bool "Clock driver for Aspeed BMC SoCs"
281 depends on ARCH_ASPEED || COMPILE_TEST
284 select RESET_CONTROLLER
286 This driver supports the SoC clocks on the Aspeed BMC platforms.
288 The G4 and G5 series, including the ast2400 and ast2500, are supported
291 config COMMON_CLK_S2MPS11
292 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
293 depends on MFD_SEC_CORE || COMPILE_TEST
295 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
296 clock. These multi-function devices have two (S2MPS14) or three
297 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
300 tristate "External McPDM functional clock from twl6040"
301 depends on TWL6040_CORE
303 Enable the external functional clock support on OMAP4+ platforms for
304 McPDM. McPDM module is using the external bit clock on the McPDM bus
307 config COMMON_CLK_AXI_CLKGEN
308 tristate "AXI clkgen driver"
309 depends on HAS_IOMEM || COMPILE_TEST
312 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
313 FPGAs. It is commonly used in Analog Devices' reference designs.
316 bool "Clock driver for Freescale QorIQ platforms"
318 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
320 This adds the clock driver support for Freescale QorIQ platforms
321 using common clock framework.
323 config CLK_LS1028A_PLLDIG
324 tristate "Clock driver for LS1028A Display output"
325 depends on ARCH_LAYERSCAPE || COMPILE_TEST
326 default ARCH_LAYERSCAPE
328 This driver support the Display output interfaces(LCD, DPHY) pixel clocks
329 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
330 features of the PLL are currently supported by the driver. By default,
331 configured bypass mode with this PLL.
333 config COMMON_CLK_XGENE
334 bool "Clock driver for APM XGene SoC"
336 depends on ARM64 || COMPILE_TEST
338 Support for the APM X-Gene SoC reference, PLL, and device clocks.
340 config COMMON_CLK_LOCHNAGAR
341 tristate "Cirrus Logic Lochnagar clock driver"
342 depends on MFD_LOCHNAGAR
344 This driver supports the clocking features of the Cirrus Logic
345 Lochnagar audio development board.
347 config COMMON_CLK_LOONGSON2
348 bool "Clock driver for Loongson-2 SoC"
349 depends on LOONGARCH || COMPILE_TEST
351 This driver provides support for clock controller on Loongson-2 SoC.
352 The clock controller can generates and supplies clock to various
353 peripherals within the SoC.
354 Say Y here to support Loongson-2 SoC clock driver.
356 config COMMON_CLK_NXP
357 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
358 select REGMAP_MMIO if ARCH_LPC32XX
359 select MFD_SYSCON if ARCH_LPC18XX
361 Support for clock providers on NXP platforms.
363 config COMMON_CLK_PALMAS
364 tristate "Clock driver for TI Palmas devices"
365 depends on MFD_PALMAS
367 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
368 using common clock framework.
370 config COMMON_CLK_PWM
371 tristate "Clock driver for PWMs used as clock outputs"
374 Adapter driver so that any PWM output can be (mis)used as clock signal
377 config COMMON_CLK_PXA
378 def_bool COMMON_CLK && ARCH_PXA
380 Support for the Marvell PXA SoC.
382 config COMMON_CLK_RS9_PCIE
383 tristate "Clock driver for Renesas 9-series PCIe clock generators"
388 This driver supports the Renesas 9-series PCIe clock generator
389 models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
391 config COMMON_CLK_SI521XX
392 tristate "Clock driver for SkyWorks Si521xx PCIe clock generators"
397 This driver supports the SkyWorks Si521xx PCIe clock generator
398 models Si52144/Si52146/Si52147.
400 config COMMON_CLK_VC3
401 tristate "Clock driver for Renesas VersaClock 3 devices"
406 This driver supports the Renesas VersaClock 3 programmable clock
409 config COMMON_CLK_VC5
410 tristate "Clock driver for IDT VersaClock 5,6 devices"
415 This driver supports the IDT VersaClock 5 and VersaClock 6
416 programmable clock generators.
418 config COMMON_CLK_VC7
419 tristate "Clock driver for Renesas Versaclock 7 devices"
424 Renesas Versaclock7 is a family of configurable clock generator
425 and jitter attenuator ICs with fractional and integer dividers.
427 config COMMON_CLK_STM32MP135
428 def_bool COMMON_CLK && MACH_STM32MP13
430 Support for stm32mp135 SoC family clocks
432 config COMMON_CLK_STM32MP157
433 def_bool COMMON_CLK && MACH_STM32MP157
435 Support for stm32mp157 SoC family clocks
437 config COMMON_CLK_STM32F
438 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
440 Support for stm32f4 and stm32f7 SoC families clocks
442 config COMMON_CLK_STM32H7
443 def_bool COMMON_CLK && MACH_STM32H743
445 Support for stm32h7 SoC family clocks
447 config COMMON_CLK_MMP2
448 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
450 Support for Marvell MMP2 and MMP3 SoC clocks
452 config COMMON_CLK_MMP2_AUDIO
453 tristate "Clock driver for MMP2 Audio subsystem"
454 depends on COMMON_CLK_MMP2 || COMPILE_TEST
456 This driver supports clocks for Audio subsystem on MMP2 SoC.
458 config COMMON_CLK_BD718XX
459 tristate "Clock driver for 32K clk gates on ROHM PMICs"
460 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
462 This driver supports ROHM BD71837, BD71847, BD71850, BD71815
463 and BD71828 PMICs clock gates.
465 config COMMON_CLK_FIXED_MMIO
466 bool "Clock driver for Memory Mapped Fixed values"
467 depends on COMMON_CLK && OF
470 Support for Memory Mapped IO Fixed clocks
472 config COMMON_CLK_K210
473 bool "Clock driver for the Canaan Kendryte K210 SoC"
474 depends on OF && RISCV && SOC_CANAAN
477 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
479 config COMMON_CLK_SP7021
480 tristate "Clock driver for Sunplus SP7021 SoC"
481 depends on SOC_SP7021 || COMPILE_TEST
484 This driver supports the Sunplus SP7021 SoC clocks.
485 It implements SP7021 PLLs/gate.
486 Not all features of the PLL are currently supported
489 source "drivers/clk/actions/Kconfig"
490 source "drivers/clk/analogbits/Kconfig"
491 source "drivers/clk/baikal-t1/Kconfig"
492 source "drivers/clk/bcm/Kconfig"
493 source "drivers/clk/hisilicon/Kconfig"
494 source "drivers/clk/imgtec/Kconfig"
495 source "drivers/clk/imx/Kconfig"
496 source "drivers/clk/ingenic/Kconfig"
497 source "drivers/clk/keystone/Kconfig"
498 source "drivers/clk/mediatek/Kconfig"
499 source "drivers/clk/meson/Kconfig"
500 source "drivers/clk/mstar/Kconfig"
501 source "drivers/clk/microchip/Kconfig"
502 source "drivers/clk/mvebu/Kconfig"
503 source "drivers/clk/nuvoton/Kconfig"
504 source "drivers/clk/pistachio/Kconfig"
505 source "drivers/clk/qcom/Kconfig"
506 source "drivers/clk/ralink/Kconfig"
507 source "drivers/clk/renesas/Kconfig"
508 source "drivers/clk/rockchip/Kconfig"
509 source "drivers/clk/samsung/Kconfig"
510 source "drivers/clk/sifive/Kconfig"
511 source "drivers/clk/socfpga/Kconfig"
512 source "drivers/clk/sprd/Kconfig"
513 source "drivers/clk/starfive/Kconfig"
514 source "drivers/clk/sunxi/Kconfig"
515 source "drivers/clk/sunxi-ng/Kconfig"
516 source "drivers/clk/tegra/Kconfig"
517 source "drivers/clk/ti/Kconfig"
518 source "drivers/clk/uniphier/Kconfig"
519 source "drivers/clk/visconti/Kconfig"
520 source "drivers/clk/x86/Kconfig"
521 source "drivers/clk/xilinx/Kconfig"
522 source "drivers/clk/zynqmp/Kconfig"
525 config CLK_KUNIT_TEST
526 tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS
528 default KUNIT_ALL_TESTS
530 Kunit tests for the common clock framework.
532 config CLK_GATE_KUNIT_TEST
533 tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
535 default KUNIT_ALL_TESTS
537 Kunit test for the basic clk gate type.