1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
7 thus are a key power management tool on many systems.
9 config HAVE_CLK_PREPARE
12 config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated
16 Select this option when the clock API in <linux/clk.h> is implemented
17 by platform/architecture code. This method is deprecated. Modern
18 code should select COMMON_CLK instead and not define a custom
22 bool "Common Clock Framework"
23 depends on !HAVE_LEGACY_CLK
24 select HAVE_CLK_PREPARE
29 The common clock framework is a single definition of struct
30 clk, useful across many platforms, as well as an
31 implementation of the clock API in include/linux/clk.h.
32 Architectures utilizing the common struct clk should select
37 config COMMON_CLK_WM831X
38 tristate "Clock driver for WM831x/2x PMICs"
41 Supports the clocking subsystem of the WM831x/2x series of
42 PMICs from Wolfson Microelectronics.
44 source "drivers/clk/versatile/Kconfig"
47 bool "PLL Driver for HSDK platform"
48 depends on ARC_SOC_HSDK || COMPILE_TEST
51 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
55 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Say yes here to build support for Texas Instruments' LMK04832 Ultra
60 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
62 config COMMON_CLK_MAX77686
63 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
64 depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
66 This driver supports Maxim 77620/77686/77802 crystal oscillator
69 config COMMON_CLK_MAX9485
70 tristate "Maxim 9485 Programmable Clock Generator"
73 This driver supports Maxim 9485 Programmable Audio Clock Generator
75 config COMMON_CLK_RK808
76 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
79 This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
80 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
81 Clkout1 is always on, Clkout2 can off by control register.
83 config COMMON_CLK_HI655X
84 tristate "Clock driver for Hi655x" if EXPERT
85 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
87 default MFD_HI655X_PMIC
89 This driver supports the hi655x PMIC clock. This
90 multi-function device has one fixed-rate oscillator, clocked
93 config COMMON_CLK_HIFIBERRY_DACPLUSHD
96 config COMMON_CLK_HIFIBERRY_DACPRO
99 config COMMON_CLK_SCMI
100 tristate "Clock driver controlled via SCMI interface"
101 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
103 This driver provides support for clocks that are controlled
104 by firmware that implements the SCMI interface.
106 This driver uses SCMI Message Protocol to interact with the
107 firmware providing all the clock controls.
109 config COMMON_CLK_SCPI
110 tristate "Clock driver controlled via SCPI interface"
111 depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
113 This driver provides support for clocks that are controlled
114 by firmware that implements the SCPI interface.
116 This driver uses SCPI Message Protocol to interact with the
117 firmware providing all the clock controls.
119 config COMMON_CLK_SI5341
120 tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices"
124 This driver supports Silicon Labs Si5341 and Si5340 programmable clock
125 generators. Not all features of these chips are currently supported
126 by the driver, in particular it only supports XTAL input. The chip can
127 be pre-programmed to support other configurations and features not yet
128 implemented in the driver.
130 config COMMON_CLK_SI5351
131 tristate "Clock driver for SiLabs 5351A/B/C"
135 This driver supports Silicon Labs 5351A/B/C programmable clock
138 config COMMON_CLK_SI514
139 tristate "Clock driver for SiLabs 514 devices"
144 This driver supports the Silicon Labs 514 programmable clock
147 config COMMON_CLK_SI544
148 tristate "Clock driver for SiLabs 544 devices"
152 This driver supports the Silicon Labs 544 programmable clock
155 config COMMON_CLK_SI570
156 tristate "Clock driver for SiLabs 570 and compatible devices"
161 This driver supports Silicon Labs 570/571/598/599 programmable
164 config COMMON_CLK_BM1880
165 bool "Clock driver for Bitmain BM1880 SoC"
166 depends on ARCH_BITMAIN || COMPILE_TEST
169 This driver supports the clocks on Bitmain BM1880 SoC.
171 config COMMON_CLK_CDCE706
172 tristate "Clock driver for TI CDCE706 clock synthesizer"
176 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
178 config COMMON_CLK_CDCE925
179 tristate "Clock driver for TI CDCE913/925/937/949 devices"
184 This driver supports the TI CDCE913/925/937/949 programmable clock
185 synthesizer. Each chip has different number of PLLs and outputs.
186 For example, the CDCE925 contains two PLLs with spread-spectrum
187 clocking support and five output dividers. The driver only supports
188 the following setup, and uses a fixed setting for the output muxes.
189 Y1 is derived from the input clock
190 Y2 and Y3 derive from PLL1
191 Y4 and Y5 derive from PLL2
192 Given a target output frequency, the driver will set the PLL and
193 divider to best approximate the desired output.
195 config COMMON_CLK_CS2000_CP
196 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
199 If you say yes here you get support for the CS2000 clock multiplier.
201 config COMMON_CLK_FSL_FLEXSPI
202 tristate "Clock driver for FlexSPI on Layerscape SoCs"
203 depends on ARCH_LAYERSCAPE || COMPILE_TEST
204 default ARCH_LAYERSCAPE && SPI_NXP_FLEXSPI
206 On Layerscape SoCs there is a special clock for the FlexSPI
209 config COMMON_CLK_FSL_SAI
210 bool "Clock driver for BCLK of Freescale SAI cores"
211 depends on ARCH_LAYERSCAPE || COMPILE_TEST
213 This driver supports the Freescale SAI (Synchronous Audio Interface)
214 to be used as a generic clock output. Some SoCs have restrictions
215 regarding the possible pin multiplexer settings. Eg. on some SoCs
216 two SAI interfaces can only be enabled together. If just one is
217 needed, the BCLK pin of the second one can be used as general
218 purpose clock output. Ideally, it can be used to drive an audio
219 codec (sometimes known as MCLK).
221 config COMMON_CLK_GEMINI
222 bool "Clock driver for Cortina Systems Gemini SoC"
223 depends on ARCH_GEMINI || COMPILE_TEST
225 select RESET_CONTROLLER
227 This driver supports the SoC clocks on the Cortina Systems Gemini
228 platform, also known as SL3516 or CS3516.
230 config COMMON_CLK_ASPEED
231 bool "Clock driver for Aspeed BMC SoCs"
232 depends on ARCH_ASPEED || COMPILE_TEST
235 select RESET_CONTROLLER
237 This driver supports the SoC clocks on the Aspeed BMC platforms.
239 The G4 and G5 series, including the ast2400 and ast2500, are supported
242 config COMMON_CLK_S2MPS11
243 tristate "Clock driver for S2MPS1X/S5M8767 MFD"
244 depends on MFD_SEC_CORE || COMPILE_TEST
246 This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator
247 clock. These multi-function devices have two (S2MPS14) or three
248 (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each.
251 tristate "External McPDM functional clock from twl6040"
252 depends on TWL6040_CORE
254 Enable the external functional clock support on OMAP4+ platforms for
255 McPDM. McPDM module is using the external bit clock on the McPDM bus
258 config COMMON_CLK_AXI_CLKGEN
259 tristate "AXI clkgen driver"
260 depends on HAS_IOMEM || COMPILE_TEST
263 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
264 FPGAs. It is commonly used in Analog Devices' reference designs.
267 bool "Clock driver for Freescale QorIQ platforms"
269 depends on PPC_E500MC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
271 This adds the clock driver support for Freescale QorIQ platforms
272 using common clock framework.
274 config CLK_LS1028A_PLLDIG
275 tristate "Clock driver for LS1028A Display output"
276 depends on ARCH_LAYERSCAPE || COMPILE_TEST
277 default ARCH_LAYERSCAPE
279 This driver support the Display output interfaces(LCD, DPHY) pixel clocks
280 of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
281 features of the PLL are currently supported by the driver. By default,
282 configured bypass mode with this PLL.
284 config COMMON_CLK_XGENE
285 bool "Clock driver for APM XGene SoC"
287 depends on ARM64 || COMPILE_TEST
289 Support for the APM X-Gene SoC reference, PLL, and device clocks.
291 config COMMON_CLK_LOCHNAGAR
292 tristate "Cirrus Logic Lochnagar clock driver"
293 depends on MFD_LOCHNAGAR
295 This driver supports the clocking features of the Cirrus Logic
296 Lochnagar audio development board.
298 config COMMON_CLK_NXP
299 def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
300 select REGMAP_MMIO if ARCH_LPC32XX
301 select MFD_SYSCON if ARCH_LPC18XX
303 Support for clock providers on NXP platforms.
305 config COMMON_CLK_PALMAS
306 tristate "Clock driver for TI Palmas devices"
307 depends on MFD_PALMAS
309 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
310 using common clock framework.
312 config COMMON_CLK_PWM
313 tristate "Clock driver for PWMs used as clock outputs"
316 Adapter driver so that any PWM output can be (mis)used as clock signal
319 config COMMON_CLK_PXA
320 def_bool COMMON_CLK && ARCH_PXA
322 Support for the Marvell PXA SoC.
324 config COMMON_CLK_PIC32
325 def_bool COMMON_CLK && MACH_PIC32
327 config COMMON_CLK_OXNAS
328 bool "Clock driver for the OXNAS SoC Family"
329 depends on ARCH_OXNAS || COMPILE_TEST
332 Support for the OXNAS SoC Family clocks.
334 config COMMON_CLK_VC5
335 tristate "Clock driver for IDT VersaClock 5,6 devices"
340 This driver supports the IDT VersaClock 5 and VersaClock 6
341 programmable clock generators.
343 config COMMON_CLK_STM32MP157
344 def_bool COMMON_CLK && MACH_STM32MP157
346 Support for stm32mp157 SoC family clocks
348 config COMMON_CLK_STM32MP157_SCMI
349 bool "stm32mp157 Clock driver with Trusted Firmware"
350 depends on COMMON_CLK_STM32MP157
351 select COMMON_CLK_SCMI
352 select ARM_SCMI_PROTOCOL
355 Support for stm32mp157 SoC family clocks with Trusted Firmware using
358 config COMMON_CLK_STM32F
359 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
361 Support for stm32f4 and stm32f7 SoC families clocks
363 config COMMON_CLK_STM32H7
364 def_bool COMMON_CLK && MACH_STM32H743
366 Support for stm32h7 SoC family clocks
368 config COMMON_CLK_MMP2
369 def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
371 Support for Marvell MMP2 and MMP3 SoC clocks
373 config COMMON_CLK_MMP2_AUDIO
374 tristate "Clock driver for MMP2 Audio subsystem"
375 depends on COMMON_CLK_MMP2 || COMPILE_TEST
377 This driver supports clocks for Audio subsystem on MMP2 SoC.
379 config COMMON_CLK_BD718XX
380 tristate "Clock driver for 32K clk gates on ROHM PMICs"
381 depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
383 This driver supports ROHM BD71837, BD71847, BD71850, BD71815
384 and BD71828 PMICs clock gates.
386 config COMMON_CLK_FIXED_MMIO
387 bool "Clock driver for Memory Mapped Fixed values"
388 depends on COMMON_CLK && OF
390 Support for Memory Mapped IO Fixed clocks
392 config COMMON_CLK_K210
393 bool "Clock driver for the Canaan Kendryte K210 SoC"
394 depends on OF && RISCV && SOC_CANAAN
397 Support for the Canaan Kendryte K210 RISC-V SoC clocks.
399 source "drivers/clk/actions/Kconfig"
400 source "drivers/clk/analogbits/Kconfig"
401 source "drivers/clk/baikal-t1/Kconfig"
402 source "drivers/clk/bcm/Kconfig"
403 source "drivers/clk/hisilicon/Kconfig"
404 source "drivers/clk/imgtec/Kconfig"
405 source "drivers/clk/imx/Kconfig"
406 source "drivers/clk/ingenic/Kconfig"
407 source "drivers/clk/keystone/Kconfig"
408 source "drivers/clk/mediatek/Kconfig"
409 source "drivers/clk/meson/Kconfig"
410 source "drivers/clk/mstar/Kconfig"
411 source "drivers/clk/mvebu/Kconfig"
412 source "drivers/clk/pistachio/Kconfig"
413 source "drivers/clk/qcom/Kconfig"
414 source "drivers/clk/ralink/Kconfig"
415 source "drivers/clk/renesas/Kconfig"
416 source "drivers/clk/rockchip/Kconfig"
417 source "drivers/clk/samsung/Kconfig"
418 source "drivers/clk/sifive/Kconfig"
419 source "drivers/clk/socfpga/Kconfig"
420 source "drivers/clk/sprd/Kconfig"
421 source "drivers/clk/sunxi/Kconfig"
422 source "drivers/clk/sunxi-ng/Kconfig"
423 source "drivers/clk/tegra/Kconfig"
424 source "drivers/clk/ti/Kconfig"
425 source "drivers/clk/uniphier/Kconfig"
426 source "drivers/clk/x86/Kconfig"
427 source "drivers/clk/xilinx/Kconfig"
428 source "drivers/clk/zynqmp/Kconfig"
431 config CLK_KUNIT_TEST
432 tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS
434 default KUNIT_ALL_TESTS
436 Kunit tests for the common clock framework.