2 * Device driver for Microgate SyncLink GT serial adapters.
4 * written by Paul Fulghum for Microgate Corporation
7 * Microgate and SyncLink are trademarks of Microgate Corporation
9 * This code is released under the GNU General Public License (GPL)
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
25 * DEBUG OUTPUT DEFINITIONS
27 * uncomment lines below to enable specific types of debug output
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
76 #include <asm/system.h>
80 #include <asm/types.h>
81 #include <asm/uaccess.h>
83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84 #define SYNCLINK_GENERIC_HDLC 1
86 #define SYNCLINK_GENERIC_HDLC 0
90 * module identification
92 static char *driver_name = "SyncLink GT";
93 static char *tty_driver_name = "synclink_gt";
94 static char *tty_dev_prefix = "ttySLG";
95 MODULE_LICENSE("GPL");
96 #define MGSL_MAGIC 0x5401
97 #define MAX_DEVICES 32
99 static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
106 MODULE_DEVICE_TABLE(pci, pci_table);
108 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109 static void remove_one(struct pci_dev *dev);
110 static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
114 .remove = __devexit_p(remove_one),
117 static bool pci_registered;
120 * module configuration and status
122 static struct slgt_info *slgt_device_list;
123 static int slgt_device_count;
126 static int debug_level;
127 static int maxframe[MAX_DEVICES];
129 module_param(ttymajor, int, 0);
130 module_param(debug_level, int, 0);
131 module_param_array(maxframe, int, NULL, 0);
133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
138 * tty support and callbacks
140 static struct tty_driver *serial_driver;
142 static int open(struct tty_struct *tty, struct file * filp);
143 static void close(struct tty_struct *tty, struct file * filp);
144 static void hangup(struct tty_struct *tty);
145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
147 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148 static int put_char(struct tty_struct *tty, unsigned char ch);
149 static void send_xchar(struct tty_struct *tty, char ch);
150 static void wait_until_sent(struct tty_struct *tty, int timeout);
151 static int write_room(struct tty_struct *tty);
152 static void flush_chars(struct tty_struct *tty);
153 static void flush_buffer(struct tty_struct *tty);
154 static void tx_hold(struct tty_struct *tty);
155 static void tx_release(struct tty_struct *tty);
157 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
158 static int chars_in_buffer(struct tty_struct *tty);
159 static void throttle(struct tty_struct * tty);
160 static void unthrottle(struct tty_struct * tty);
161 static int set_break(struct tty_struct *tty, int break_state);
164 * generic HDLC support and callbacks
166 #if SYNCLINK_GENERIC_HDLC
167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
168 static void hdlcdev_tx_done(struct slgt_info *info);
169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170 static int hdlcdev_init(struct slgt_info *info);
171 static void hdlcdev_exit(struct slgt_info *info);
176 * device specific structures, macros and functions
179 #define SLGT_MAX_PORTS 4
180 #define SLGT_REG_SIZE 256
183 * conditional wait facility
186 struct cond_wait *next;
191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void flush_cond_wait(struct cond_wait **head);
197 * DMA buffer descriptor and access macros
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
218 #define desc_count(a) (le16_to_cpu((a).count))
219 #define desc_status(a) (le16_to_cpu((a).status))
220 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
221 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
222 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
223 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
224 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
226 struct _input_signal_events {
238 * device instance data structure
241 void *if_ptr; /* General purpose pointer (used by SPPP) */
242 struct tty_port port;
244 struct slgt_info *next_device; /* device list link */
248 char device_name[25];
249 struct pci_dev *pdev;
251 int port_count; /* count of ports on adapter */
252 int adapter_num; /* adapter instance number */
253 int port_num; /* port instance number */
255 /* array of pointers to port contexts on this adapter */
256 struct slgt_info *port_array[SLGT_MAX_PORTS];
258 int line; /* tty line instance number */
260 struct mgsl_icount icount;
263 int x_char; /* xon/xoff character */
264 unsigned int read_status_mask;
265 unsigned int ignore_status_mask;
267 wait_queue_head_t status_event_wait_q;
268 wait_queue_head_t event_wait_q;
269 struct timer_list tx_timer;
270 struct timer_list rx_timer;
272 unsigned int gpio_present;
273 struct cond_wait *gpio_wait_q;
275 spinlock_t lock; /* spinlock for synchronizing with ISR */
277 struct work_struct task;
283 bool irq_requested; /* true if IRQ requested */
284 bool irq_occurred; /* for diagnostics use */
286 /* device configuration */
288 unsigned int bus_type;
289 unsigned int irq_level;
290 unsigned long irq_flags;
292 unsigned char __iomem * reg_addr; /* memory mapped registers address */
294 bool reg_addr_requested;
296 MGSL_PARAMS params; /* communications parameters */
298 u32 max_frame_size; /* as set by device config */
300 unsigned int rbuf_fill_level;
302 unsigned int if_mode;
303 unsigned int base_clock;
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
316 unsigned char *tx_buf;
319 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
320 char char_buf[MAX_ASYNC_BUFFER_SIZE];
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
347 /* SPPP/Cisco HDLC device parts */
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
370 .parity = ASYNC_PARITY_NONE
375 #define BH_TRANSMIT 2
377 #define IO_PIN_SHUTDOWN_LIMIT 100
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
410 #define RXBREAK BIT14
411 #define IRQ_TXDATA BIT13
412 #define IRQ_TXIDLE BIT12
413 #define IRQ_TXUNDER BIT11 /* HDLC */
414 #define IRQ_RXDATA BIT10
415 #define IRQ_RXIDLE BIT9 /* HDLC */
416 #define IRQ_RXBREAK BIT9 /* async */
417 #define IRQ_RXOVER BIT8
422 #define IRQ_ALL 0x3ff0
423 #define IRQ_MASTER BIT0
425 #define slgt_irq_on(info, mask) \
426 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
427 #define slgt_irq_off(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
431 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
432 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
433 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
434 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
435 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437 static void msc_set_vcr(struct slgt_info *info);
439 static int startup(struct slgt_info *info);
440 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
441 static void shutdown(struct slgt_info *info);
442 static void program_hw(struct slgt_info *info);
443 static void change_params(struct slgt_info *info);
445 static int register_test(struct slgt_info *info);
446 static int irq_test(struct slgt_info *info);
447 static int loopback_test(struct slgt_info *info);
448 static int adapter_test(struct slgt_info *info);
450 static void reset_adapter(struct slgt_info *info);
451 static void reset_port(struct slgt_info *info);
452 static void async_mode(struct slgt_info *info);
453 static void sync_mode(struct slgt_info *info);
455 static void rx_stop(struct slgt_info *info);
456 static void rx_start(struct slgt_info *info);
457 static void reset_rbufs(struct slgt_info *info);
458 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
459 static void rdma_reset(struct slgt_info *info);
460 static bool rx_get_frame(struct slgt_info *info);
461 static bool rx_get_buf(struct slgt_info *info);
463 static void tx_start(struct slgt_info *info);
464 static void tx_stop(struct slgt_info *info);
465 static void tx_set_idle(struct slgt_info *info);
466 static unsigned int free_tbuf_count(struct slgt_info *info);
467 static unsigned int tbuf_bytes(struct slgt_info *info);
468 static void reset_tbufs(struct slgt_info *info);
469 static void tdma_reset(struct slgt_info *info);
470 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472 static void get_signals(struct slgt_info *info);
473 static void set_signals(struct slgt_info *info);
474 static void enable_loopback(struct slgt_info *info);
475 static void set_rate(struct slgt_info *info, u32 data_rate);
477 static int bh_action(struct slgt_info *info);
478 static void bh_handler(struct work_struct *work);
479 static void bh_transmit(struct slgt_info *info);
480 static void isr_serial(struct slgt_info *info);
481 static void isr_rdma(struct slgt_info *info);
482 static void isr_txeom(struct slgt_info *info, unsigned short status);
483 static void isr_tdma(struct slgt_info *info);
485 static int alloc_dma_bufs(struct slgt_info *info);
486 static void free_dma_bufs(struct slgt_info *info);
487 static int alloc_desc(struct slgt_info *info);
488 static void free_desc(struct slgt_info *info);
489 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
490 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static int alloc_tmp_rbuf(struct slgt_info *info);
493 static void free_tmp_rbuf(struct slgt_info *info);
495 static void tx_timeout(unsigned long context);
496 static void rx_timeout(unsigned long context);
501 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
502 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
503 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
505 static int set_txidle(struct slgt_info *info, int idle_mode);
506 static int tx_enable(struct slgt_info *info, int enable);
507 static int tx_abort(struct slgt_info *info);
508 static int rx_enable(struct slgt_info *info, int enable);
509 static int modem_input_wait(struct slgt_info *info,int arg);
510 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
511 static int tiocmget(struct tty_struct *tty, struct file *file);
512 static int tiocmset(struct tty_struct *tty, struct file *file,
513 unsigned int set, unsigned int clear);
514 static int set_break(struct tty_struct *tty, int break_state);
515 static int get_interface(struct slgt_info *info, int __user *if_mode);
516 static int set_interface(struct slgt_info *info, int if_mode);
517 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
518 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
524 static void add_device(struct slgt_info *info);
525 static void device_init(int adapter_num, struct pci_dev *pdev);
526 static int claim_resources(struct slgt_info *info);
527 static void release_resources(struct slgt_info *info);
546 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
550 printk("%s %s data:\n",info->device_name, label);
552 linecount = (count > 16) ? 16 : count;
553 for(i=0; i < linecount; i++)
554 printk("%02X ",(unsigned char)data[i]);
557 for(i=0;i<linecount;i++) {
558 if (data[i]>=040 && data[i]<=0176)
559 printk("%c",data[i]);
569 #define DBGDATA(info, buf, size, label)
573 static void dump_tbufs(struct slgt_info *info)
576 printk("tbuf_current=%d\n", info->tbuf_current);
577 for (i=0 ; i < info->tbuf_count ; i++) {
578 printk("%d: count=%04X status=%04X\n",
579 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
583 #define DBGTBUF(info)
587 static void dump_rbufs(struct slgt_info *info)
590 printk("rbuf_current=%d\n", info->rbuf_current);
591 for (i=0 ; i < info->rbuf_count ; i++) {
592 printk("%d: count=%04X status=%04X\n",
593 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
597 #define DBGRBUF(info)
600 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
604 printk("null struct slgt_info for (%s) in %s\n", devname, name);
607 if (info->magic != MGSL_MAGIC) {
608 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
619 * line discipline callback wrappers
621 * The wrappers maintain line discipline references
622 * while calling into the line discipline.
624 * ldisc_receive_buf - pass receive data to line discipline
626 static void ldisc_receive_buf(struct tty_struct *tty,
627 const __u8 *data, char *flags, int count)
629 struct tty_ldisc *ld;
632 ld = tty_ldisc_ref(tty);
634 if (ld->ops->receive_buf)
635 ld->ops->receive_buf(tty, data, flags, count);
642 static int open(struct tty_struct *tty, struct file *filp)
644 struct slgt_info *info;
649 if ((line < 0) || (line >= slgt_device_count)) {
650 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
654 info = slgt_device_list;
655 while(info && info->line != line)
656 info = info->next_device;
657 if (sanity_check(info, tty->name, "open"))
659 if (info->init_error) {
660 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
664 tty->driver_data = info;
665 info->port.tty = tty;
667 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
669 /* If port is closing, signal caller to try again */
670 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
671 if (info->port.flags & ASYNC_CLOSING)
672 interruptible_sleep_on(&info->port.close_wait);
673 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
674 -EAGAIN : -ERESTARTSYS);
678 mutex_lock(&info->port.mutex);
679 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
681 spin_lock_irqsave(&info->netlock, flags);
682 if (info->netcount) {
684 spin_unlock_irqrestore(&info->netlock, flags);
685 mutex_unlock(&info->port.mutex);
689 spin_unlock_irqrestore(&info->netlock, flags);
691 if (info->port.count == 1) {
692 /* 1st open on this device, init hardware */
693 retval = startup(info);
697 mutex_unlock(&info->port.mutex);
698 retval = block_til_ready(tty, filp, info);
700 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
709 info->port.tty = NULL; /* tty layer will release tty struct */
714 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
718 static void close(struct tty_struct *tty, struct file *filp)
720 struct slgt_info *info = tty->driver_data;
722 if (sanity_check(info, tty->name, "close"))
724 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
726 if (tty_port_close_start(&info->port, tty, filp) == 0)
729 mutex_lock(&info->port.mutex);
730 if (info->port.flags & ASYNC_INITIALIZED)
731 wait_until_sent(tty, info->timeout);
733 tty_ldisc_flush(tty);
736 mutex_unlock(&info->port.mutex);
738 tty_port_close_end(&info->port, tty);
739 info->port.tty = NULL;
741 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
744 static void hangup(struct tty_struct *tty)
746 struct slgt_info *info = tty->driver_data;
749 if (sanity_check(info, tty->name, "hangup"))
751 DBGINFO(("%s hangup\n", info->device_name));
755 mutex_lock(&info->port.mutex);
758 spin_lock_irqsave(&info->port.lock, flags);
759 info->port.count = 0;
760 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
761 info->port.tty = NULL;
762 spin_unlock_irqrestore(&info->port.lock, flags);
763 mutex_unlock(&info->port.mutex);
765 wake_up_interruptible(&info->port.open_wait);
768 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
770 struct slgt_info *info = tty->driver_data;
773 DBGINFO(("%s set_termios\n", tty->driver->name));
777 /* Handle transition to B0 status */
778 if (old_termios->c_cflag & CBAUD &&
779 !(tty->termios->c_cflag & CBAUD)) {
780 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
781 spin_lock_irqsave(&info->lock,flags);
783 spin_unlock_irqrestore(&info->lock,flags);
786 /* Handle transition away from B0 status */
787 if (!(old_termios->c_cflag & CBAUD) &&
788 tty->termios->c_cflag & CBAUD) {
789 info->signals |= SerialSignal_DTR;
790 if (!(tty->termios->c_cflag & CRTSCTS) ||
791 !test_bit(TTY_THROTTLED, &tty->flags)) {
792 info->signals |= SerialSignal_RTS;
794 spin_lock_irqsave(&info->lock,flags);
796 spin_unlock_irqrestore(&info->lock,flags);
799 /* Handle turning off CRTSCTS */
800 if (old_termios->c_cflag & CRTSCTS &&
801 !(tty->termios->c_cflag & CRTSCTS)) {
807 static void update_tx_timer(struct slgt_info *info)
810 * use worst case speed of 1200bps to calculate transmit timeout
811 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
813 if (info->params.mode == MGSL_MODE_HDLC) {
814 int timeout = (tbuf_bytes(info) * 7) + 1000;
815 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
819 static int write(struct tty_struct *tty,
820 const unsigned char *buf, int count)
823 struct slgt_info *info = tty->driver_data;
826 if (sanity_check(info, tty->name, "write"))
829 DBGINFO(("%s write count=%d\n", info->device_name, count));
831 if (!info->tx_buf || (count > info->max_frame_size))
834 if (!count || tty->stopped || tty->hw_stopped)
837 spin_lock_irqsave(&info->lock, flags);
839 if (info->tx_count) {
840 /* send accumulated data from send_char() */
841 if (!tx_load(info, info->tx_buf, info->tx_count))
846 if (tx_load(info, buf, count))
850 spin_unlock_irqrestore(&info->lock, flags);
851 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
855 static int put_char(struct tty_struct *tty, unsigned char ch)
857 struct slgt_info *info = tty->driver_data;
861 if (sanity_check(info, tty->name, "put_char"))
863 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
866 spin_lock_irqsave(&info->lock,flags);
867 if (info->tx_count < info->max_frame_size) {
868 info->tx_buf[info->tx_count++] = ch;
871 spin_unlock_irqrestore(&info->lock,flags);
875 static void send_xchar(struct tty_struct *tty, char ch)
877 struct slgt_info *info = tty->driver_data;
880 if (sanity_check(info, tty->name, "send_xchar"))
882 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
885 spin_lock_irqsave(&info->lock,flags);
886 if (!info->tx_enabled)
888 spin_unlock_irqrestore(&info->lock,flags);
892 static void wait_until_sent(struct tty_struct *tty, int timeout)
894 struct slgt_info *info = tty->driver_data;
895 unsigned long orig_jiffies, char_time;
899 if (sanity_check(info, tty->name, "wait_until_sent"))
901 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
902 if (!(info->port.flags & ASYNC_INITIALIZED))
905 orig_jiffies = jiffies;
907 /* Set check interval to 1/5 of estimated time to
908 * send a character, and make it at least 1. The check
909 * interval should also be less than the timeout.
910 * Note: use tight timings here to satisfy the NIST-PCTS.
913 if (info->params.data_rate) {
914 char_time = info->timeout/(32 * 5);
921 char_time = min_t(unsigned long, char_time, timeout);
923 while (info->tx_active) {
924 msleep_interruptible(jiffies_to_msecs(char_time));
925 if (signal_pending(current))
927 if (timeout && time_after(jiffies, orig_jiffies + timeout))
931 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
934 static int write_room(struct tty_struct *tty)
936 struct slgt_info *info = tty->driver_data;
939 if (sanity_check(info, tty->name, "write_room"))
941 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
942 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
946 static void flush_chars(struct tty_struct *tty)
948 struct slgt_info *info = tty->driver_data;
951 if (sanity_check(info, tty->name, "flush_chars"))
953 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
955 if (info->tx_count <= 0 || tty->stopped ||
956 tty->hw_stopped || !info->tx_buf)
959 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
961 spin_lock_irqsave(&info->lock,flags);
962 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
964 spin_unlock_irqrestore(&info->lock,flags);
967 static void flush_buffer(struct tty_struct *tty)
969 struct slgt_info *info = tty->driver_data;
972 if (sanity_check(info, tty->name, "flush_buffer"))
974 DBGINFO(("%s flush_buffer\n", info->device_name));
976 spin_lock_irqsave(&info->lock, flags);
978 spin_unlock_irqrestore(&info->lock, flags);
984 * throttle (stop) transmitter
986 static void tx_hold(struct tty_struct *tty)
988 struct slgt_info *info = tty->driver_data;
991 if (sanity_check(info, tty->name, "tx_hold"))
993 DBGINFO(("%s tx_hold\n", info->device_name));
994 spin_lock_irqsave(&info->lock,flags);
995 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
997 spin_unlock_irqrestore(&info->lock,flags);
1001 * release (start) transmitter
1003 static void tx_release(struct tty_struct *tty)
1005 struct slgt_info *info = tty->driver_data;
1006 unsigned long flags;
1008 if (sanity_check(info, tty->name, "tx_release"))
1010 DBGINFO(("%s tx_release\n", info->device_name));
1011 spin_lock_irqsave(&info->lock, flags);
1012 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1014 spin_unlock_irqrestore(&info->lock, flags);
1018 * Service an IOCTL request
1022 * tty pointer to tty instance data
1023 * file pointer to associated file object for device
1024 * cmd IOCTL command code
1025 * arg command argument/context
1027 * Return 0 if success, otherwise error code
1029 static int ioctl(struct tty_struct *tty, struct file *file,
1030 unsigned int cmd, unsigned long arg)
1032 struct slgt_info *info = tty->driver_data;
1033 struct mgsl_icount cnow; /* kernel counter temps */
1034 struct serial_icounter_struct __user *p_cuser; /* user space */
1035 unsigned long flags;
1036 void __user *argp = (void __user *)arg;
1039 if (sanity_check(info, tty->name, "ioctl"))
1041 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1043 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1044 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1045 if (tty->flags & (1 << TTY_IO_ERROR))
1050 case MGSL_IOCWAITEVENT:
1051 return wait_mgsl_event(info, argp);
1053 return modem_input_wait(info,(int)arg);
1055 spin_lock_irqsave(&info->lock,flags);
1056 cnow = info->icount;
1057 spin_unlock_irqrestore(&info->lock,flags);
1059 if (put_user(cnow.cts, &p_cuser->cts) ||
1060 put_user(cnow.dsr, &p_cuser->dsr) ||
1061 put_user(cnow.rng, &p_cuser->rng) ||
1062 put_user(cnow.dcd, &p_cuser->dcd) ||
1063 put_user(cnow.rx, &p_cuser->rx) ||
1064 put_user(cnow.tx, &p_cuser->tx) ||
1065 put_user(cnow.frame, &p_cuser->frame) ||
1066 put_user(cnow.overrun, &p_cuser->overrun) ||
1067 put_user(cnow.parity, &p_cuser->parity) ||
1068 put_user(cnow.brk, &p_cuser->brk) ||
1069 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1073 return set_gpio(info, argp);
1075 return get_gpio(info, argp);
1076 case MGSL_IOCWAITGPIO:
1077 return wait_gpio(info, argp);
1079 mutex_lock(&info->port.mutex);
1081 case MGSL_IOCGPARAMS:
1082 ret = get_params(info, argp);
1084 case MGSL_IOCSPARAMS:
1085 ret = set_params(info, argp);
1087 case MGSL_IOCGTXIDLE:
1088 ret = get_txidle(info, argp);
1090 case MGSL_IOCSTXIDLE:
1091 ret = set_txidle(info, (int)arg);
1093 case MGSL_IOCTXENABLE:
1094 ret = tx_enable(info, (int)arg);
1096 case MGSL_IOCRXENABLE:
1097 ret = rx_enable(info, (int)arg);
1099 case MGSL_IOCTXABORT:
1100 ret = tx_abort(info);
1102 case MGSL_IOCGSTATS:
1103 ret = get_stats(info, argp);
1106 ret = get_interface(info, argp);
1109 ret = set_interface(info,(int)arg);
1114 mutex_unlock(&info->port.mutex);
1119 * support for 32 bit ioctl calls on 64 bit systems
1121 #ifdef CONFIG_COMPAT
1122 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1124 struct MGSL_PARAMS32 tmp_params;
1126 DBGINFO(("%s get_params32\n", info->device_name));
1127 tmp_params.mode = (compat_ulong_t)info->params.mode;
1128 tmp_params.loopback = info->params.loopback;
1129 tmp_params.flags = info->params.flags;
1130 tmp_params.encoding = info->params.encoding;
1131 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1132 tmp_params.addr_filter = info->params.addr_filter;
1133 tmp_params.crc_type = info->params.crc_type;
1134 tmp_params.preamble_length = info->params.preamble_length;
1135 tmp_params.preamble = info->params.preamble;
1136 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1137 tmp_params.data_bits = info->params.data_bits;
1138 tmp_params.stop_bits = info->params.stop_bits;
1139 tmp_params.parity = info->params.parity;
1140 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1145 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1147 struct MGSL_PARAMS32 tmp_params;
1149 DBGINFO(("%s set_params32\n", info->device_name));
1150 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1153 spin_lock(&info->lock);
1154 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1155 info->base_clock = tmp_params.clock_speed;
1157 info->params.mode = tmp_params.mode;
1158 info->params.loopback = tmp_params.loopback;
1159 info->params.flags = tmp_params.flags;
1160 info->params.encoding = tmp_params.encoding;
1161 info->params.clock_speed = tmp_params.clock_speed;
1162 info->params.addr_filter = tmp_params.addr_filter;
1163 info->params.crc_type = tmp_params.crc_type;
1164 info->params.preamble_length = tmp_params.preamble_length;
1165 info->params.preamble = tmp_params.preamble;
1166 info->params.data_rate = tmp_params.data_rate;
1167 info->params.data_bits = tmp_params.data_bits;
1168 info->params.stop_bits = tmp_params.stop_bits;
1169 info->params.parity = tmp_params.parity;
1171 spin_unlock(&info->lock);
1178 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1179 unsigned int cmd, unsigned long arg)
1181 struct slgt_info *info = tty->driver_data;
1182 int rc = -ENOIOCTLCMD;
1184 if (sanity_check(info, tty->name, "compat_ioctl"))
1186 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1190 case MGSL_IOCSPARAMS32:
1191 rc = set_params32(info, compat_ptr(arg));
1194 case MGSL_IOCGPARAMS32:
1195 rc = get_params32(info, compat_ptr(arg));
1198 case MGSL_IOCGPARAMS:
1199 case MGSL_IOCSPARAMS:
1200 case MGSL_IOCGTXIDLE:
1201 case MGSL_IOCGSTATS:
1202 case MGSL_IOCWAITEVENT:
1206 case MGSL_IOCWAITGPIO:
1208 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1211 case MGSL_IOCSTXIDLE:
1212 case MGSL_IOCTXENABLE:
1213 case MGSL_IOCRXENABLE:
1214 case MGSL_IOCTXABORT:
1217 rc = ioctl(tty, file, cmd, arg);
1221 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1225 #define slgt_compat_ioctl NULL
1226 #endif /* ifdef CONFIG_COMPAT */
1231 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1234 unsigned long flags;
1236 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237 info->device_name, info->phys_reg_addr,
1238 info->irq_level, info->max_frame_size);
1240 /* output current serial signal states */
1241 spin_lock_irqsave(&info->lock,flags);
1243 spin_unlock_irqrestore(&info->lock,flags);
1247 if (info->signals & SerialSignal_RTS)
1248 strcat(stat_buf, "|RTS");
1249 if (info->signals & SerialSignal_CTS)
1250 strcat(stat_buf, "|CTS");
1251 if (info->signals & SerialSignal_DTR)
1252 strcat(stat_buf, "|DTR");
1253 if (info->signals & SerialSignal_DSR)
1254 strcat(stat_buf, "|DSR");
1255 if (info->signals & SerialSignal_DCD)
1256 strcat(stat_buf, "|CD");
1257 if (info->signals & SerialSignal_RI)
1258 strcat(stat_buf, "|RI");
1260 if (info->params.mode != MGSL_MODE_ASYNC) {
1261 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262 info->icount.txok, info->icount.rxok);
1263 if (info->icount.txunder)
1264 seq_printf(m, " txunder:%d", info->icount.txunder);
1265 if (info->icount.txabort)
1266 seq_printf(m, " txabort:%d", info->icount.txabort);
1267 if (info->icount.rxshort)
1268 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269 if (info->icount.rxlong)
1270 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271 if (info->icount.rxover)
1272 seq_printf(m, " rxover:%d", info->icount.rxover);
1273 if (info->icount.rxcrc)
1274 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1276 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277 info->icount.tx, info->icount.rx);
1278 if (info->icount.frame)
1279 seq_printf(m, " fe:%d", info->icount.frame);
1280 if (info->icount.parity)
1281 seq_printf(m, " pe:%d", info->icount.parity);
1282 if (info->icount.brk)
1283 seq_printf(m, " brk:%d", info->icount.brk);
1284 if (info->icount.overrun)
1285 seq_printf(m, " oe:%d", info->icount.overrun);
1288 /* Append serial signal status to end */
1289 seq_printf(m, " %s\n", stat_buf+1);
1291 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292 info->tx_active,info->bh_requested,info->bh_running,
1296 /* Called to print information about devices
1298 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1300 struct slgt_info *info;
1302 seq_puts(m, "synclink_gt driver\n");
1304 info = slgt_device_list;
1307 info = info->next_device;
1312 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1314 return single_open(file, synclink_gt_proc_show, NULL);
1317 static const struct file_operations synclink_gt_proc_fops = {
1318 .owner = THIS_MODULE,
1319 .open = synclink_gt_proc_open,
1321 .llseek = seq_lseek,
1322 .release = single_release,
1326 * return count of bytes in transmit buffer
1328 static int chars_in_buffer(struct tty_struct *tty)
1330 struct slgt_info *info = tty->driver_data;
1332 if (sanity_check(info, tty->name, "chars_in_buffer"))
1334 count = tbuf_bytes(info);
1335 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1340 * signal remote device to throttle send data (our receive data)
1342 static void throttle(struct tty_struct * tty)
1344 struct slgt_info *info = tty->driver_data;
1345 unsigned long flags;
1347 if (sanity_check(info, tty->name, "throttle"))
1349 DBGINFO(("%s throttle\n", info->device_name));
1351 send_xchar(tty, STOP_CHAR(tty));
1352 if (tty->termios->c_cflag & CRTSCTS) {
1353 spin_lock_irqsave(&info->lock,flags);
1354 info->signals &= ~SerialSignal_RTS;
1356 spin_unlock_irqrestore(&info->lock,flags);
1361 * signal remote device to stop throttling send data (our receive data)
1363 static void unthrottle(struct tty_struct * tty)
1365 struct slgt_info *info = tty->driver_data;
1366 unsigned long flags;
1368 if (sanity_check(info, tty->name, "unthrottle"))
1370 DBGINFO(("%s unthrottle\n", info->device_name));
1375 send_xchar(tty, START_CHAR(tty));
1377 if (tty->termios->c_cflag & CRTSCTS) {
1378 spin_lock_irqsave(&info->lock,flags);
1379 info->signals |= SerialSignal_RTS;
1381 spin_unlock_irqrestore(&info->lock,flags);
1386 * set or clear transmit break condition
1387 * break_state -1=set break condition, 0=clear
1389 static int set_break(struct tty_struct *tty, int break_state)
1391 struct slgt_info *info = tty->driver_data;
1392 unsigned short value;
1393 unsigned long flags;
1395 if (sanity_check(info, tty->name, "set_break"))
1397 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1399 spin_lock_irqsave(&info->lock,flags);
1400 value = rd_reg16(info, TCR);
1401 if (break_state == -1)
1405 wr_reg16(info, TCR, value);
1406 spin_unlock_irqrestore(&info->lock,flags);
1410 #if SYNCLINK_GENERIC_HDLC
1413 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414 * set encoding and frame check sequence (FCS) options
1416 * dev pointer to network device structure
1417 * encoding serial encoding setting
1418 * parity FCS setting
1420 * returns 0 if success, otherwise error code
1422 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423 unsigned short parity)
1425 struct slgt_info *info = dev_to_port(dev);
1426 unsigned char new_encoding;
1427 unsigned short new_crctype;
1429 /* return error if TTY interface open */
1430 if (info->port.count)
1433 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1437 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1438 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442 default: return -EINVAL;
1447 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1448 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450 default: return -EINVAL;
1453 info->params.encoding = new_encoding;
1454 info->params.crc_type = new_crctype;
1456 /* if network interface up, reprogram hardware */
1464 * called by generic HDLC layer to send frame
1466 * skb socket buffer containing HDLC frame
1467 * dev pointer to network device structure
1469 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470 struct net_device *dev)
1472 struct slgt_info *info = dev_to_port(dev);
1473 unsigned long flags;
1475 DBGINFO(("%s hdlc_xmit\n", dev->name));
1478 return NETDEV_TX_OK;
1480 /* stop sending until this frame completes */
1481 netif_stop_queue(dev);
1483 /* update network statistics */
1484 dev->stats.tx_packets++;
1485 dev->stats.tx_bytes += skb->len;
1487 /* save start time for transmit timeout detection */
1488 dev->trans_start = jiffies;
1490 spin_lock_irqsave(&info->lock, flags);
1491 tx_load(info, skb->data, skb->len);
1492 spin_unlock_irqrestore(&info->lock, flags);
1494 /* done with socket buffer, so free it */
1497 return NETDEV_TX_OK;
1501 * called by network layer when interface enabled
1502 * claim resources and initialize hardware
1504 * dev pointer to network device structure
1506 * returns 0 if success, otherwise error code
1508 static int hdlcdev_open(struct net_device *dev)
1510 struct slgt_info *info = dev_to_port(dev);
1512 unsigned long flags;
1514 if (!try_module_get(THIS_MODULE))
1517 DBGINFO(("%s hdlcdev_open\n", dev->name));
1519 /* generic HDLC layer open processing */
1520 if ((rc = hdlc_open(dev)))
1523 /* arbitrate between network and tty opens */
1524 spin_lock_irqsave(&info->netlock, flags);
1525 if (info->port.count != 0 || info->netcount != 0) {
1526 DBGINFO(("%s hdlc_open busy\n", dev->name));
1527 spin_unlock_irqrestore(&info->netlock, flags);
1531 spin_unlock_irqrestore(&info->netlock, flags);
1533 /* claim resources and init adapter */
1534 if ((rc = startup(info)) != 0) {
1535 spin_lock_irqsave(&info->netlock, flags);
1537 spin_unlock_irqrestore(&info->netlock, flags);
1541 /* assert DTR and RTS, apply hardware settings */
1542 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1545 /* enable network layer transmit */
1546 dev->trans_start = jiffies;
1547 netif_start_queue(dev);
1549 /* inform generic HDLC layer of current DCD status */
1550 spin_lock_irqsave(&info->lock, flags);
1552 spin_unlock_irqrestore(&info->lock, flags);
1553 if (info->signals & SerialSignal_DCD)
1554 netif_carrier_on(dev);
1556 netif_carrier_off(dev);
1561 * called by network layer when interface is disabled
1562 * shutdown hardware and release resources
1564 * dev pointer to network device structure
1566 * returns 0 if success, otherwise error code
1568 static int hdlcdev_close(struct net_device *dev)
1570 struct slgt_info *info = dev_to_port(dev);
1571 unsigned long flags;
1573 DBGINFO(("%s hdlcdev_close\n", dev->name));
1575 netif_stop_queue(dev);
1577 /* shutdown adapter and release resources */
1582 spin_lock_irqsave(&info->netlock, flags);
1584 spin_unlock_irqrestore(&info->netlock, flags);
1586 module_put(THIS_MODULE);
1591 * called by network layer to process IOCTL call to network device
1593 * dev pointer to network device structure
1594 * ifr pointer to network interface request structure
1595 * cmd IOCTL command code
1597 * returns 0 if success, otherwise error code
1599 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1601 const size_t size = sizeof(sync_serial_settings);
1602 sync_serial_settings new_line;
1603 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1604 struct slgt_info *info = dev_to_port(dev);
1607 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1609 /* return error if TTY interface open */
1610 if (info->port.count)
1613 if (cmd != SIOCWANDEV)
1614 return hdlc_ioctl(dev, ifr, cmd);
1616 switch(ifr->ifr_settings.type) {
1617 case IF_GET_IFACE: /* return current sync_serial_settings */
1619 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1620 if (ifr->ifr_settings.size < size) {
1621 ifr->ifr_settings.size = size; /* data size wanted */
1625 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1626 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1627 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1628 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1631 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1632 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1633 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1634 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1635 default: new_line.clock_type = CLOCK_DEFAULT;
1638 new_line.clock_rate = info->params.clock_speed;
1639 new_line.loopback = info->params.loopback ? 1:0;
1641 if (copy_to_user(line, &new_line, size))
1645 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1647 if(!capable(CAP_NET_ADMIN))
1649 if (copy_from_user(&new_line, line, size))
1652 switch (new_line.clock_type)
1654 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1655 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1656 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1657 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1658 case CLOCK_DEFAULT: flags = info->params.flags &
1659 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1660 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1661 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1662 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1663 default: return -EINVAL;
1666 if (new_line.loopback != 0 && new_line.loopback != 1)
1669 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1670 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1671 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1672 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1673 info->params.flags |= flags;
1675 info->params.loopback = new_line.loopback;
1677 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1678 info->params.clock_speed = new_line.clock_rate;
1680 info->params.clock_speed = 0;
1682 /* if network interface up, reprogram hardware */
1688 return hdlc_ioctl(dev, ifr, cmd);
1693 * called by network layer when transmit timeout is detected
1695 * dev pointer to network device structure
1697 static void hdlcdev_tx_timeout(struct net_device *dev)
1699 struct slgt_info *info = dev_to_port(dev);
1700 unsigned long flags;
1702 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1704 dev->stats.tx_errors++;
1705 dev->stats.tx_aborted_errors++;
1707 spin_lock_irqsave(&info->lock,flags);
1709 spin_unlock_irqrestore(&info->lock,flags);
1711 netif_wake_queue(dev);
1715 * called by device driver when transmit completes
1716 * reenable network layer transmit if stopped
1718 * info pointer to device instance information
1720 static void hdlcdev_tx_done(struct slgt_info *info)
1722 if (netif_queue_stopped(info->netdev))
1723 netif_wake_queue(info->netdev);
1727 * called by device driver when frame received
1728 * pass frame to network layer
1730 * info pointer to device instance information
1731 * buf pointer to buffer contianing frame data
1732 * size count of data bytes in buf
1734 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1736 struct sk_buff *skb = dev_alloc_skb(size);
1737 struct net_device *dev = info->netdev;
1739 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1742 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1743 dev->stats.rx_dropped++;
1747 memcpy(skb_put(skb, size), buf, size);
1749 skb->protocol = hdlc_type_trans(skb, dev);
1751 dev->stats.rx_packets++;
1752 dev->stats.rx_bytes += size;
1757 static const struct net_device_ops hdlcdev_ops = {
1758 .ndo_open = hdlcdev_open,
1759 .ndo_stop = hdlcdev_close,
1760 .ndo_change_mtu = hdlc_change_mtu,
1761 .ndo_start_xmit = hdlc_start_xmit,
1762 .ndo_do_ioctl = hdlcdev_ioctl,
1763 .ndo_tx_timeout = hdlcdev_tx_timeout,
1767 * called by device driver when adding device instance
1768 * do generic HDLC initialization
1770 * info pointer to device instance information
1772 * returns 0 if success, otherwise error code
1774 static int hdlcdev_init(struct slgt_info *info)
1777 struct net_device *dev;
1780 /* allocate and initialize network and HDLC layer objects */
1782 if (!(dev = alloc_hdlcdev(info))) {
1783 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1787 /* for network layer reporting purposes only */
1788 dev->mem_start = info->phys_reg_addr;
1789 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1790 dev->irq = info->irq_level;
1792 /* network layer callbacks and settings */
1793 dev->netdev_ops = &hdlcdev_ops;
1794 dev->watchdog_timeo = 10 * HZ;
1795 dev->tx_queue_len = 50;
1797 /* generic HDLC layer callbacks and settings */
1798 hdlc = dev_to_hdlc(dev);
1799 hdlc->attach = hdlcdev_attach;
1800 hdlc->xmit = hdlcdev_xmit;
1802 /* register objects with HDLC layer */
1803 if ((rc = register_hdlc_device(dev))) {
1804 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1814 * called by device driver when removing device instance
1815 * do generic HDLC cleanup
1817 * info pointer to device instance information
1819 static void hdlcdev_exit(struct slgt_info *info)
1821 unregister_hdlc_device(info->netdev);
1822 free_netdev(info->netdev);
1823 info->netdev = NULL;
1826 #endif /* ifdef CONFIG_HDLC */
1829 * get async data from rx DMA buffers
1831 static void rx_async(struct slgt_info *info)
1833 struct tty_struct *tty = info->port.tty;
1834 struct mgsl_icount *icount = &info->icount;
1835 unsigned int start, end;
1837 unsigned char status;
1838 struct slgt_desc *bufs = info->rbufs;
1844 start = end = info->rbuf_current;
1846 while(desc_complete(bufs[end])) {
1847 count = desc_count(bufs[end]) - info->rbuf_index;
1848 p = bufs[end].buf + info->rbuf_index;
1850 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1851 DBGDATA(info, p, count, "rx");
1853 for(i=0 ; i < count; i+=2, p+=2) {
1859 if ((status = *(p+1) & (BIT1 + BIT0))) {
1862 else if (status & BIT0)
1864 /* discard char if tty control flags say so */
1865 if (status & info->ignore_status_mask)
1869 else if (status & BIT0)
1873 tty_insert_flip_char(tty, ch, stat);
1879 /* receive buffer not completed */
1880 info->rbuf_index += i;
1881 mod_timer(&info->rx_timer, jiffies + 1);
1885 info->rbuf_index = 0;
1886 free_rbufs(info, end, end);
1888 if (++end == info->rbuf_count)
1891 /* if entire list searched then no frame available */
1897 tty_flip_buffer_push(tty);
1901 * return next bottom half action to perform
1903 static int bh_action(struct slgt_info *info)
1905 unsigned long flags;
1908 spin_lock_irqsave(&info->lock,flags);
1910 if (info->pending_bh & BH_RECEIVE) {
1911 info->pending_bh &= ~BH_RECEIVE;
1913 } else if (info->pending_bh & BH_TRANSMIT) {
1914 info->pending_bh &= ~BH_TRANSMIT;
1916 } else if (info->pending_bh & BH_STATUS) {
1917 info->pending_bh &= ~BH_STATUS;
1920 /* Mark BH routine as complete */
1921 info->bh_running = false;
1922 info->bh_requested = false;
1926 spin_unlock_irqrestore(&info->lock,flags);
1932 * perform bottom half processing
1934 static void bh_handler(struct work_struct *work)
1936 struct slgt_info *info = container_of(work, struct slgt_info, task);
1941 info->bh_running = true;
1943 while((action = bh_action(info))) {
1946 DBGBH(("%s bh receive\n", info->device_name));
1947 switch(info->params.mode) {
1948 case MGSL_MODE_ASYNC:
1951 case MGSL_MODE_HDLC:
1952 while(rx_get_frame(info));
1955 case MGSL_MODE_MONOSYNC:
1956 case MGSL_MODE_BISYNC:
1957 while(rx_get_buf(info));
1960 /* restart receiver if rx DMA buffers exhausted */
1961 if (info->rx_restart)
1968 DBGBH(("%s bh status\n", info->device_name));
1969 info->ri_chkcount = 0;
1970 info->dsr_chkcount = 0;
1971 info->dcd_chkcount = 0;
1972 info->cts_chkcount = 0;
1975 DBGBH(("%s unknown action\n", info->device_name));
1979 DBGBH(("%s bh_handler exit\n", info->device_name));
1982 static void bh_transmit(struct slgt_info *info)
1984 struct tty_struct *tty = info->port.tty;
1986 DBGBH(("%s bh_transmit\n", info->device_name));
1991 static void dsr_change(struct slgt_info *info, unsigned short status)
1993 if (status & BIT3) {
1994 info->signals |= SerialSignal_DSR;
1995 info->input_signal_events.dsr_up++;
1997 info->signals &= ~SerialSignal_DSR;
1998 info->input_signal_events.dsr_down++;
2000 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2001 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2002 slgt_irq_off(info, IRQ_DSR);
2006 wake_up_interruptible(&info->status_event_wait_q);
2007 wake_up_interruptible(&info->event_wait_q);
2008 info->pending_bh |= BH_STATUS;
2011 static void cts_change(struct slgt_info *info, unsigned short status)
2013 if (status & BIT2) {
2014 info->signals |= SerialSignal_CTS;
2015 info->input_signal_events.cts_up++;
2017 info->signals &= ~SerialSignal_CTS;
2018 info->input_signal_events.cts_down++;
2020 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2021 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2022 slgt_irq_off(info, IRQ_CTS);
2026 wake_up_interruptible(&info->status_event_wait_q);
2027 wake_up_interruptible(&info->event_wait_q);
2028 info->pending_bh |= BH_STATUS;
2030 if (info->port.flags & ASYNC_CTS_FLOW) {
2031 if (info->port.tty) {
2032 if (info->port.tty->hw_stopped) {
2033 if (info->signals & SerialSignal_CTS) {
2034 info->port.tty->hw_stopped = 0;
2035 info->pending_bh |= BH_TRANSMIT;
2039 if (!(info->signals & SerialSignal_CTS))
2040 info->port.tty->hw_stopped = 1;
2046 static void dcd_change(struct slgt_info *info, unsigned short status)
2048 if (status & BIT1) {
2049 info->signals |= SerialSignal_DCD;
2050 info->input_signal_events.dcd_up++;
2052 info->signals &= ~SerialSignal_DCD;
2053 info->input_signal_events.dcd_down++;
2055 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2056 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2057 slgt_irq_off(info, IRQ_DCD);
2061 #if SYNCLINK_GENERIC_HDLC
2062 if (info->netcount) {
2063 if (info->signals & SerialSignal_DCD)
2064 netif_carrier_on(info->netdev);
2066 netif_carrier_off(info->netdev);
2069 wake_up_interruptible(&info->status_event_wait_q);
2070 wake_up_interruptible(&info->event_wait_q);
2071 info->pending_bh |= BH_STATUS;
2073 if (info->port.flags & ASYNC_CHECK_CD) {
2074 if (info->signals & SerialSignal_DCD)
2075 wake_up_interruptible(&info->port.open_wait);
2078 tty_hangup(info->port.tty);
2083 static void ri_change(struct slgt_info *info, unsigned short status)
2085 if (status & BIT0) {
2086 info->signals |= SerialSignal_RI;
2087 info->input_signal_events.ri_up++;
2089 info->signals &= ~SerialSignal_RI;
2090 info->input_signal_events.ri_down++;
2092 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2093 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2094 slgt_irq_off(info, IRQ_RI);
2098 wake_up_interruptible(&info->status_event_wait_q);
2099 wake_up_interruptible(&info->event_wait_q);
2100 info->pending_bh |= BH_STATUS;
2103 static void isr_rxdata(struct slgt_info *info)
2105 unsigned int count = info->rbuf_fill_count;
2106 unsigned int i = info->rbuf_fill_index;
2109 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2110 reg = rd_reg16(info, RDR);
2111 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2112 if (desc_complete(info->rbufs[i])) {
2113 /* all buffers full */
2115 info->rx_restart = 1;
2118 info->rbufs[i].buf[count++] = (unsigned char)reg;
2119 /* async mode saves status byte to buffer for each data byte */
2120 if (info->params.mode == MGSL_MODE_ASYNC)
2121 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2122 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2123 /* buffer full or end of frame */
2124 set_desc_count(info->rbufs[i], count);
2125 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2126 info->rbuf_fill_count = count = 0;
2127 if (++i == info->rbuf_count)
2129 info->pending_bh |= BH_RECEIVE;
2133 info->rbuf_fill_index = i;
2134 info->rbuf_fill_count = count;
2137 static void isr_serial(struct slgt_info *info)
2139 unsigned short status = rd_reg16(info, SSR);
2141 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2143 wr_reg16(info, SSR, status); /* clear pending */
2145 info->irq_occurred = true;
2147 if (info->params.mode == MGSL_MODE_ASYNC) {
2148 if (status & IRQ_TXIDLE) {
2149 if (info->tx_active)
2150 isr_txeom(info, status);
2152 if (info->rx_pio && (status & IRQ_RXDATA))
2154 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2156 /* process break detection if tty control allows */
2157 if (info->port.tty) {
2158 if (!(status & info->ignore_status_mask)) {
2159 if (info->read_status_mask & MASK_BREAK) {
2160 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2161 if (info->port.flags & ASYNC_SAK)
2162 do_SAK(info->port.tty);
2168 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2169 isr_txeom(info, status);
2170 if (info->rx_pio && (status & IRQ_RXDATA))
2172 if (status & IRQ_RXIDLE) {
2173 if (status & RXIDLE)
2174 info->icount.rxidle++;
2176 info->icount.exithunt++;
2177 wake_up_interruptible(&info->event_wait_q);
2180 if (status & IRQ_RXOVER)
2184 if (status & IRQ_DSR)
2185 dsr_change(info, status);
2186 if (status & IRQ_CTS)
2187 cts_change(info, status);
2188 if (status & IRQ_DCD)
2189 dcd_change(info, status);
2190 if (status & IRQ_RI)
2191 ri_change(info, status);
2194 static void isr_rdma(struct slgt_info *info)
2196 unsigned int status = rd_reg32(info, RDCSR);
2198 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2200 /* RDCSR (rx DMA control/status)
2203 * 06 save status byte to DMA buffer
2205 * 04 eol (end of list)
2206 * 03 eob (end of buffer)
2211 wr_reg32(info, RDCSR, status); /* clear pending */
2213 if (status & (BIT5 + BIT4)) {
2214 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2215 info->rx_restart = true;
2217 info->pending_bh |= BH_RECEIVE;
2220 static void isr_tdma(struct slgt_info *info)
2222 unsigned int status = rd_reg32(info, TDCSR);
2224 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2226 /* TDCSR (tx DMA control/status)
2230 * 04 eol (end of list)
2231 * 03 eob (end of buffer)
2236 wr_reg32(info, TDCSR, status); /* clear pending */
2238 if (status & (BIT5 + BIT4 + BIT3)) {
2239 // another transmit buffer has completed
2240 // run bottom half to get more send data from user
2241 info->pending_bh |= BH_TRANSMIT;
2246 * return true if there are unsent tx DMA buffers, otherwise false
2248 * if there are unsent buffers then info->tbuf_start
2249 * is set to index of first unsent buffer
2251 static bool unsent_tbufs(struct slgt_info *info)
2253 unsigned int i = info->tbuf_current;
2257 * search backwards from last loaded buffer (precedes tbuf_current)
2258 * for first unsent buffer (desc_count > 0)
2265 i = info->tbuf_count - 1;
2266 if (!desc_count(info->tbufs[i]))
2268 info->tbuf_start = i;
2270 } while (i != info->tbuf_current);
2275 static void isr_txeom(struct slgt_info *info, unsigned short status)
2277 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2279 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2281 if (status & IRQ_TXUNDER) {
2282 unsigned short val = rd_reg16(info, TCR);
2283 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2284 wr_reg16(info, TCR, val); /* clear reset bit */
2287 if (info->tx_active) {
2288 if (info->params.mode != MGSL_MODE_ASYNC) {
2289 if (status & IRQ_TXUNDER)
2290 info->icount.txunder++;
2291 else if (status & IRQ_TXIDLE)
2292 info->icount.txok++;
2295 if (unsent_tbufs(info)) {
2297 update_tx_timer(info);
2300 info->tx_active = false;
2302 del_timer(&info->tx_timer);
2304 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2305 info->signals &= ~SerialSignal_RTS;
2306 info->drop_rts_on_tx_done = false;
2310 #if SYNCLINK_GENERIC_HDLC
2312 hdlcdev_tx_done(info);
2316 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2320 info->pending_bh |= BH_TRANSMIT;
2325 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2327 struct cond_wait *w, *prev;
2329 /* wake processes waiting for specific transitions */
2330 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2331 if (w->data & changed) {
2333 wake_up_interruptible(&w->q);
2335 prev->next = w->next;
2337 info->gpio_wait_q = w->next;
2343 /* interrupt service routine
2345 * irq interrupt number
2346 * dev_id device ID supplied during interrupt registration
2348 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2350 struct slgt_info *info = dev_id;
2354 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2356 spin_lock(&info->lock);
2358 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2359 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2360 info->irq_occurred = true;
2361 for(i=0; i < info->port_count ; i++) {
2362 if (info->port_array[i] == NULL)
2364 if (gsr & (BIT8 << i))
2365 isr_serial(info->port_array[i]);
2366 if (gsr & (BIT16 << (i*2)))
2367 isr_rdma(info->port_array[i]);
2368 if (gsr & (BIT17 << (i*2)))
2369 isr_tdma(info->port_array[i]);
2373 if (info->gpio_present) {
2375 unsigned int changed;
2376 while ((changed = rd_reg32(info, IOSR)) != 0) {
2377 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2378 /* read latched state of GPIO signals */
2379 state = rd_reg32(info, IOVR);
2380 /* clear pending GPIO interrupt bits */
2381 wr_reg32(info, IOSR, changed);
2382 for (i=0 ; i < info->port_count ; i++) {
2383 if (info->port_array[i] != NULL)
2384 isr_gpio(info->port_array[i], changed, state);
2389 for(i=0; i < info->port_count ; i++) {
2390 struct slgt_info *port = info->port_array[i];
2392 if (port && (port->port.count || port->netcount) &&
2393 port->pending_bh && !port->bh_running &&
2394 !port->bh_requested) {
2395 DBGISR(("%s bh queued\n", port->device_name));
2396 schedule_work(&port->task);
2397 port->bh_requested = true;
2401 spin_unlock(&info->lock);
2403 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2407 static int startup(struct slgt_info *info)
2409 DBGINFO(("%s startup\n", info->device_name));
2411 if (info->port.flags & ASYNC_INITIALIZED)
2414 if (!info->tx_buf) {
2415 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2416 if (!info->tx_buf) {
2417 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2422 info->pending_bh = 0;
2424 memset(&info->icount, 0, sizeof(info->icount));
2426 /* program hardware for current parameters */
2427 change_params(info);
2430 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2432 info->port.flags |= ASYNC_INITIALIZED;
2438 * called by close() and hangup() to shutdown hardware
2440 static void shutdown(struct slgt_info *info)
2442 unsigned long flags;
2444 if (!(info->port.flags & ASYNC_INITIALIZED))
2447 DBGINFO(("%s shutdown\n", info->device_name));
2449 /* clear status wait queue because status changes */
2450 /* can't happen after shutting down the hardware */
2451 wake_up_interruptible(&info->status_event_wait_q);
2452 wake_up_interruptible(&info->event_wait_q);
2454 del_timer_sync(&info->tx_timer);
2455 del_timer_sync(&info->rx_timer);
2457 kfree(info->tx_buf);
2458 info->tx_buf = NULL;
2460 spin_lock_irqsave(&info->lock,flags);
2465 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2467 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2468 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2472 flush_cond_wait(&info->gpio_wait_q);
2474 spin_unlock_irqrestore(&info->lock,flags);
2477 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2479 info->port.flags &= ~ASYNC_INITIALIZED;
2482 static void program_hw(struct slgt_info *info)
2484 unsigned long flags;
2486 spin_lock_irqsave(&info->lock,flags);
2491 if (info->params.mode != MGSL_MODE_ASYNC ||
2499 info->dcd_chkcount = 0;
2500 info->cts_chkcount = 0;
2501 info->ri_chkcount = 0;
2502 info->dsr_chkcount = 0;
2504 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2507 if (info->netcount ||
2508 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2511 spin_unlock_irqrestore(&info->lock,flags);
2515 * reconfigure adapter based on new parameters
2517 static void change_params(struct slgt_info *info)
2522 if (!info->port.tty || !info->port.tty->termios)
2524 DBGINFO(("%s change_params\n", info->device_name));
2526 cflag = info->port.tty->termios->c_cflag;
2528 /* if B0 rate (hangup) specified then negate DTR and RTS */
2529 /* otherwise assert DTR and RTS */
2531 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2533 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2535 /* byte size and parity */
2537 switch (cflag & CSIZE) {
2538 case CS5: info->params.data_bits = 5; break;
2539 case CS6: info->params.data_bits = 6; break;
2540 case CS7: info->params.data_bits = 7; break;
2541 case CS8: info->params.data_bits = 8; break;
2542 default: info->params.data_bits = 7; break;
2545 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2548 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2550 info->params.parity = ASYNC_PARITY_NONE;
2552 /* calculate number of jiffies to transmit a full
2553 * FIFO (32 bytes) at specified data rate
2555 bits_per_char = info->params.data_bits +
2556 info->params.stop_bits + 1;
2558 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2560 if (info->params.data_rate) {
2561 info->timeout = (32*HZ*bits_per_char) /
2562 info->params.data_rate;
2564 info->timeout += HZ/50; /* Add .02 seconds of slop */
2566 if (cflag & CRTSCTS)
2567 info->port.flags |= ASYNC_CTS_FLOW;
2569 info->port.flags &= ~ASYNC_CTS_FLOW;
2572 info->port.flags &= ~ASYNC_CHECK_CD;
2574 info->port.flags |= ASYNC_CHECK_CD;
2576 /* process tty input control flags */
2578 info->read_status_mask = IRQ_RXOVER;
2579 if (I_INPCK(info->port.tty))
2580 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2581 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2582 info->read_status_mask |= MASK_BREAK;
2583 if (I_IGNPAR(info->port.tty))
2584 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2585 if (I_IGNBRK(info->port.tty)) {
2586 info->ignore_status_mask |= MASK_BREAK;
2587 /* If ignoring parity and break indicators, ignore
2588 * overruns too. (For real raw support).
2590 if (I_IGNPAR(info->port.tty))
2591 info->ignore_status_mask |= MASK_OVERRUN;
2597 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2599 DBGINFO(("%s get_stats\n", info->device_name));
2601 memset(&info->icount, 0, sizeof(info->icount));
2603 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2609 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2611 DBGINFO(("%s get_params\n", info->device_name));
2612 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2617 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2619 unsigned long flags;
2620 MGSL_PARAMS tmp_params;
2622 DBGINFO(("%s set_params\n", info->device_name));
2623 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2626 spin_lock_irqsave(&info->lock, flags);
2627 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2628 info->base_clock = tmp_params.clock_speed;
2630 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2631 spin_unlock_irqrestore(&info->lock, flags);
2638 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2640 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2641 if (put_user(info->idle_mode, idle_mode))
2646 static int set_txidle(struct slgt_info *info, int idle_mode)
2648 unsigned long flags;
2649 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2650 spin_lock_irqsave(&info->lock,flags);
2651 info->idle_mode = idle_mode;
2652 if (info->params.mode != MGSL_MODE_ASYNC)
2654 spin_unlock_irqrestore(&info->lock,flags);
2658 static int tx_enable(struct slgt_info *info, int enable)
2660 unsigned long flags;
2661 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2662 spin_lock_irqsave(&info->lock,flags);
2664 if (!info->tx_enabled)
2667 if (info->tx_enabled)
2670 spin_unlock_irqrestore(&info->lock,flags);
2675 * abort transmit HDLC frame
2677 static int tx_abort(struct slgt_info *info)
2679 unsigned long flags;
2680 DBGINFO(("%s tx_abort\n", info->device_name));
2681 spin_lock_irqsave(&info->lock,flags);
2683 spin_unlock_irqrestore(&info->lock,flags);
2687 static int rx_enable(struct slgt_info *info, int enable)
2689 unsigned long flags;
2690 unsigned int rbuf_fill_level;
2691 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2692 spin_lock_irqsave(&info->lock,flags);
2694 * enable[31..16] = receive DMA buffer fill level
2695 * 0 = noop (leave fill level unchanged)
2696 * fill level must be multiple of 4 and <= buffer size
2698 rbuf_fill_level = ((unsigned int)enable) >> 16;
2699 if (rbuf_fill_level) {
2700 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2701 spin_unlock_irqrestore(&info->lock, flags);
2704 info->rbuf_fill_level = rbuf_fill_level;
2705 if (rbuf_fill_level < 128)
2706 info->rx_pio = 1; /* PIO mode */
2708 info->rx_pio = 0; /* DMA mode */
2709 rx_stop(info); /* restart receiver to use new fill level */
2713 * enable[1..0] = receiver enable command
2716 * 2 = enable or force hunt mode if already enabled
2720 if (!info->rx_enabled)
2722 else if (enable == 2) {
2723 /* force hunt mode (write 1 to RCR[3]) */
2724 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2727 if (info->rx_enabled)
2730 spin_unlock_irqrestore(&info->lock,flags);
2735 * wait for specified event to occur
2737 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2739 unsigned long flags;
2742 struct mgsl_icount cprev, cnow;
2745 struct _input_signal_events oldsigs, newsigs;
2746 DECLARE_WAITQUEUE(wait, current);
2748 if (get_user(mask, mask_ptr))
2751 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2753 spin_lock_irqsave(&info->lock,flags);
2755 /* return immediately if state matches requested events */
2760 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2761 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2762 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2763 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2765 spin_unlock_irqrestore(&info->lock,flags);
2769 /* save current irq counts */
2770 cprev = info->icount;
2771 oldsigs = info->input_signal_events;
2773 /* enable hunt and idle irqs if needed */
2774 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2775 unsigned short val = rd_reg16(info, SCR);
2776 if (!(val & IRQ_RXIDLE))
2777 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2780 set_current_state(TASK_INTERRUPTIBLE);
2781 add_wait_queue(&info->event_wait_q, &wait);
2783 spin_unlock_irqrestore(&info->lock,flags);
2787 if (signal_pending(current)) {
2792 /* get current irq counts */
2793 spin_lock_irqsave(&info->lock,flags);
2794 cnow = info->icount;
2795 newsigs = info->input_signal_events;
2796 set_current_state(TASK_INTERRUPTIBLE);
2797 spin_unlock_irqrestore(&info->lock,flags);
2799 /* if no change, wait aborted for some reason */
2800 if (newsigs.dsr_up == oldsigs.dsr_up &&
2801 newsigs.dsr_down == oldsigs.dsr_down &&
2802 newsigs.dcd_up == oldsigs.dcd_up &&
2803 newsigs.dcd_down == oldsigs.dcd_down &&
2804 newsigs.cts_up == oldsigs.cts_up &&
2805 newsigs.cts_down == oldsigs.cts_down &&
2806 newsigs.ri_up == oldsigs.ri_up &&
2807 newsigs.ri_down == oldsigs.ri_down &&
2808 cnow.exithunt == cprev.exithunt &&
2809 cnow.rxidle == cprev.rxidle) {
2815 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2816 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2817 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2818 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2819 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2820 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2821 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2822 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2823 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2824 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2832 remove_wait_queue(&info->event_wait_q, &wait);
2833 set_current_state(TASK_RUNNING);
2836 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2837 spin_lock_irqsave(&info->lock,flags);
2838 if (!waitqueue_active(&info->event_wait_q)) {
2839 /* disable enable exit hunt mode/idle rcvd IRQs */
2841 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2843 spin_unlock_irqrestore(&info->lock,flags);
2847 rc = put_user(events, mask_ptr);
2851 static int get_interface(struct slgt_info *info, int __user *if_mode)
2853 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2854 if (put_user(info->if_mode, if_mode))
2859 static int set_interface(struct slgt_info *info, int if_mode)
2861 unsigned long flags;
2864 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2865 spin_lock_irqsave(&info->lock,flags);
2866 info->if_mode = if_mode;
2870 /* TCR (tx control) 07 1=RTS driver control */
2871 val = rd_reg16(info, TCR);
2872 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2876 wr_reg16(info, TCR, val);
2878 spin_unlock_irqrestore(&info->lock,flags);
2883 * set general purpose IO pin state and direction
2886 * state each bit indicates a pin state
2887 * smask set bit indicates pin state to set
2888 * dir each bit indicates a pin direction (0=input, 1=output)
2889 * dmask set bit indicates pin direction to set
2891 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2893 unsigned long flags;
2894 struct gpio_desc gpio;
2897 if (!info->gpio_present)
2899 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2901 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2902 info->device_name, gpio.state, gpio.smask,
2903 gpio.dir, gpio.dmask));
2905 spin_lock_irqsave(&info->lock,flags);
2907 data = rd_reg32(info, IODR);
2908 data |= gpio.dmask & gpio.dir;
2909 data &= ~(gpio.dmask & ~gpio.dir);
2910 wr_reg32(info, IODR, data);
2913 data = rd_reg32(info, IOVR);
2914 data |= gpio.smask & gpio.state;
2915 data &= ~(gpio.smask & ~gpio.state);
2916 wr_reg32(info, IOVR, data);
2918 spin_unlock_irqrestore(&info->lock,flags);
2924 * get general purpose IO pin state and direction
2926 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2928 struct gpio_desc gpio;
2929 if (!info->gpio_present)
2931 gpio.state = rd_reg32(info, IOVR);
2932 gpio.smask = 0xffffffff;
2933 gpio.dir = rd_reg32(info, IODR);
2934 gpio.dmask = 0xffffffff;
2935 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2937 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2938 info->device_name, gpio.state, gpio.dir));
2943 * conditional wait facility
2945 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2947 init_waitqueue_head(&w->q);
2948 init_waitqueue_entry(&w->wait, current);
2952 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2954 set_current_state(TASK_INTERRUPTIBLE);
2955 add_wait_queue(&w->q, &w->wait);
2960 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2962 struct cond_wait *w, *prev;
2963 remove_wait_queue(&cw->q, &cw->wait);
2964 set_current_state(TASK_RUNNING);
2965 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2968 prev->next = w->next;
2976 static void flush_cond_wait(struct cond_wait **head)
2978 while (*head != NULL) {
2979 wake_up_interruptible(&(*head)->q);
2980 *head = (*head)->next;
2985 * wait for general purpose I/O pin(s) to enter specified state
2988 * state - bit indicates target pin state
2989 * smask - set bit indicates watched pin
2991 * The wait ends when at least one watched pin enters the specified
2992 * state. When 0 (no error) is returned, user_gpio->state is set to the
2993 * state of all GPIO pins when the wait ends.
2995 * Note: Each pin may be a dedicated input, dedicated output, or
2996 * configurable input/output. The number and configuration of pins
2997 * varies with the specific adapter model. Only input pins (dedicated
2998 * or configured) can be monitored with this function.
3000 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3002 unsigned long flags;
3004 struct gpio_desc gpio;
3005 struct cond_wait wait;
3008 if (!info->gpio_present)
3010 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3012 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3013 info->device_name, gpio.state, gpio.smask));
3014 /* ignore output pins identified by set IODR bit */
3015 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3017 init_cond_wait(&wait, gpio.smask);
3019 spin_lock_irqsave(&info->lock, flags);
3020 /* enable interrupts for watched pins */
3021 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3022 /* get current pin states */
3023 state = rd_reg32(info, IOVR);
3025 if (gpio.smask & ~(state ^ gpio.state)) {
3026 /* already in target state */
3029 /* wait for target state */
3030 add_cond_wait(&info->gpio_wait_q, &wait);
3031 spin_unlock_irqrestore(&info->lock, flags);
3033 if (signal_pending(current))
3036 gpio.state = wait.data;
3037 spin_lock_irqsave(&info->lock, flags);
3038 remove_cond_wait(&info->gpio_wait_q, &wait);
3041 /* disable all GPIO interrupts if no waiting processes */
3042 if (info->gpio_wait_q == NULL)
3043 wr_reg32(info, IOER, 0);
3044 spin_unlock_irqrestore(&info->lock,flags);
3046 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3051 static int modem_input_wait(struct slgt_info *info,int arg)
3053 unsigned long flags;
3055 struct mgsl_icount cprev, cnow;
3056 DECLARE_WAITQUEUE(wait, current);
3058 /* save current irq counts */
3059 spin_lock_irqsave(&info->lock,flags);
3060 cprev = info->icount;
3061 add_wait_queue(&info->status_event_wait_q, &wait);
3062 set_current_state(TASK_INTERRUPTIBLE);
3063 spin_unlock_irqrestore(&info->lock,flags);
3067 if (signal_pending(current)) {
3072 /* get new irq counts */
3073 spin_lock_irqsave(&info->lock,flags);
3074 cnow = info->icount;
3075 set_current_state(TASK_INTERRUPTIBLE);
3076 spin_unlock_irqrestore(&info->lock,flags);
3078 /* if no change, wait aborted for some reason */
3079 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3080 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3085 /* check for change in caller specified modem input */
3086 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3087 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3088 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3089 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3096 remove_wait_queue(&info->status_event_wait_q, &wait);
3097 set_current_state(TASK_RUNNING);
3102 * return state of serial control and status signals
3104 static int tiocmget(struct tty_struct *tty, struct file *file)
3106 struct slgt_info *info = tty->driver_data;
3107 unsigned int result;
3108 unsigned long flags;
3110 spin_lock_irqsave(&info->lock,flags);
3112 spin_unlock_irqrestore(&info->lock,flags);
3114 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3115 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3116 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3117 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3118 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3119 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3121 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3126 * set modem control signals (DTR/RTS)
3128 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3129 * TIOCMSET = set/clear signal values
3130 * value bit mask for command
3132 static int tiocmset(struct tty_struct *tty, struct file *file,
3133 unsigned int set, unsigned int clear)
3135 struct slgt_info *info = tty->driver_data;
3136 unsigned long flags;
3138 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3140 if (set & TIOCM_RTS)
3141 info->signals |= SerialSignal_RTS;
3142 if (set & TIOCM_DTR)
3143 info->signals |= SerialSignal_DTR;
3144 if (clear & TIOCM_RTS)
3145 info->signals &= ~SerialSignal_RTS;
3146 if (clear & TIOCM_DTR)
3147 info->signals &= ~SerialSignal_DTR;
3149 spin_lock_irqsave(&info->lock,flags);
3151 spin_unlock_irqrestore(&info->lock,flags);
3155 static int carrier_raised(struct tty_port *port)
3157 unsigned long flags;
3158 struct slgt_info *info = container_of(port, struct slgt_info, port);
3160 spin_lock_irqsave(&info->lock,flags);
3162 spin_unlock_irqrestore(&info->lock,flags);
3163 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3166 static void dtr_rts(struct tty_port *port, int on)
3168 unsigned long flags;
3169 struct slgt_info *info = container_of(port, struct slgt_info, port);
3171 spin_lock_irqsave(&info->lock,flags);
3173 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3175 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3177 spin_unlock_irqrestore(&info->lock,flags);
3182 * block current process until the device is ready to open
3184 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3185 struct slgt_info *info)
3187 DECLARE_WAITQUEUE(wait, current);
3189 bool do_clocal = false;
3190 bool extra_count = false;
3191 unsigned long flags;
3193 struct tty_port *port = &info->port;
3195 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3197 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3198 /* nonblock mode is set or port is not enabled */
3199 port->flags |= ASYNC_NORMAL_ACTIVE;
3203 if (tty->termios->c_cflag & CLOCAL)
3206 /* Wait for carrier detect and the line to become
3207 * free (i.e., not in use by the callout). While we are in
3208 * this loop, port->count is dropped by one, so that
3209 * close() knows when to free things. We restore it upon
3210 * exit, either normal or abnormal.
3214 add_wait_queue(&port->open_wait, &wait);
3216 spin_lock_irqsave(&info->lock, flags);
3217 if (!tty_hung_up_p(filp)) {
3221 spin_unlock_irqrestore(&info->lock, flags);
3222 port->blocked_open++;
3225 if ((tty->termios->c_cflag & CBAUD))
3226 tty_port_raise_dtr_rts(port);
3228 set_current_state(TASK_INTERRUPTIBLE);
3230 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3231 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3232 -EAGAIN : -ERESTARTSYS;
3236 cd = tty_port_carrier_raised(port);
3238 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3241 if (signal_pending(current)) {
3242 retval = -ERESTARTSYS;
3246 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3252 set_current_state(TASK_RUNNING);
3253 remove_wait_queue(&port->open_wait, &wait);
3257 port->blocked_open--;
3260 port->flags |= ASYNC_NORMAL_ACTIVE;
3262 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3266 static int alloc_tmp_rbuf(struct slgt_info *info)
3268 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3269 if (info->tmp_rbuf == NULL)
3274 static void free_tmp_rbuf(struct slgt_info *info)
3276 kfree(info->tmp_rbuf);
3277 info->tmp_rbuf = NULL;
3281 * allocate DMA descriptor lists.
3283 static int alloc_desc(struct slgt_info *info)
3288 /* allocate memory to hold descriptor lists */
3289 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3290 if (info->bufs == NULL)
3293 memset(info->bufs, 0, DESC_LIST_SIZE);
3295 info->rbufs = (struct slgt_desc*)info->bufs;
3296 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3298 pbufs = (unsigned int)info->bufs_dma_addr;
3301 * Build circular lists of descriptors
3304 for (i=0; i < info->rbuf_count; i++) {
3305 /* physical address of this descriptor */
3306 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3308 /* physical address of next descriptor */
3309 if (i == info->rbuf_count - 1)
3310 info->rbufs[i].next = cpu_to_le32(pbufs);
3312 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3313 set_desc_count(info->rbufs[i], DMABUFSIZE);
3316 for (i=0; i < info->tbuf_count; i++) {
3317 /* physical address of this descriptor */
3318 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3320 /* physical address of next descriptor */
3321 if (i == info->tbuf_count - 1)
3322 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3324 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3330 static void free_desc(struct slgt_info *info)
3332 if (info->bufs != NULL) {
3333 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3340 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3343 for (i=0; i < count; i++) {
3344 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3346 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3351 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3354 for (i=0; i < count; i++) {
3355 if (bufs[i].buf == NULL)
3357 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3362 static int alloc_dma_bufs(struct slgt_info *info)
3364 info->rbuf_count = 32;
3365 info->tbuf_count = 32;
3367 if (alloc_desc(info) < 0 ||
3368 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3369 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3370 alloc_tmp_rbuf(info) < 0) {
3371 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3378 static void free_dma_bufs(struct slgt_info *info)
3381 free_bufs(info, info->rbufs, info->rbuf_count);
3382 free_bufs(info, info->tbufs, info->tbuf_count);
3385 free_tmp_rbuf(info);
3388 static int claim_resources(struct slgt_info *info)
3390 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3391 DBGERR(("%s reg addr conflict, addr=%08X\n",
3392 info->device_name, info->phys_reg_addr));
3393 info->init_error = DiagStatus_AddressConflict;
3397 info->reg_addr_requested = true;
3399 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3400 if (!info->reg_addr) {
3401 DBGERR(("%s cant map device registers, addr=%08X\n",
3402 info->device_name, info->phys_reg_addr));
3403 info->init_error = DiagStatus_CantAssignPciResources;
3409 release_resources(info);
3413 static void release_resources(struct slgt_info *info)
3415 if (info->irq_requested) {
3416 free_irq(info->irq_level, info);
3417 info->irq_requested = false;
3420 if (info->reg_addr_requested) {
3421 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3422 info->reg_addr_requested = false;
3425 if (info->reg_addr) {
3426 iounmap(info->reg_addr);
3427 info->reg_addr = NULL;
3431 /* Add the specified device instance data structure to the
3432 * global linked list of devices and increment the device count.
3434 static void add_device(struct slgt_info *info)
3438 info->next_device = NULL;
3439 info->line = slgt_device_count;
3440 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3442 if (info->line < MAX_DEVICES) {
3443 if (maxframe[info->line])
3444 info->max_frame_size = maxframe[info->line];
3447 slgt_device_count++;
3449 if (!slgt_device_list)
3450 slgt_device_list = info;
3452 struct slgt_info *current_dev = slgt_device_list;
3453 while(current_dev->next_device)
3454 current_dev = current_dev->next_device;
3455 current_dev->next_device = info;
3458 if (info->max_frame_size < 4096)
3459 info->max_frame_size = 4096;
3460 else if (info->max_frame_size > 65535)
3461 info->max_frame_size = 65535;
3463 switch(info->pdev->device) {
3464 case SYNCLINK_GT_DEVICE_ID:
3467 case SYNCLINK_GT2_DEVICE_ID:
3470 case SYNCLINK_GT4_DEVICE_ID:
3473 case SYNCLINK_AC_DEVICE_ID:
3475 info->params.mode = MGSL_MODE_ASYNC;
3478 devstr = "(unknown model)";
3480 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3481 devstr, info->device_name, info->phys_reg_addr,
3482 info->irq_level, info->max_frame_size);
3484 #if SYNCLINK_GENERIC_HDLC
3489 static const struct tty_port_operations slgt_port_ops = {
3490 .carrier_raised = carrier_raised,
3495 * allocate device instance structure, return NULL on failure
3497 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3499 struct slgt_info *info;
3501 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3504 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3505 driver_name, adapter_num, port_num));
3507 tty_port_init(&info->port);
3508 info->port.ops = &slgt_port_ops;
3509 info->magic = MGSL_MAGIC;
3510 INIT_WORK(&info->task, bh_handler);
3511 info->max_frame_size = 4096;
3512 info->base_clock = 14745600;
3513 info->rbuf_fill_level = DMABUFSIZE;
3514 info->port.close_delay = 5*HZ/10;
3515 info->port.closing_wait = 30*HZ;
3516 init_waitqueue_head(&info->status_event_wait_q);
3517 init_waitqueue_head(&info->event_wait_q);
3518 spin_lock_init(&info->netlock);
3519 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3520 info->idle_mode = HDLC_TXIDLE_FLAGS;
3521 info->adapter_num = adapter_num;
3522 info->port_num = port_num;
3524 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3525 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3527 /* Copy configuration info to device instance data */
3529 info->irq_level = pdev->irq;
3530 info->phys_reg_addr = pci_resource_start(pdev,0);
3532 info->bus_type = MGSL_BUS_TYPE_PCI;
3533 info->irq_flags = IRQF_SHARED;
3535 info->init_error = -1; /* assume error, set to 0 on successful init */
3541 static void device_init(int adapter_num, struct pci_dev *pdev)
3543 struct slgt_info *port_array[SLGT_MAX_PORTS];
3547 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3549 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3552 /* allocate device instances for all ports */
3553 for (i=0; i < port_count; ++i) {
3554 port_array[i] = alloc_dev(adapter_num, i, pdev);
3555 if (port_array[i] == NULL) {
3556 for (--i; i >= 0; --i)
3557 kfree(port_array[i]);
3562 /* give copy of port_array to all ports and add to device list */
3563 for (i=0; i < port_count; ++i) {
3564 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3565 add_device(port_array[i]);
3566 port_array[i]->port_count = port_count;
3567 spin_lock_init(&port_array[i]->lock);
3570 /* Allocate and claim adapter resources */
3571 if (!claim_resources(port_array[0])) {
3573 alloc_dma_bufs(port_array[0]);
3575 /* copy resource information from first port to others */
3576 for (i = 1; i < port_count; ++i) {
3577 port_array[i]->lock = port_array[0]->lock;
3578 port_array[i]->irq_level = port_array[0]->irq_level;
3579 port_array[i]->reg_addr = port_array[0]->reg_addr;
3580 alloc_dma_bufs(port_array[i]);
3583 if (request_irq(port_array[0]->irq_level,
3585 port_array[0]->irq_flags,
3586 port_array[0]->device_name,
3587 port_array[0]) < 0) {
3588 DBGERR(("%s request_irq failed IRQ=%d\n",
3589 port_array[0]->device_name,
3590 port_array[0]->irq_level));
3592 port_array[0]->irq_requested = true;
3593 adapter_test(port_array[0]);
3594 for (i=1 ; i < port_count ; i++) {
3595 port_array[i]->init_error = port_array[0]->init_error;
3596 port_array[i]->gpio_present = port_array[0]->gpio_present;
3601 for (i=0; i < port_count; ++i)
3602 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3605 static int __devinit init_one(struct pci_dev *dev,
3606 const struct pci_device_id *ent)
3608 if (pci_enable_device(dev)) {
3609 printk("error enabling pci device %p\n", dev);
3612 pci_set_master(dev);
3613 device_init(slgt_device_count, dev);
3617 static void __devexit remove_one(struct pci_dev *dev)
3621 static const struct tty_operations ops = {
3625 .put_char = put_char,
3626 .flush_chars = flush_chars,
3627 .write_room = write_room,
3628 .chars_in_buffer = chars_in_buffer,
3629 .flush_buffer = flush_buffer,
3631 .compat_ioctl = slgt_compat_ioctl,
3632 .throttle = throttle,
3633 .unthrottle = unthrottle,
3634 .send_xchar = send_xchar,
3635 .break_ctl = set_break,
3636 .wait_until_sent = wait_until_sent,
3637 .set_termios = set_termios,
3639 .start = tx_release,
3641 .tiocmget = tiocmget,
3642 .tiocmset = tiocmset,
3643 .proc_fops = &synclink_gt_proc_fops,
3646 static void slgt_cleanup(void)
3649 struct slgt_info *info;
3650 struct slgt_info *tmp;
3652 printk(KERN_INFO "unload %s\n", driver_name);
3654 if (serial_driver) {
3655 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3656 tty_unregister_device(serial_driver, info->line);
3657 if ((rc = tty_unregister_driver(serial_driver)))
3658 DBGERR(("tty_unregister_driver error=%d\n", rc));
3659 put_tty_driver(serial_driver);
3663 info = slgt_device_list;
3666 info = info->next_device;
3669 /* release devices */
3670 info = slgt_device_list;
3672 #if SYNCLINK_GENERIC_HDLC
3675 free_dma_bufs(info);
3676 free_tmp_rbuf(info);
3677 if (info->port_num == 0)
3678 release_resources(info);
3680 info = info->next_device;
3685 pci_unregister_driver(&pci_driver);
3689 * Driver initialization entry point.
3691 static int __init slgt_init(void)
3695 printk(KERN_INFO "%s\n", driver_name);
3697 serial_driver = alloc_tty_driver(MAX_DEVICES);
3698 if (!serial_driver) {
3699 printk("%s can't allocate tty driver\n", driver_name);
3703 /* Initialize the tty_driver structure */
3705 serial_driver->owner = THIS_MODULE;
3706 serial_driver->driver_name = tty_driver_name;
3707 serial_driver->name = tty_dev_prefix;
3708 serial_driver->major = ttymajor;
3709 serial_driver->minor_start = 64;
3710 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3711 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3712 serial_driver->init_termios = tty_std_termios;
3713 serial_driver->init_termios.c_cflag =
3714 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3715 serial_driver->init_termios.c_ispeed = 9600;
3716 serial_driver->init_termios.c_ospeed = 9600;
3717 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3718 tty_set_operations(serial_driver, &ops);
3719 if ((rc = tty_register_driver(serial_driver)) < 0) {
3720 DBGERR(("%s can't register serial driver\n", driver_name));
3721 put_tty_driver(serial_driver);
3722 serial_driver = NULL;
3726 printk(KERN_INFO "%s, tty major#%d\n",
3727 driver_name, serial_driver->major);
3729 slgt_device_count = 0;
3730 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3731 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3734 pci_registered = true;
3736 if (!slgt_device_list)
3737 printk("%s no devices found\n",driver_name);
3746 static void __exit slgt_exit(void)
3751 module_init(slgt_init);
3752 module_exit(slgt_exit);
3755 * register access routines
3758 #define CALC_REGADDR() \
3759 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3761 reg_addr += (info->port_num) * 32;
3763 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3766 return readb((void __iomem *)reg_addr);
3769 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3772 writeb(value, (void __iomem *)reg_addr);
3775 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3778 return readw((void __iomem *)reg_addr);
3781 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3784 writew(value, (void __iomem *)reg_addr);
3787 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3790 return readl((void __iomem *)reg_addr);
3793 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3796 writel(value, (void __iomem *)reg_addr);
3799 static void rdma_reset(struct slgt_info *info)
3804 wr_reg32(info, RDCSR, BIT1);
3806 /* wait for enable bit cleared */
3807 for(i=0 ; i < 1000 ; i++)
3808 if (!(rd_reg32(info, RDCSR) & BIT0))
3812 static void tdma_reset(struct slgt_info *info)
3817 wr_reg32(info, TDCSR, BIT1);
3819 /* wait for enable bit cleared */
3820 for(i=0 ; i < 1000 ; i++)
3821 if (!(rd_reg32(info, TDCSR) & BIT0))
3826 * enable internal loopback
3827 * TxCLK and RxCLK are generated from BRG
3828 * and TxD is looped back to RxD internally.
3830 static void enable_loopback(struct slgt_info *info)
3832 /* SCR (serial control) BIT2=looopback enable */
3833 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3835 if (info->params.mode != MGSL_MODE_ASYNC) {
3836 /* CCR (clock control)
3837 * 07..05 tx clock source (010 = BRG)
3838 * 04..02 rx clock source (010 = BRG)
3839 * 01 auxclk enable (0 = disable)
3840 * 00 BRG enable (1 = enable)
3844 wr_reg8(info, CCR, 0x49);
3846 /* set speed if available, otherwise use default */
3847 if (info->params.clock_speed)
3848 set_rate(info, info->params.clock_speed);
3850 set_rate(info, 3686400);
3855 * set baud rate generator to specified rate
3857 static void set_rate(struct slgt_info *info, u32 rate)
3860 unsigned int osc = info->base_clock;
3862 /* div = osc/rate - 1
3864 * Round div up if osc/rate is not integer to
3865 * force to next slowest rate.
3870 if (!(osc % rate) && div)
3872 wr_reg16(info, BDR, (unsigned short)div);
3876 static void rx_stop(struct slgt_info *info)
3880 /* disable and reset receiver */
3881 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3882 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3883 wr_reg16(info, RCR, val); /* clear reset bit */
3885 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3887 /* clear pending rx interrupts */
3888 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3892 info->rx_enabled = false;
3893 info->rx_restart = false;
3896 static void rx_start(struct slgt_info *info)
3900 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3902 /* clear pending rx overrun IRQ */
3903 wr_reg16(info, SSR, IRQ_RXOVER);
3905 /* reset and disable receiver */
3906 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3907 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3908 wr_reg16(info, RCR, val); /* clear reset bit */
3914 /* rx request when rx FIFO not empty */
3915 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3916 slgt_irq_on(info, IRQ_RXDATA);
3917 if (info->params.mode == MGSL_MODE_ASYNC) {
3918 /* enable saving of rx status */
3919 wr_reg32(info, RDCSR, BIT6);
3922 /* rx request when rx FIFO half full */
3923 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3924 /* set 1st descriptor address */
3925 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3927 if (info->params.mode != MGSL_MODE_ASYNC) {
3928 /* enable rx DMA and DMA interrupt */
3929 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3931 /* enable saving of rx status, rx DMA and DMA interrupt */
3932 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3936 slgt_irq_on(info, IRQ_RXOVER);
3938 /* enable receiver */
3939 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3941 info->rx_restart = false;
3942 info->rx_enabled = true;
3945 static void tx_start(struct slgt_info *info)
3947 if (!info->tx_enabled) {
3949 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3950 info->tx_enabled = true;
3953 if (desc_count(info->tbufs[info->tbuf_start])) {
3954 info->drop_rts_on_tx_done = false;
3956 if (info->params.mode != MGSL_MODE_ASYNC) {
3957 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3959 if (!(info->signals & SerialSignal_RTS)) {
3960 info->signals |= SerialSignal_RTS;
3962 info->drop_rts_on_tx_done = true;
3966 slgt_irq_off(info, IRQ_TXDATA);
3967 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3968 /* clear tx idle and underrun status bits */
3969 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3971 slgt_irq_off(info, IRQ_TXDATA);
3972 slgt_irq_on(info, IRQ_TXIDLE);
3973 /* clear tx idle status bit */
3974 wr_reg16(info, SSR, IRQ_TXIDLE);
3976 /* set 1st descriptor address and start DMA */
3977 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3978 wr_reg32(info, TDCSR, BIT2 + BIT0);
3979 info->tx_active = true;
3983 static void tx_stop(struct slgt_info *info)
3987 del_timer(&info->tx_timer);
3991 /* reset and disable transmitter */
3992 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3993 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3995 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3997 /* clear tx idle and underrun status bit */
3998 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4002 info->tx_enabled = false;
4003 info->tx_active = false;
4006 static void reset_port(struct slgt_info *info)
4008 if (!info->reg_addr)
4014 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4017 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4020 static void reset_adapter(struct slgt_info *info)
4023 for (i=0; i < info->port_count; ++i) {
4024 if (info->port_array[i])
4025 reset_port(info->port_array[i]);
4029 static void async_mode(struct slgt_info *info)
4033 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4039 * 15..13 mode, 010=async
4040 * 12..10 encoding, 000=NRZ
4042 * 08 1=odd parity, 0=even parity
4043 * 07 1=RTS driver control
4045 * 05..04 character length
4050 * 03 0=1 stop bit, 1=2 stop bits
4053 * 00 auto-CTS enable
4057 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4060 if (info->params.parity != ASYNC_PARITY_NONE) {
4062 if (info->params.parity == ASYNC_PARITY_ODD)
4066 switch (info->params.data_bits)
4068 case 6: val |= BIT4; break;
4069 case 7: val |= BIT5; break;
4070 case 8: val |= BIT5 + BIT4; break;
4073 if (info->params.stop_bits != 1)
4076 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4079 wr_reg16(info, TCR, val);
4083 * 15..13 mode, 010=async
4084 * 12..10 encoding, 000=NRZ
4086 * 08 1=odd parity, 0=even parity
4087 * 07..06 reserved, must be 0
4088 * 05..04 character length
4093 * 03 reserved, must be zero
4096 * 00 auto-DCD enable
4100 if (info->params.parity != ASYNC_PARITY_NONE) {
4102 if (info->params.parity == ASYNC_PARITY_ODD)
4106 switch (info->params.data_bits)
4108 case 6: val |= BIT4; break;
4109 case 7: val |= BIT5; break;
4110 case 8: val |= BIT5 + BIT4; break;
4113 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4116 wr_reg16(info, RCR, val);
4118 /* CCR (clock control)
4120 * 07..05 011 = tx clock source is BRG/16
4121 * 04..02 010 = rx clock source is BRG
4122 * 01 0 = auxclk disabled
4123 * 00 1 = BRG enabled
4127 wr_reg8(info, CCR, 0x69);
4131 /* SCR (serial control)
4133 * 15 1=tx req on FIFO half empty
4134 * 14 1=rx req on FIFO half full
4135 * 13 tx data IRQ enable
4136 * 12 tx idle IRQ enable
4137 * 11 rx break on IRQ enable
4138 * 10 rx data IRQ enable
4139 * 09 rx break off IRQ enable
4140 * 08 overrun IRQ enable
4145 * 03 0=16x sampling, 1=8x sampling
4146 * 02 1=txd->rxd internal loopback enable
4147 * 01 reserved, must be zero
4148 * 00 1=master IRQ enable
4150 val = BIT15 + BIT14 + BIT0;
4151 /* JCR[8] : 1 = x8 async mode feature available */
4152 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4153 ((info->base_clock < (info->params.data_rate * 16)) ||
4154 (info->base_clock % (info->params.data_rate * 16)))) {
4155 /* use 8x sampling */
4157 set_rate(info, info->params.data_rate * 8);
4159 /* use 16x sampling */
4160 set_rate(info, info->params.data_rate * 16);
4162 wr_reg16(info, SCR, val);
4164 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4166 if (info->params.loopback)
4167 enable_loopback(info);
4170 static void sync_mode(struct slgt_info *info)
4174 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4180 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4184 * 07 1=RTS driver control
4185 * 06 preamble enable
4186 * 05..04 preamble length
4187 * 03 share open/close flag
4190 * 00 auto-CTS enable
4194 switch(info->params.mode) {
4195 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4196 case MGSL_MODE_BISYNC: val |= BIT15; break;
4197 case MGSL_MODE_RAW: val |= BIT13; break;
4199 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4202 switch(info->params.encoding)
4204 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4205 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4206 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4207 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4208 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4209 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4210 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4213 switch (info->params.crc_type & HDLC_CRC_MASK)
4215 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4216 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4219 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4222 switch (info->params.preamble_length)
4224 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4225 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4226 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4229 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4232 wr_reg16(info, TCR, val);
4234 /* TPR (transmit preamble) */
4236 switch (info->params.preamble)
4238 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4239 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4240 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4241 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4242 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4243 default: val = 0x7e; break;
4245 wr_reg8(info, TPR, (unsigned char)val);
4249 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4253 * 07..03 reserved, must be 0
4256 * 00 auto-DCD enable
4260 switch(info->params.mode) {
4261 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4262 case MGSL_MODE_BISYNC: val |= BIT15; break;
4263 case MGSL_MODE_RAW: val |= BIT13; break;
4266 switch(info->params.encoding)
4268 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4269 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4270 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4271 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4272 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4273 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4274 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4277 switch (info->params.crc_type & HDLC_CRC_MASK)
4279 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4280 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4283 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4286 wr_reg16(info, RCR, val);
4288 /* CCR (clock control)
4290 * 07..05 tx clock source
4291 * 04..02 rx clock source
4297 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4299 // when RxC source is DPLL, BRG generates 16X DPLL
4300 // reference clock, so take TxC from BRG/16 to get
4301 // transmit clock at actual data rate
4302 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4303 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4305 val |= BIT6; /* 010, txclk = BRG */
4307 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4308 val |= BIT7; /* 100, txclk = DPLL Input */
4309 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4310 val |= BIT5; /* 001, txclk = RXC Input */
4312 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4313 val |= BIT3; /* 010, rxclk = BRG */
4314 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4315 val |= BIT4; /* 100, rxclk = DPLL */
4316 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4317 val |= BIT2; /* 001, rxclk = TXC Input */
4319 if (info->params.clock_speed)
4322 wr_reg8(info, CCR, (unsigned char)val);
4324 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4326 // program DPLL mode
4327 switch(info->params.encoding)
4329 case HDLC_ENCODING_BIPHASE_MARK:
4330 case HDLC_ENCODING_BIPHASE_SPACE:
4332 case HDLC_ENCODING_BIPHASE_LEVEL:
4333 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4334 val = BIT7 + BIT6; break;
4335 default: val = BIT6; // NRZ encodings
4337 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4339 // DPLL requires a 16X reference clock from BRG
4340 set_rate(info, info->params.clock_speed * 16);
4343 set_rate(info, info->params.clock_speed);
4349 /* SCR (serial control)
4351 * 15 1=tx req on FIFO half empty
4352 * 14 1=rx req on FIFO half full
4353 * 13 tx data IRQ enable
4354 * 12 tx idle IRQ enable
4355 * 11 underrun IRQ enable
4356 * 10 rx data IRQ enable
4357 * 09 rx idle IRQ enable
4358 * 08 overrun IRQ enable
4363 * 03 reserved, must be zero
4364 * 02 1=txd->rxd internal loopback enable
4365 * 01 reserved, must be zero
4366 * 00 1=master IRQ enable
4368 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4370 if (info->params.loopback)
4371 enable_loopback(info);
4375 * set transmit idle mode
4377 static void tx_set_idle(struct slgt_info *info)
4382 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4383 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4385 tcr = rd_reg16(info, TCR);
4386 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4387 /* disable preamble, set idle size to 16 bits */
4388 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4389 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4390 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4391 } else if (!(tcr & BIT6)) {
4392 /* preamble is disabled, set idle size to 8 bits */
4393 tcr &= ~(BIT5 + BIT4);
4395 wr_reg16(info, TCR, tcr);
4397 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4398 /* LSB of custom tx idle specified in tx idle register */
4399 val = (unsigned char)(info->idle_mode & 0xff);
4401 /* standard 8 bit idle patterns */
4402 switch(info->idle_mode)
4404 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4405 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4406 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4407 case HDLC_TXIDLE_ZEROS:
4408 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4409 default: val = 0xff;
4413 wr_reg8(info, TIR, val);
4417 * get state of V24 status (input) signals
4419 static void get_signals(struct slgt_info *info)
4421 unsigned short status = rd_reg16(info, SSR);
4423 /* clear all serial signals except DTR and RTS */
4424 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4427 info->signals |= SerialSignal_DSR;
4429 info->signals |= SerialSignal_CTS;
4431 info->signals |= SerialSignal_DCD;
4433 info->signals |= SerialSignal_RI;
4437 * set V.24 Control Register based on current configuration
4439 static void msc_set_vcr(struct slgt_info *info)
4441 unsigned char val = 0;
4443 /* VCR (V.24 control)
4445 * 07..04 serial IF select
4452 switch(info->if_mode & MGSL_INTERFACE_MASK)
4454 case MGSL_INTERFACE_RS232:
4455 val |= BIT5; /* 0010 */
4457 case MGSL_INTERFACE_V35:
4458 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4460 case MGSL_INTERFACE_RS422:
4461 val |= BIT6; /* 0100 */
4465 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4467 if (info->signals & SerialSignal_DTR)
4469 if (info->signals & SerialSignal_RTS)
4471 if (info->if_mode & MGSL_INTERFACE_LL)
4473 if (info->if_mode & MGSL_INTERFACE_RL)
4475 wr_reg8(info, VCR, val);
4479 * set state of V24 control (output) signals
4481 static void set_signals(struct slgt_info *info)
4483 unsigned char val = rd_reg8(info, VCR);
4484 if (info->signals & SerialSignal_DTR)
4488 if (info->signals & SerialSignal_RTS)
4492 wr_reg8(info, VCR, val);
4496 * free range of receive DMA buffers (i to last)
4498 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4503 /* reset current buffer for reuse */
4504 info->rbufs[i].status = 0;
4505 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4508 if (++i == info->rbuf_count)
4511 info->rbuf_current = i;
4515 * mark all receive DMA buffers as free
4517 static void reset_rbufs(struct slgt_info *info)
4519 free_rbufs(info, 0, info->rbuf_count - 1);
4520 info->rbuf_fill_index = 0;
4521 info->rbuf_fill_count = 0;
4525 * pass receive HDLC frame to upper layer
4527 * return true if frame available, otherwise false
4529 static bool rx_get_frame(struct slgt_info *info)
4531 unsigned int start, end;
4532 unsigned short status;
4533 unsigned int framesize = 0;
4534 unsigned long flags;
4535 struct tty_struct *tty = info->port.tty;
4536 unsigned char addr_field = 0xff;
4537 unsigned int crc_size = 0;
4539 switch (info->params.crc_type & HDLC_CRC_MASK) {
4540 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4541 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4548 start = end = info->rbuf_current;
4551 if (!desc_complete(info->rbufs[end]))
4554 if (framesize == 0 && info->params.addr_filter != 0xff)
4555 addr_field = info->rbufs[end].buf[0];
4557 framesize += desc_count(info->rbufs[end]);
4559 if (desc_eof(info->rbufs[end]))
4562 if (++end == info->rbuf_count)
4565 if (end == info->rbuf_current) {
4566 if (info->rx_enabled){
4567 spin_lock_irqsave(&info->lock,flags);
4569 spin_unlock_irqrestore(&info->lock,flags);
4577 * 15 buffer complete
4580 * 02 eof (end of frame)
4584 status = desc_status(info->rbufs[end]);
4586 /* ignore CRC bit if not using CRC (bit is undefined) */
4587 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4590 if (framesize == 0 ||
4591 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4592 free_rbufs(info, start, end);
4596 if (framesize < (2 + crc_size) || status & BIT0) {
4597 info->icount.rxshort++;
4599 } else if (status & BIT1) {
4600 info->icount.rxcrc++;
4601 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4605 #if SYNCLINK_GENERIC_HDLC
4606 if (framesize == 0) {
4607 info->netdev->stats.rx_errors++;
4608 info->netdev->stats.rx_frame_errors++;
4612 DBGBH(("%s rx frame status=%04X size=%d\n",
4613 info->device_name, status, framesize));
4614 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4617 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4618 framesize -= crc_size;
4622 if (framesize > info->max_frame_size + crc_size)
4623 info->icount.rxlong++;
4625 /* copy dma buffer(s) to contiguous temp buffer */
4626 int copy_count = framesize;
4628 unsigned char *p = info->tmp_rbuf;
4629 info->tmp_rbuf_count = framesize;
4631 info->icount.rxok++;
4634 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4635 memcpy(p, info->rbufs[i].buf, partial_count);
4637 copy_count -= partial_count;
4638 if (++i == info->rbuf_count)
4642 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4643 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4647 #if SYNCLINK_GENERIC_HDLC
4649 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4652 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4655 free_rbufs(info, start, end);
4663 * pass receive buffer (RAW synchronous mode) to tty layer
4664 * return true if buffer available, otherwise false
4666 static bool rx_get_buf(struct slgt_info *info)
4668 unsigned int i = info->rbuf_current;
4671 if (!desc_complete(info->rbufs[i]))
4673 count = desc_count(info->rbufs[i]);
4674 switch(info->params.mode) {
4675 case MGSL_MODE_MONOSYNC:
4676 case MGSL_MODE_BISYNC:
4677 /* ignore residue in byte synchronous modes */
4678 if (desc_residue(info->rbufs[i]))
4682 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4683 DBGINFO(("rx_get_buf size=%d\n", count));
4685 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4686 info->flag_buf, count);
4687 free_rbufs(info, i, i);
4691 static void reset_tbufs(struct slgt_info *info)
4694 info->tbuf_current = 0;
4695 for (i=0 ; i < info->tbuf_count ; i++) {
4696 info->tbufs[i].status = 0;
4697 info->tbufs[i].count = 0;
4702 * return number of free transmit DMA buffers
4704 static unsigned int free_tbuf_count(struct slgt_info *info)
4706 unsigned int count = 0;
4707 unsigned int i = info->tbuf_current;
4711 if (desc_count(info->tbufs[i]))
4712 break; /* buffer in use */
4714 if (++i == info->tbuf_count)
4716 } while (i != info->tbuf_current);
4718 /* if tx DMA active, last zero count buffer is in use */
4719 if (count && (rd_reg32(info, TDCSR) & BIT0))
4726 * return number of bytes in unsent transmit DMA buffers
4727 * and the serial controller tx FIFO
4729 static unsigned int tbuf_bytes(struct slgt_info *info)
4731 unsigned int total_count = 0;
4732 unsigned int i = info->tbuf_current;
4733 unsigned int reg_value;
4735 unsigned int active_buf_count = 0;
4738 * Add descriptor counts for all tx DMA buffers.
4739 * If count is zero (cleared by DMA controller after read),
4740 * the buffer is complete or is actively being read from.
4742 * Record buf_count of last buffer with zero count starting
4743 * from current ring position. buf_count is mirror
4744 * copy of count and is not cleared by serial controller.
4745 * If DMA controller is active, that buffer is actively
4746 * being read so add to total.
4749 count = desc_count(info->tbufs[i]);
4751 total_count += count;
4752 else if (!total_count)
4753 active_buf_count = info->tbufs[i].buf_count;
4754 if (++i == info->tbuf_count)
4756 } while (i != info->tbuf_current);
4758 /* read tx DMA status register */
4759 reg_value = rd_reg32(info, TDCSR);
4761 /* if tx DMA active, last zero count buffer is in use */
4762 if (reg_value & BIT0)
4763 total_count += active_buf_count;
4765 /* add tx FIFO count = reg_value[15..8] */
4766 total_count += (reg_value >> 8) & 0xff;
4768 /* if transmitter active add one byte for shift register */
4769 if (info->tx_active)
4776 * load data into transmit DMA buffer ring and start transmitter if needed
4777 * return true if data accepted, otherwise false (buffers full)
4779 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4781 unsigned short count;
4783 struct slgt_desc *d;
4785 /* check required buffer space */
4786 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4789 DBGDATA(info, buf, size, "tx");
4792 * copy data to one or more DMA buffers in circular ring
4793 * tbuf_start = first buffer for this data
4794 * tbuf_current = next free buffer
4796 * Copy all data before making data visible to DMA controller by
4797 * setting descriptor count of the first buffer.
4798 * This prevents an active DMA controller from reading the first DMA
4799 * buffers of a frame and stopping before the final buffers are filled.
4802 info->tbuf_start = i = info->tbuf_current;
4805 d = &info->tbufs[i];
4807 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4808 memcpy(d->buf, buf, count);
4814 * set EOF bit for last buffer of HDLC frame or
4815 * for every buffer in raw mode
4817 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4818 info->params.mode == MGSL_MODE_RAW)
4819 set_desc_eof(*d, 1);
4821 set_desc_eof(*d, 0);
4823 /* set descriptor count for all but first buffer */
4824 if (i != info->tbuf_start)
4825 set_desc_count(*d, count);
4826 d->buf_count = count;
4828 if (++i == info->tbuf_count)
4832 info->tbuf_current = i;
4834 /* set first buffer count to make new data visible to DMA controller */
4835 d = &info->tbufs[info->tbuf_start];
4836 set_desc_count(*d, d->buf_count);
4838 /* start transmitter if needed and update transmit timeout */
4839 if (!info->tx_active)
4841 update_tx_timer(info);
4846 static int register_test(struct slgt_info *info)
4848 static unsigned short patterns[] =
4849 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4850 static unsigned int count = ARRAY_SIZE(patterns);
4854 for (i=0 ; i < count ; i++) {
4855 wr_reg16(info, TIR, patterns[i]);
4856 wr_reg16(info, BDR, patterns[(i+1)%count]);
4857 if ((rd_reg16(info, TIR) != patterns[i]) ||
4858 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4863 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4864 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4868 static int irq_test(struct slgt_info *info)
4870 unsigned long timeout;
4871 unsigned long flags;
4872 struct tty_struct *oldtty = info->port.tty;
4873 u32 speed = info->params.data_rate;
4875 info->params.data_rate = 921600;
4876 info->port.tty = NULL;
4878 spin_lock_irqsave(&info->lock, flags);
4880 slgt_irq_on(info, IRQ_TXIDLE);
4882 /* enable transmitter */
4884 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4886 /* write one byte and wait for tx idle */
4887 wr_reg16(info, TDR, 0);
4889 /* assume failure */
4890 info->init_error = DiagStatus_IrqFailure;
4891 info->irq_occurred = false;
4893 spin_unlock_irqrestore(&info->lock, flags);
4896 while(timeout-- && !info->irq_occurred)
4897 msleep_interruptible(10);
4899 spin_lock_irqsave(&info->lock,flags);
4901 spin_unlock_irqrestore(&info->lock,flags);
4903 info->params.data_rate = speed;
4904 info->port.tty = oldtty;
4906 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4907 return info->irq_occurred ? 0 : -ENODEV;
4910 static int loopback_test_rx(struct slgt_info *info)
4912 unsigned char *src, *dest;
4915 if (desc_complete(info->rbufs[0])) {
4916 count = desc_count(info->rbufs[0]);
4917 src = info->rbufs[0].buf;
4918 dest = info->tmp_rbuf;
4920 for( ; count ; count-=2, src+=2) {
4921 /* src=data byte (src+1)=status byte */
4922 if (!(*(src+1) & (BIT9 + BIT8))) {
4925 info->tmp_rbuf_count++;
4928 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4934 static int loopback_test(struct slgt_info *info)
4936 #define TESTFRAMESIZE 20
4938 unsigned long timeout;
4939 u16 count = TESTFRAMESIZE;
4940 unsigned char buf[TESTFRAMESIZE];
4942 unsigned long flags;
4944 struct tty_struct *oldtty = info->port.tty;
4947 memcpy(¶ms, &info->params, sizeof(params));
4949 info->params.mode = MGSL_MODE_ASYNC;
4950 info->params.data_rate = 921600;
4951 info->params.loopback = 1;
4952 info->port.tty = NULL;
4954 /* build and send transmit frame */
4955 for (count = 0; count < TESTFRAMESIZE; ++count)
4956 buf[count] = (unsigned char)count;
4958 info->tmp_rbuf_count = 0;
4959 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4961 /* program hardware for HDLC and enabled receiver */
4962 spin_lock_irqsave(&info->lock,flags);
4965 tx_load(info, buf, count);
4966 spin_unlock_irqrestore(&info->lock, flags);
4968 /* wait for receive complete */
4969 for (timeout = 100; timeout; --timeout) {
4970 msleep_interruptible(10);
4971 if (loopback_test_rx(info)) {
4977 /* verify received frame length and contents */
4978 if (!rc && (info->tmp_rbuf_count != count ||
4979 memcmp(buf, info->tmp_rbuf, count))) {
4983 spin_lock_irqsave(&info->lock,flags);
4984 reset_adapter(info);
4985 spin_unlock_irqrestore(&info->lock,flags);
4987 memcpy(&info->params, ¶ms, sizeof(info->params));
4988 info->port.tty = oldtty;
4990 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4994 static int adapter_test(struct slgt_info *info)
4996 DBGINFO(("testing %s\n", info->device_name));
4997 if (register_test(info) < 0) {
4998 printk("register test failure %s addr=%08X\n",
4999 info->device_name, info->phys_reg_addr);
5000 } else if (irq_test(info) < 0) {
5001 printk("IRQ test failure %s IRQ=%d\n",
5002 info->device_name, info->irq_level);
5003 } else if (loopback_test(info) < 0) {
5004 printk("loopback test failure %s\n", info->device_name);
5006 return info->init_error;
5010 * transmit timeout handler
5012 static void tx_timeout(unsigned long context)
5014 struct slgt_info *info = (struct slgt_info*)context;
5015 unsigned long flags;
5017 DBGINFO(("%s tx_timeout\n", info->device_name));
5018 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5019 info->icount.txtimeout++;
5021 spin_lock_irqsave(&info->lock,flags);
5023 spin_unlock_irqrestore(&info->lock,flags);
5025 #if SYNCLINK_GENERIC_HDLC
5027 hdlcdev_tx_done(info);
5034 * receive buffer polling timer
5036 static void rx_timeout(unsigned long context)
5038 struct slgt_info *info = (struct slgt_info*)context;
5039 unsigned long flags;
5041 DBGINFO(("%s rx_timeout\n", info->device_name));
5042 spin_lock_irqsave(&info->lock, flags);
5043 info->pending_bh |= BH_RECEIVE;
5044 spin_unlock_irqrestore(&info->lock, flags);
5045 bh_handler(&info->task);