drivers/char/mux_sdio_opt1_hal/ipc_sdio.c

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14
  15 #include <linux/delay.h>
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/list.h>
  22 #include <linux/wakelock.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/wait.h>
  25 #include <linux/sched.h>
  26 #include <linux/kthread.h>
  27 #include <linux/slab.h>
  28 #include <linux/io.h>
  29 #include "ipc_gpio.h"
  30 //#include <mach/modem_interface.h>
  31 #include <linux/sprdmux.h>
  32 #include <linux/mmc/sdio_channel.h>
  33 #include <linux/kfifo.h>
  34 #include "ipc_info.h"
  35 #define  MUX_IPC_READ_DISABLE                    0x01
  36 #define  MUX_IPC_WRITE_DISABLE                  0x02
  37
  38
  39
  40 //#define SDIO_READ_DEBUG
  41 //#define SDIO_LOOPBACK_TEST
  42 //#define SDIO_DEBUG_ENABLE
  43
  44 //#define SDIO_LOOP_TEST
  45 #define SDIO_VARIABLE_DL_LEN
  46 //#define SC9620_JTAG_DL_MOD
  47 #define HEADER_TAG 0x7e7f
  48 #define HEADER_TYPE 0xaa00
  49
  50 #define IPC_DRIVER_NAME "IPC_SDIO"
  51
  52 #define MAX_SDIO_TX_WAIT_TIMEOUT    100
  53
  54 #define MAX_SDIO_CP_AWAKE_TIMEOUT    500
  55 #define MAX_SDIO_SLEEP_TIMEOUT    50
  56 #define MAX_SDIO_CP_ACK_TIMEOUT    1000
  57 #define MAX_SDIO_TX_WATERMARK    4
  58 #define MAX_SDIO_RX_RETRY               3
  59 #define MAX_SDIO_TX_RETRY               3
  60
  61 #define SDIO_GPIO_RES_FREE                      0
  62 #define SDIO_GPIO_RES_USING             1
  63
  64
  65 #define MAX_MIPC_RX_FRAME_SIZE          (64*1024)
  66 #define MAX_MIPC_TX_FRAME_SIZE          (32*1024)
  67
  68 #define MIN_MIPC_TX_FRAME_SIZE          (4 * 1024)
  69
  70 #define MAX_MIPC_RX_CACHE_SIZE   MAX_MIPC_RX_FRAME_SIZE*4
  71
  72 //#define MAX_MIPC_TX_FIFO_SIZE    (1 << 7)   // 128
  73 #define MAX_MIPC_TX_FIFO_SIZE    (1 << 3)   // 16
  74
  75
  76 #define MAX_MIPC_TX_FRAME_NUM    (MAX_MIPC_TX_FIFO_SIZE - 1)
  77
  78 #ifdef SDIO_VARIABLE_DL_LEN
  79 #define DEFAULT_RX_FRAME_SIZE   (4*1024)
  80 #else
  81 #define DEFAULT_RX_FRAME_SIZE   MAX_MIPC_RX_FRAME_SIZE
  82 #endif
  83
  84 #define NEXT_TX_FIFO_IDX(idx) (((idx) + 1) & (MAX_MIPC_TX_FIFO_SIZE - 1))
  85
  86 #define MIPC_TX_REQ_FLAG ((s_mipc_tx_ctrl.fifo_wr != s_mipc_tx_ctrl.fifo_rd) && s_tx_flow_info)
  87
  88
  89
  90 //#define IPC_DBG(f, x...)      pr_debug(IPC_DRIVER_NAME " [%s()]: " f, __func__,## x)
  91 #define IPC_DBG printk
  92
  93 /* Log Macros */
  94 #define IPC_SDIO_INFO(fmt...)  pr_debug("IPC_SDIO: " fmt)
  95 #define IPC_SDIO_DEBUG(fmt...) pr_debug("IPC_SDIO: " fmt)
  96 #define IPC_SDIO_WARN(fmt...)   pr_warn("IPC_SDIO: " fmt)
  97 #define IPC_SDIO_ERR(fmt...)   pr_err("IPC_SDIO: Error: " fmt)
  98
  99
 100
 101 struct packet_header {
 102         u16 tag;
 103         u16 flag;
 104         u32 length;
 105         u32 frame_num;
 106         union {
 107                 u32 emergency_cmd;
 108                 u32 ul_frame_num;
 109         } u;
 110         u32 next_length;
 111         u32 reserved[3];
 112 } __packed;
 113
 114 typedef struct  MIPC_TRANSF_FRAME_Tag {
 115         u8*  buf_ptr;
 116         u32  buf_size;
 117         u32  pos;
 118         u32  flag;
 119         struct list_head  link;
 120 } MIPC_TRANSF_FRAME_T;
 121
 122 typedef struct  MIPC_FRAME_LIST_Tag {
 123         struct list_head   frame_list_head;
 124         struct mutex       list_mutex;
 125         u32    counter;
 126 } MIPC_FRAME_LIST_T;
 127
 128 typedef struct MIPC_TRANSFER_Tag {
 129         struct mutex                             transfer_mutex;
 130         struct list_head                        frame_fifo;
 131         wait_queue_head_t                       frame_free_wq;
 132         MIPC_TRANSF_FRAME_T*        cur_frame_ptr;
 133         u32                                     frame_count;
 134         u32                                            counter;
 135 } MIPC_TRANSFER_T;
 136
 137 typedef struct CP_AWAKE_STATUS_Tag {
 138         u32 ack_time;
 139         bool awake;
 140         spinlock_t lock;
 141         wait_queue_head_t wait;
 142 } CP_AWAKE_STATUS_T;
 143
 144 typedef struct MIPC_TX_CTRL_Tag {
 145         MIPC_TRANSF_FRAME_T*            fifo[MAX_MIPC_TX_FIFO_SIZE];
 146         volatile u32                 fifo_rd;
 147         volatile u32                 fifo_wr;
 148         u32                             fifo_ack;
 149         u32                                                     last_ack_frame;
 150 } MIPC_TX_CTRL_T;
 151
 152 static struct kfifo  s_mipc_rx_cache_kfifo;
 153
 154 u8* s_mipc_rx_buf = NULL;
 155 u32 s_mipc_next_rx_len = DEFAULT_RX_FRAME_SIZE;
 156
 157
 158 MIPC_TRANSF_FRAME_T   s_tx_transfer_frame[MAX_MIPC_TX_FRAME_NUM];
 159
 160 static struct wake_lock   s_ipc_sdio_wake_lock;
 161 static struct wake_lock   s_cp_req_wake_lock;
 162
 163
 164 static struct mutex ipc_mutex;
 165 wait_queue_head_t s_mux_read_rts;
 166 wait_queue_head_t s_rx_fifo_avail;
 167 wait_queue_head_t s_modem_ready;
 168 wait_queue_head_t s_sdio_gpio_res_free;
 169
 170
 171 u32 s_mux_ipc_event_flags = 0;
 172
 173 static struct task_struct *s_mux_ipc_rx_thread;
 174 static struct task_struct *s_mux_ipc_tx_thread;
 175 static struct task_struct *s_mux_ipc_sdio_thread;
 176
 177
 178 static  int   sdio_tx_wait_time = 1;
 179 MIPC_FRAME_LIST_T  s_mipc_tx_free_frame_list;
 180 MIPC_TRANSFER_T     s_mipc_tx_tansfer;
 181
 182 static u32  s_mux_ipc_enable = 0;
 183 static u32  s_sdio_gpio_res_status = SDIO_GPIO_RES_FREE;
 184
 185 static wait_queue_head_t s_mux_ipc_tx_wq;
 186 static wait_queue_head_t s_mux_ipc_rx_wq;
 187
 188
 189
 190 static u32  s_mux_ipc_module_inited = 0;
 191
 192 static int  sdio_transfer_crc_check_enable = 0;
 193 static int  sdio_transfer_frame_check_enable = 0;
 194
 195 u32 s_mipc_rx_event_flags = 0;
 196
 197 static wait_queue_head_t s_mux_ipc_sdio_wq;
 198 static u32 s_mipc_rx_req_flag = 0;
 199 static u32 s_mipc_enable_change_flag = 0;
 200
 201 static CP_AWAKE_STATUS_T s_cp_awake_status;
 202 //static u32 s_mipc_tx_above_watermark = 0;
 203 static u32 s_tx_flow_info = 0xFF;
 204 static u32 s_acked_tx_frame = 0;
 205 static u32 s_last_tx_frame = 0;
 206 static u32 s_tx_frame_counter; //tx frame number start from 1
 207
 208 static MIPC_TX_CTRL_T s_mipc_tx_ctrl;
 209
 210 //static atomic_t               s_mipc_read_pending;
 211
 212
 213
 214 static DEFINE_MUTEX(sdio_tx_lock);
 215 static int mux_ipc_xmit_buf(const char *buf, ssize_t len);
 216 static int mux_ipc_sdio_write( const char *buf, size_t  count);
 217 static int mux_ipc_sdio_read(  char *buf, size_t  count);
 218 static u32 _FreeAllTxTransferFrame(void);
 219 static void _FreeFrame(MIPC_TRANSF_FRAME_T* frame_ptr, MIPC_FRAME_LIST_T*  frame_list_ptr);
 220 static u32 _FlushTxTransfer(void);
 221 static void _WaitTxTransferFree(void);
 222 static void _WakeTxTransfer(void);
 223
 224
 225
 226 #include<mach/hardware.h>
 227
 228 /* use this method we can get time everytime */
 229 #define TIMER_REG(off) (SPRD_TIMER_BASE + (off))
 230 #define SYSCNT_REG(off) (SPRD_SYSCNT_BASE + (off))
 231 #define SYSCNT_COUNT    SYSCNT_REG(0x0004)
 232
 233 /* no need double-reading */
 234 #define SYSCNT_SHADOW_COUNT    SYSCNT_REG(0x000c)
 235
 236 #if 0
 237 static u32 inline get_sys_cnt(void)
 238 {
 239 #if defined(CONFIG_ARCH_SC7710)
 240         return __raw_readl(SYSCNT_SHADOW_COUNT);
 241 #else
 242         u32 val1, val2;
 243         val1 = __raw_readl(SYSCNT_COUNT);
 244         val2 = __raw_readl(SYSCNT_COUNT);
 245         while(val2 != val1) {
 246                 val1 = val2;
 247                 val2 = __raw_readl(SYSCNT_COUNT);
 248         }
 249         return val2;
 250 #endif
 251 }
 252 #endif
 253
 254 static  u32  _is_mux_ipc_enable(void)
 255 {
 256 #ifdef SC9620_JTAG_DL_MOD
 257         return 1;
 258 #else
 259         return s_mux_ipc_enable;
 260 #endif
 261 }
 262
 263
 264 void wait_cp_bootup(void)
 265 {
 266         wait_event(s_modem_ready, _is_mux_ipc_enable());
 267 }
 268
 269 void init_cp_awake_status(void)
 270 {
 271         s_cp_awake_status.ack_time = 0;
 272         s_cp_awake_status.awake = false;
 273         spin_lock_init(&s_cp_awake_status.lock);
 274         init_waitqueue_head(&s_cp_awake_status.wait);
 275 }
 276
 277 void set_cp_awake(bool awake)
 278 {
 279         unsigned long flags;
 280         bool last_status;
 281
 282         spin_lock_irqsave(&s_cp_awake_status.lock, flags);
 283         last_status = s_cp_awake_status.awake;
 284         s_cp_awake_status.awake = awake;
 285         if(s_cp_awake_status.awake) {
 286                 s_cp_awake_status.ack_time = jiffies;
 287         }
 288         spin_unlock_irqrestore(&s_cp_awake_status.lock, flags);
 289
 290         if(!last_status && awake) {
 291                 wake_up(&s_cp_awake_status.wait);
 292         }
 293 }
 294
 295 bool get_cp_awake(void)
 296 {
 297         unsigned long flags;
 298         bool ret = false;
 299
 300         spin_lock_irqsave(&s_cp_awake_status.lock, flags);
 301         if(s_cp_awake_status.awake) {
 302                 unsigned long diff = (long)jiffies - (long)s_cp_awake_status.ack_time;
 303
 304                 if(jiffies_to_msecs(diff) > MAX_SDIO_CP_AWAKE_TIMEOUT) {
 305                         s_cp_awake_status.awake = false;
 306                 }
 307         }
 308         ret = s_cp_awake_status.awake;
 309         spin_unlock_irqrestore(&s_cp_awake_status.lock, flags);
 310
 311         return ret;
 312 }
 313
 314 bool wait_cp_awake(unsigned long timeout)
 315 {
 316         if(get_cp_awake()) {
 317                 return true;
 318         }
 319         if(!wait_event_timeout(s_cp_awake_status.wait,  s_cp_awake_status.awake,
 320                                timeout)) {
 321                 IPC_SDIO_ERR("[MIPC] SDIO wait cp awake for a long time!\r\n");
 322         }
 323
 324         return s_cp_awake_status.awake;
 325 }
 326
 327 //MIPC_TX_CTRL_T ops
 328 void init_mipc_tx_ctrl(void)
 329 {
 330         memset(s_mipc_tx_ctrl.fifo, 0, sizeof(MIPC_TRANSF_FRAME_T*) * MAX_MIPC_TX_FIFO_SIZE);
 331         s_mipc_tx_ctrl.fifo_rd = 0;
 332         s_mipc_tx_ctrl.fifo_wr = 0;
 333         s_mipc_tx_ctrl.fifo_ack = 0;
 334         s_mipc_tx_ctrl.last_ack_frame = 0;
 335         s_tx_frame_counter = 1; //tx frame number start from 1
 336 }
 337
 338 void put_to_sdio_tx_fifo(MIPC_TRANSF_FRAME_T* frame)
 339 {
 340         s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_wr] = frame;
 341         smp_mb();
 342         s_mipc_tx_ctrl.fifo_wr = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_wr);
 343
 344         wake_up(&s_mux_ipc_sdio_wq);
 345 }
 346
 347 MIPC_TRANSF_FRAME_T* get_from_sdio_tx_fifo(void)
 348 {
 349         MIPC_TRANSF_FRAME_T* ret = NULL;
 350
 351         if(s_mipc_tx_ctrl.fifo_rd != s_mipc_tx_ctrl.fifo_wr) {
 352                 smp_mb();
 353                 ret = s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_rd];
 354                 smp_mb();
 355                 s_mipc_tx_ctrl.fifo_rd = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_rd);
 356         }
 357
 358         return ret;
 359 }
 360
 361 void ack_tx_frame_num(u32 frame_num)
 362 {
 363         struct packet_header * pkt = NULL;
 364
 365         while(s_mipc_tx_ctrl.fifo_ack != s_mipc_tx_ctrl.fifo_rd) {
 366                 smp_mb();
 367                 if(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack]) {
 368                         pkt = (struct packet_header *)s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack]->buf_ptr;
 369
 370                         if((long)(frame_num) - (long)(pkt->frame_num) >= 0) {
 371                                 //calc tx payload
 372                                 ipc_info_sdio_write_payload(pkt->length);
 373                                 _FreeFrame(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack], &s_mipc_tx_free_frame_list);
 374
 375                                 smp_mb();
 376                                 s_mipc_tx_ctrl.fifo_ack = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_ack);
 377                         } else {
 378                                 break;
 379                         }
 380                 } else {
 381                         IPC_SDIO_ERR("[MIPC] ERROR s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack] == 0!\r\n");
 382                         break;
 383                 }
 384         }
 385         s_mipc_tx_ctrl.last_ack_frame = frame_num;
 386 }
 387
 388
 389 void nack_tx_frame_num(void)
 390 {
 391         //test
 392         {
 393                 u32 ack, rd;
 394                 ack = s_mipc_tx_ctrl.fifo_ack;
 395                 rd = s_mipc_tx_ctrl.fifo_rd;
 396                 while(ack != rd) {
 397                         ipc_info_error_status(IPC_TX_CHANNEL, IPC_STATUS_INVALID_PACKET);
 398                         ack = NEXT_TX_FIFO_IDX(ack);
 399                 }
 400         }
 401
 402         IPC_SDIO_INFO("[mipc]before nack_tx_frame_num fifo_rd:%ld\n", s_mipc_tx_ctrl.fifo_rd);
 403         s_mipc_tx_ctrl.fifo_rd = s_mipc_tx_ctrl.fifo_ack;
 404         IPC_SDIO_INFO("[mipc]nack_tx_frame_num fifo_rd:%d\n", s_mipc_tx_ctrl.fifo_rd);
 405 }
 406
 407
 408
 409 bool implicit_ack_tx_frame(void)
 410 {
 411         if(s_mipc_tx_ctrl.fifo_ack != s_mipc_tx_ctrl.fifo_rd) {
 412                 if(!s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack]) {
 413                         IPC_SDIO_ERR("[MIPC] ERROR implicit_ack_tx_frame fifo[fifo_ack] == 0!\r\n");
 414                 } else {
 415                         //calc tx payload
 416                         struct packet_header * pkt;
 417                         pkt = (struct packet_header *)s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack]->buf_ptr;
 418                         ipc_info_sdio_write_payload(pkt->length);
 419
 420                         _FreeFrame(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack], &s_mipc_tx_free_frame_list);
 421                         s_mipc_tx_ctrl.fifo_ack = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_ack);
 422                         return true;
 423                 }
 424         } else {
 425                 IPC_SDIO_ERR("[MIPC] ERROR implicit_ack_tx_frame fifo_ack == fifo_rd!\r\n");
 426         }
 427         return false;
 428 }
 429
 430 void free_all_tx_frame_in_fifo(void)
 431 {
 432         //free written items
 433         while(s_mipc_tx_ctrl.fifo_ack != s_mipc_tx_ctrl.fifo_rd) {
 434                 if(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack]) {
 435                         _FreeFrame(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_ack], &s_mipc_tx_free_frame_list);
 436                         s_mipc_tx_ctrl.fifo_ack = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_ack);
 437
 438                 }
 439         }
 440         //free un-written items
 441         while(s_mipc_tx_ctrl.fifo_rd != s_mipc_tx_ctrl.fifo_wr) {
 442                 if(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_rd]) {
 443                         _FreeFrame(s_mipc_tx_ctrl.fifo[s_mipc_tx_ctrl.fifo_rd], &s_mipc_tx_free_frame_list);
 444                         s_mipc_tx_ctrl.fifo_rd = NEXT_TX_FIFO_IDX(s_mipc_tx_ctrl.fifo_rd);
 445
 446                 }
 447         }
 448         s_mipc_tx_ctrl.fifo_ack = 0;
 449         s_mipc_tx_ctrl.fifo_rd = 0;
 450         s_mipc_tx_ctrl.fifo_wr = 0;
 451 }
 452
 453 #define MUX_IPC_DISABLE    0
 454 #define MUX_IPC_ENABLE    1
 455 void  sdio_ipc_enable(u8  is_enable)
 456 {
 457         if(!s_mux_ipc_module_inited) {
 458                 IPC_SDIO_ERR("Error: mux ipc module is not initialized!\r\n");
 459                 return;
 460         }
 461
 462
 463         if(is_enable) {
 464                 //msleep(1000);
 465                 kfifo_reset(&s_mipc_rx_cache_kfifo);
 466                 _FlushTxTransfer();
 467                 _FreeAllTxTransferFrame();
 468                 s_tx_flow_info = 0xFF;
 469                 s_acked_tx_frame = 0;
 470                 s_last_tx_frame = 0;
 471                 s_tx_frame_counter = 1; //tx frame number start from 1
 472                 s_mipc_next_rx_len = DEFAULT_RX_FRAME_SIZE;
 473                 //sdhci_resetconnect(MUX_IPC_DISABLE);
 474                 mutex_lock(&ipc_mutex);
 475                 s_mux_ipc_event_flags = 0;
 476                 mutex_unlock(&ipc_mutex);
 477                 s_mipc_enable_change_flag = 0;
 478                 s_mux_ipc_enable = MUX_IPC_ENABLE;
 479                 wake_up(&s_modem_ready);
 480         } else {
 481                 s_mux_ipc_enable = MUX_IPC_DISABLE;
 482                 //wakeup sdio thread to release sdio_gpio_res
 483                 s_mipc_enable_change_flag = 1;
 484                 wake_up(&s_mux_ipc_sdio_wq);
 485                 //wait all resources freed
 486                 wait_event(s_sdio_gpio_res_free,
 487                                          (s_sdio_gpio_res_status == SDIO_GPIO_RES_FREE));
 488         }
 489
 490         IPC_SDIO_WARN("[mipc]mux ipc enable:0x%x, status:0x%x\r\n", is_enable, s_mux_ipc_enable);
 491 }
 492
 493 int mux_ipc_sdio_stop(int mode)
 494 {
 495         mutex_lock(&ipc_mutex);
 496         if(mode & SPRDMUX_READ) {
 497                 s_mux_ipc_event_flags |=  MUX_IPC_READ_DISABLE;
 498         }
 499
 500         if(mode & SPRDMUX_WRITE) {
 501                 s_mux_ipc_event_flags |=  MUX_IPC_WRITE_DISABLE;
 502         }
 503         mutex_unlock(&ipc_mutex);
 504         wake_up(&s_mux_read_rts);
 505         _WakeTxTransfer();
 506         return 0;
 507 }
 508
 509 static char s_dbg_buf[MAX_MIPC_TX_FRAME_SIZE];
 510
 511 #ifdef SDIO_LOOP_TEST
 512
 513 unsigned char s_dbg_tx_seed_v0 = 0;
 514 unsigned char s_dbg_tx_seed_v1 = 0;
 515
 516
 517 void set_tx_buf_dbg_data(unsigned char* payload, unsigned long length)
 518 {
 519         int i = 0;
 520         unsigned char v0 = s_dbg_tx_seed_v0;
 521         unsigned char v1 = s_dbg_tx_seed_v1;
 522         unsigned char val;
 523
 524         for(i = 0; i < length; i++) {
 525
 526                 val = v0 + v1 + 1;
 527                 v0 = v1;
 528                 v1 = val;
 529
 530                 payload[i] = val;
 531         }
 532         s_dbg_tx_seed_v0 = v0;
 533         s_dbg_tx_seed_v1 = v1;
 534 }
 535
 536 unsigned char s_dbg_tx_chk_seed_v0 = 0;
 537 unsigned char s_dbg_tx_chk_seed_v1 = 0;
 538 unsigned long s_dbg_rx_data_cnt = 0;
 539
 540
 541
 542 void chk_tx_buf_dbg_data(unsigned char* payload, unsigned long length)
 543 {
 544         int i = 0;
 545         unsigned char v0 = s_dbg_tx_chk_seed_v0;
 546         unsigned char v1 = s_dbg_tx_chk_seed_v1;
 547         unsigned char val;
 548
 549         for(i = 0; i < length; i++) {
 550
 551                 /*if(s_dbg_rx_data_cnt == ((64 * 1024 - 32) * 8)) {
 552                         s_dbg_tx_chk_seed_v0 = 0;
 553                         s_dbg_tx_chk_seed_v1 = 0;
 554                         v0 = s_dbg_tx_chk_seed_v0;
 555                         v1 = s_dbg_tx_chk_seed_v1;
 556                         s_dbg_rx_data_cnt = 0;
 557                 }*/
 558                 val = v0 + v1 + 1;
 559                 v0 = v1;
 560                 v1 = val;
 561
 562                 if(payload[i] != val) {
 563                         while(1) {
 564                                 IPC_SDIO_ERR("[mipc]chk_tx_buf_dbg_data error, rx_cnt:%d!\r\n", s_dbg_rx_data_cnt);
 565                                 msleep(200);
 566                         }
 567                 }
 568                 ++s_dbg_rx_data_cnt;
 569         }
 570         s_dbg_tx_chk_seed_v0 = v0;
 571         s_dbg_tx_chk_seed_v1 = v1;
 572 }
 573
 574 int mux_ipc_sdio_write_test(const char *buf, size_t  count)
 575 {
 576         static int first = 1;
 577         IPC_SDIO_INFO("[mipc]mux_ipc_sdio_write write len:%d\r\n", count);
 578         if(first) {
 579                 int cnt = 0;
 580                 first = 0;
 581                 wait_cp_bootup();
 582                 while(1) {
 583                         set_tx_buf_dbg_data(s_dbg_buf, MAX_MIPC_TX_FRAME_SIZE  - sizeof(struct packet_header));
 584                         mux_ipc_xmit_buf(s_dbg_buf, MAX_MIPC_TX_FRAME_SIZE  - sizeof(struct packet_header));
 585
 586                         cnt++;
 587                         if(cnt == MAX_MIPC_TX_FRAME_SIZE)
 588                                 //if(cnt == 4)
 589                         {
 590                                 msleep(100);
 591                                 cnt = 0;
 592                         }
 593                 }
 594         }
 595
 596         return count;
 597
 598         //return mux_ipc_xmit_buf(buf, count);
 599 }
 600 #endif
 601
 602 #ifndef SDIO_LOOP_TEST
 603
 604 int mux_ipc_sdio_write(const char *buf, size_t  count)
 605 {
 606         if(s_mux_ipc_event_flags & MUX_IPC_WRITE_DISABLE) {
 607                 IPC_SDIO_ERR("[mipc]mux_ipc_sdio_write write disabled!\r\n");
 608                 return -1;
 609         }
 610         wait_cp_bootup();
 611         IPC_SDIO_INFO("[mipc]mux_ipc_sdio_write write len:%d\r\n", count);
 612         return mux_ipc_xmit_buf(buf, count);
 613 }
 614
 615 #else
 616
 617 int mux_ipc_sdio_write(const char *buf, size_t  count)
 618 {
 619         wait_cp_bootup();
 620         IPC_SDIO_INFO("[mipc]mux_ipc_sdio_write write len:%d\r\n", count);
 621         return count;
 622 }
 623 #endif
 624
 625 #ifdef SDIO_LOOP_TEST
 626
 627 int do_mux_ipc_sdio_read(char *buf, size_t  count)
 628 {
 629         int ret = 0;
 630
 631         wait_event(s_mux_read_rts, !kfifo_is_empty(&s_mipc_rx_cache_kfifo) || s_mux_ipc_event_flags);
 632
 633         if(s_mux_ipc_event_flags & MUX_IPC_READ_DISABLE) {
 634                 IPC_SDIO_ERR("[mipc] mux ipc  read disable!\r\n");
 635                 return -1;
 636         }
 637
 638         ret = kfifo_out(&s_mipc_rx_cache_kfifo,buf,count);
 639         IPC_SDIO_INFO("[mipc]mux_ipc_sdio_read read len:%d\r\n", ret);
 640
 641         ipc_info_mux_read(ret);
 642
 643         ipc_info_sdio_read_saved_count(kfifo_len(&s_mipc_rx_cache_kfifo));
 644
 645         //wake up rx thread
 646         wake_up(&s_rx_fifo_avail);
 647         return ret;
 648 }
 649
 650 #define DBG_RX_BUF_LEN (16 * 1024)
 651
 652 unsigned char s_dbg_rx_buf[DBG_RX_BUF_LEN];
 653
 654 int mux_ipc_sdio_test_read(char *buf, size_t  c)
 655 {
 656         int ret = 0;
 657
 658         do {
 659
 660                 ret = do_mux_ipc_sdio_read(s_dbg_rx_buf, DBG_RX_BUF_LEN);
 661                 if(ret >= 0) {
 662                         chk_tx_buf_dbg_data(s_dbg_rx_buf, ret);
 663                 }
 664                 //printk("[mipc]mux_ipc_sdio_test_read sleep 10ms\r\n");
 665                 //msleep(10);
 666         } while(ret >= 0);
 667
 668         return 0;
 669 }
 670
 671
 672 #endif
 673
 674 #ifdef SDIO_LOOP_TEST
 675 int mux_ipc_sdio_read(char *buf, size_t  count)
 676 {
 677         int ret = 0;
 678
 679         return ret;
 680 }
 681
 682 #else
 683
 684 int mux_ipc_sdio_read(char *buf, size_t  count)
 685 {
 686         int ret = 0;
 687
 688         //incrase read count
 689         //atomic_inc(&s_mipc_read_pending);
 690
 691         wait_event(s_mux_read_rts, !kfifo_is_empty(&s_mipc_rx_cache_kfifo) || s_mux_ipc_event_flags);
 692
 693         //decrase read count
 694         //atomic_dec(&s_mipc_read_pending);
 695         if(s_mux_ipc_event_flags & MUX_IPC_READ_DISABLE) {
 696                 IPC_SDIO_ERR("[mipc] mux ipc  read disable!\r\n");
 697                 //if(atomic_read(&s_mipc_read_pending) == 0) {
 698                 mutex_lock(&ipc_mutex);
 699                 s_mux_ipc_event_flags = 0;
 700                 mutex_unlock(&ipc_mutex);
 701                 //}
 702                 return -1;
 703         }
 704
 705
 706         ret = kfifo_out(&s_mipc_rx_cache_kfifo,buf,count);
 707
 708         IPC_SDIO_INFO("[mipc]mux_ipc_sdio_read read len:%d\r\n", ret);
 709
 710         ipc_info_mux_read(ret);
 711
 712         ipc_info_sdio_read_saved_count(kfifo_len(&s_mipc_rx_cache_kfifo));
 713
 714         //wake up rx thread
 715         wake_up(&s_rx_fifo_avail);
 716
 717         return ret;
 718 }
 719 #endif
 720
 721 static void _FrameList_Init(MIPC_FRAME_LIST_T* frame_list_ptr)
 722 {
 723         if(!frame_list_ptr) {
 724                 panic("_Init_Frame_List: frame_list_ptr=NULL!\r\n");
 725                 return;
 726         }
 727
 728         INIT_LIST_HEAD(&frame_list_ptr->frame_list_head);
 729         mutex_init(&frame_list_ptr->list_mutex);
 730         frame_list_ptr->counter = 0;
 731 }
 732
 733 static void _TxFreeFrameList_Init(MIPC_FRAME_LIST_T* frame_list_ptr)
 734 {
 735         u32 t = 0;
 736         MIPC_TRANSF_FRAME_T* frame_ptr = NULL;
 737
 738         _FrameList_Init(frame_list_ptr);
 739
 740         for(t = 0; t < MAX_MIPC_TX_FRAME_NUM;  t++) {
 741                 frame_ptr = &s_tx_transfer_frame[t];
 742                 frame_ptr->buf_size =  MAX_MIPC_TX_FRAME_SIZE;
 743                 frame_ptr->buf_ptr = (u8*)kmalloc(frame_ptr->buf_size , GFP_KERNEL);
 744                 frame_ptr->pos = 0;
 745                 frame_ptr->flag = 0;
 746                 list_add_tail(&frame_ptr->link, &frame_list_ptr->frame_list_head);
 747                 frame_list_ptr->counter++;
 748         }
 749
 750 }
 751
 752 static void _TransferInit(MIPC_TRANSFER_T* transfer_ptr)
 753 {
 754         if(!transfer_ptr) {
 755                 panic("_Init_Frame_List: frame_list_ptr=NULL!\r\n");
 756                 return;
 757         }
 758
 759         INIT_LIST_HEAD(&transfer_ptr->frame_fifo);
 760         mutex_init(&transfer_ptr->transfer_mutex);
 761         transfer_ptr->counter = 0;
 762         transfer_ptr->cur_frame_ptr = NULL;
 763         transfer_ptr->frame_count = 0;
 764         init_waitqueue_head(&transfer_ptr->frame_free_wq);
 765 }
 766
 767 static void _transfer_frame_init(void)
 768 {
 769         s_mipc_rx_buf =  (u8*) __get_free_pages(GFP_KERNEL, get_order(MAX_MIPC_RX_FRAME_SIZE));
 770
 771         WARN_ON(NULL == s_mipc_rx_buf);
 772
 773         if(kfifo_alloc(&s_mipc_rx_cache_kfifo,MAX_MIPC_RX_CACHE_SIZE, GFP_KERNEL)) {
 774                 IPC_SDIO_ERR("_transfer_frame_init: kfifo rx cache no memory!\r\n");
 775                 panic("%s[%d]kfifo rx cache no memory", __FILE__, __LINE__);
 776         }
 777         _TxFreeFrameList_Init(&s_mipc_tx_free_frame_list);
 778         _TransferInit(&s_mipc_tx_tansfer);
 779
 780 }
 781
 782 MIPC_TRANSF_FRAME_T* _AllocFrame(MIPC_FRAME_LIST_T*  frame_list_ptr)
 783 {
 784         MIPC_TRANSF_FRAME_T*  frame_ptr = NULL;
 785
 786         if(!frame_list_ptr) {
 787                 panic("%s[%d] frame_list_ptr = NULL!\r\n", __FILE__, __LINE__);
 788         }
 789
 790         mutex_lock(&frame_list_ptr->list_mutex);/*get  lock */
 791         if(!list_empty(&frame_list_ptr->frame_list_head)) {
 792                 frame_ptr = list_entry(frame_list_ptr->frame_list_head.next, MIPC_TRANSF_FRAME_T, link);
 793                 list_del(&frame_ptr->link);
 794                 frame_ptr->pos = sizeof(struct packet_header);
 795                 frame_ptr->flag = 1;
 796                 frame_list_ptr->counter--;
 797         }
 798         mutex_unlock(&frame_list_ptr->list_mutex);/*set  lock */
 799         IPC_SDIO_DEBUG("_AllocFrame:0x%X\r\n", (u32)frame_ptr);
 800         return  frame_ptr;
 801 }
 802
 803 static void _FreeFrame(MIPC_TRANSF_FRAME_T* frame_ptr, MIPC_FRAME_LIST_T*  frame_list_ptr)
 804 {
 805         if(!frame_list_ptr || !frame_ptr) {
 806                 panic("%s[%d] frame_list_ptr = NULL!\r\n", __FILE__, __LINE__);
 807         }
 808         IPC_SDIO_DEBUG("_FreeFrame:0x%x\r\n", (u32)frame_ptr);
 809         mutex_lock(&frame_list_ptr->list_mutex);/*get   lock */
 810         frame_ptr->pos = 0;
 811         frame_ptr->flag = 0;
 812         list_add_tail(&frame_ptr->link, &frame_list_ptr->frame_list_head);
 813         frame_list_ptr->counter++;
 814         mutex_unlock(&frame_list_ptr->list_mutex);/*set  lock */
 815         _WakeTxTransfer();
 816 }
 817
 818 static  void _AddFrameToTxTransferFifo(MIPC_TRANSF_FRAME_T* frame_ptr, MIPC_TRANSFER_T*  transfer_ptr)
 819 {
 820         struct packet_header*   header_ptr = ( struct packet_header* )frame_ptr->buf_ptr;
 821         header_ptr->tag = 0x7e7f;
 822         header_ptr->flag = 0xaa55;
 823         header_ptr->length =     frame_ptr->pos - sizeof(struct packet_header);
 824         header_ptr->frame_num = s_tx_frame_counter++; //sending_cnt;
 825         header_ptr->u.emergency_cmd = 0xabcdef00;
 826         header_ptr->next_length = 0xFFFFEEEE;
 827         header_ptr->reserved[0] = 0x11112222;
 828         header_ptr->reserved[1] = 0x33334444;
 829         header_ptr->reserved[2] = 0x55556666;
 830         list_add_tail(&frame_ptr->link,  &transfer_ptr->frame_fifo);
 831         transfer_ptr->frame_count++;
 832 }
 833
 834 static  u32 _GetFrameFromTxTransfer(MIPC_TRANSF_FRAME_T* * out_frame_ptr)
 835 {
 836         MIPC_TRANSF_FRAME_T* frame_ptr = NULL;
 837         MIPC_TRANSFER_T*  transfer_ptr =  &s_mipc_tx_tansfer;
 838         mutex_lock(&transfer_ptr->transfer_mutex);/*get  lock */
 839         if(!list_empty(&transfer_ptr->frame_fifo)) {
 840                 frame_ptr = list_entry(transfer_ptr->frame_fifo.next, MIPC_TRANSF_FRAME_T, link);
 841                 list_del(&frame_ptr->link);
 842                 transfer_ptr->frame_count--;
 843         }
 844         mutex_unlock(&transfer_ptr->transfer_mutex);/*set  lock */
 845
 846         if(!frame_ptr) {
 847                 return 1;
 848         }
 849
 850         *out_frame_ptr = frame_ptr;
 851         return 0;
 852 }
 853
 854 static  u32  _IsTransferFifoEmpty(MIPC_TRANSFER_T* transfer_ptr)
 855 {
 856         u32  ret = 0;
 857         mutex_lock(&transfer_ptr->transfer_mutex);/*get  lock */
 858         ret = list_empty(&transfer_ptr->frame_fifo);
 859         mutex_unlock(&transfer_ptr->transfer_mutex);/*set  lock */
 860         return ret;
 861 }
 862
 863 u32 s_need_wake_up_tx_thread = 0;
 864
 865 static u32 _AddDataToTxTransfer(u8* data_ptr, u32 len)
 866 {
 867         u32 ret = 0;
 868         MIPC_TRANSF_FRAME_T* frame_ptr = NULL;
 869         MIPC_TRANSF_FRAME_T* new_frame_ptr = NULL;
 870         MIPC_TRANSFER_T* transfer_ptr = &s_mipc_tx_tansfer;
 871         mutex_lock(&transfer_ptr->transfer_mutex);/*get  lock */
 872
 873         if(0 == transfer_ptr->counter) {
 874                 s_need_wake_up_tx_thread = 1;
 875         }
 876         do {
 877                 frame_ptr = transfer_ptr->cur_frame_ptr;
 878                 if(!frame_ptr) {
 879                         frame_ptr =  _AllocFrame(&s_mipc_tx_free_frame_list);
 880                 }
 881                 if(!frame_ptr) {
 882                         // printk("%s[%d]_AddDataToFrame No Empty Frame!\r\n", __FILE__, __LINE__);
 883                         ret = 0;
 884                         break;
 885                 }
 886                 if(len > (frame_ptr->buf_size - sizeof( struct packet_header))) {
 887                         IPC_SDIO_ERR("[mipc] _AddDataToFrame    data too long!\r\n");
 888                         ret = 0;
 889                         break;
 890                 }
 891                 if((len + frame_ptr->pos) > frame_ptr->buf_size) {
 892                         new_frame_ptr =  _AllocFrame(&s_mipc_tx_free_frame_list);
 893                         if(!new_frame_ptr) {
 894                                 // printk("%s[%d]_AddDataToFrame No Empty Frame : pos:%d, data len:%d\r\n", "ipc_sdio.c", __LINE__, frame_ptr->pos, len);
 895                                 ret = 0;
 896                                 break;
 897                         }
 898                         _AddFrameToTxTransferFifo(frame_ptr, transfer_ptr);
 899                         frame_ptr = new_frame_ptr;
 900                         s_need_wake_up_tx_thread = 1;
 901                 }
 902                 memcpy(&frame_ptr->buf_ptr[frame_ptr->pos], data_ptr, len);
 903                 frame_ptr->pos  += len;
 904                 transfer_ptr->counter += len;
 905                 transfer_ptr->cur_frame_ptr = frame_ptr;
 906                 ret = len;
 907         } while(0);
 908
 909         mutex_unlock(&transfer_ptr->transfer_mutex);/*set       lock */
 910
 911         return ret;
 912 }
 913
 914 static void _WaitTxTransferFree(void)
 915 {
 916         wait_event(s_mipc_tx_tansfer.frame_free_wq, (s_mipc_tx_free_frame_list.counter ||
 917                                  (s_mux_ipc_event_flags & MUX_IPC_WRITE_DISABLE)));
 918 }
 919
 920 static void _WakeTxTransfer(void)
 921 {
 922         wake_up(&s_mipc_tx_tansfer.frame_free_wq);
 923 }
 924
 925 static u32 _DelDataFromTxTransfer(MIPC_TRANSF_FRAME_T* frame_ptr)
 926 {
 927         MIPC_TRANSFER_T* transfer_ptr  = &s_mipc_tx_tansfer;
 928         mutex_lock(&transfer_ptr->transfer_mutex);
 929         transfer_ptr->counter -=  frame_ptr->pos - sizeof(struct packet_header);
 930         IPC_SDIO_DEBUG("[mipc] _DelDataFromTxTransfer transfer_ptr->counter = %d\n", transfer_ptr->counter);
 931         mutex_unlock(&transfer_ptr->transfer_mutex);
 932         //_FreeFrame(frame_ptr, &s_mipc_tx_free_frame_list); //sdio opt 1, do not free here
 933         return 0;
 934 }
 935
 936
 937 static u32 _FreeAllTxTransferFrame(void)
 938 {
 939         MIPC_TRANSF_FRAME_T*  frame_ptr = NULL;
 940         free_all_tx_frame_in_fifo();
 941         while(!_GetFrameFromTxTransfer(&frame_ptr)) {
 942                 _DelDataFromTxTransfer(frame_ptr);
 943                 _FreeFrame(frame_ptr, &s_mipc_tx_free_frame_list);
 944         }
 945         return 0;
 946 }
 947
 948
 949 static  u32 _FlushTxTransfer(void)
 950 {
 951         u32 ret = 0;
 952         MIPC_TRANSFER_T* transfer_ptr  = &s_mipc_tx_tansfer;
 953         mutex_lock(&transfer_ptr->transfer_mutex);/*get  lock */
 954         do {
 955                 if((transfer_ptr->counter == 0) || !transfer_ptr->cur_frame_ptr ||
 956                     (transfer_ptr->cur_frame_ptr->pos == sizeof( struct packet_header))) {
 957                         ret = 1;
 958                         break;
 959                 }
 960                 _AddFrameToTxTransferFifo(transfer_ptr->cur_frame_ptr, transfer_ptr);
 961                 transfer_ptr->cur_frame_ptr = NULL;
 962         } while(0);
 963         mutex_unlock(&transfer_ptr->transfer_mutex);/*set       lock */
 964         return  ret;
 965 }
 966
 967 u32 mux_ipc_GetTxTransferSavedCount(void)
 968 {
 969         u32 count = 0;
 970         MIPC_TRANSFER_T* transfer_ptr  = &s_mipc_tx_tansfer;
 971         mutex_lock(&transfer_ptr->transfer_mutex);
 972         count = transfer_ptr->counter;
 973         mutex_unlock(&transfer_ptr->transfer_mutex);
 974         return count;
 975 }
 976 static size_t sdio_write_modem_data(const u8 * buf, u32 len)
 977 {
 978         size_t ret = 0;
 979         u32  result =  SDHCI_TRANSFER_OK;
 980         u32 resend_count = 0;
 981
 982         wake_lock(&s_ipc_sdio_wake_lock);
 983
 984         do {
 985                 IPC_SDIO_INFO("SDIO  WRITE START\n");
 986
 987                 ipc_info_change_status(IPC_TX_CHANNEL, IPC_STATUS_CONNECTED);
 988                 ret = sprd_sdio_channel_tx(buf, len, (resend_count & ((1 << 17) - 1)));
 989                 if(!ret) {
 990                         set_cp_awake(true);
 991                         IPC_SDIO_INFO("SDIO  WRITE SUCESS\n");
 992                         result =  SDHCI_TRANSFER_OK;
 993                         ret = len;
 994                 } else {
 995                         ipc_info_error_status(IPC_TX_CHANNEL, IPC_STATUS_CRC_ERROR);
 996                         result =  SDHCI_TRANSFER_ERROR;
 997                         IPC_SDIO_ERR("SDIO  WRITE FAIL ret= %d\n", ret);
 998                         ret = 0;
 999                 }
1000
1001
1002                 ipc_info_change_status(IPC_TX_CHANNEL, IPC_STATUS_DISCONNECTED);
1003
1004                 if(!_is_mux_ipc_enable()) {
1005                         IPC_SDIO_ERR("[mipc] Found mux ipc disabled in do_sdio_tx\r \n", ret);
1006                         break;
1007                 }
1008                 if(result) {
1009                         resend_count++;
1010                         msleep(200);
1011                 }
1012         } while(result && (resend_count < MAX_SDIO_TX_RETRY));
1013
1014         wake_unlock(&s_ipc_sdio_wake_lock);
1015
1016         ipc_info_change_status(IPC_TX_CHANNEL, IPC_STATUS_IDLE);
1017         if(resend_count >= MAX_SDIO_TX_RETRY) {
1018 #if 0
1019                 while(1) {
1020                         msleep(2000);
1021                         printk("sdio_write_modem_data  write fail 3 times \n");
1022                 }
1023 #else
1024                 IPC_SDIO_ERR("sdio_write_modem_data  write fail 3 times \n");
1025 #endif
1026         }
1027
1028         return ret;
1029
1030 }
1031
1032 static int sdio_read_modem_data(u8 *buf, int len, int addr)
1033 {
1034         int ret = 0;
1035         IPC_SDIO_INFO("[mipc] sdio_read_modem_data entery:buf:0x%X, len:%x\r\n", (u32)buf, len);
1036         ret = sprd_sdio_channel_rx(buf, len, addr);
1037         return ret;
1038 }
1039
1040 extern  __u8   mux_calc_crc(__u8 * data, __u32 length);
1041
1042 unsigned long s_dbg_dl_frame_num = 0;
1043 static bool VerifyPacketHeader(struct packet_header *header, u32 *tx_flow_info,
1044                                u32 *acked_tx_frame)
1045 {
1046         if(0) { //(sdio_transfer_crc_check_enable)
1047                 __u8*  data_ptr = (__u8*)(header + 1);
1048                 __u8   crc_value = mux_calc_crc(data_ptr,  header->length );
1049                 if ( (header->tag != HEADER_TAG) || ((header->flag & 0xFF00) != HEADER_TYPE)
1050                      || (header->length > MAX_MIPC_RX_FRAME_SIZE)
1051                      ||(header->frame_num != crc_value)) {
1052                         IPC_SDIO_ERR("[mipc]:%s error, tag:0x%X, type:0x%X, len:0x%X, crc:0x%X, calc_crc:0x%X\r\n",
1053                                      __func__, header->tag , header->flag, header->length,header->frame_num, crc_value);
1054                         return false;
1055                 }
1056         } else {
1057                 if ( (header->tag != HEADER_TAG) || ((header->flag & 0xFF00) != HEADER_TYPE)
1058                      || (header->length > MAX_MIPC_RX_FRAME_SIZE)) {
1059                         IPC_SDIO_ERR("[mipc]:%s error, tag:0x%X, type:0x%X, len:0x%X, frame_num:0x%X\r\n",
1060                                      __func__, header->tag , header->flag, header->length,header->frame_num);
1061                         return false;
1062                 } else {
1063                         *tx_flow_info = header->flag & 0xFF;
1064                         *acked_tx_frame = header->u.ul_frame_num;
1065                         if((s_dbg_dl_frame_num + 1) != header->frame_num) {
1066                                 IPC_SDIO_ERR("[mipc]:(s_dbg_dl_frame_num + 1) != header->frame_num!!\r\n");
1067                         }
1068                         s_dbg_dl_frame_num = header->frame_num;
1069                         IPC_SDIO_DEBUG("[mipc]:s_dbg_dl_frame_num:%d!\r\n", s_dbg_dl_frame_num);
1070                         s_mipc_next_rx_len = header->next_length;
1071                 }
1072         }
1073
1074         return true;
1075 }
1076
1077 static inline bool have_buffer_to_read(void)
1078 {
1079         return (kfifo_avail(&s_mipc_rx_cache_kfifo) >= MAX_MIPC_RX_FRAME_SIZE);
1080 }
1081 u32  process_modem_packet(unsigned long data)
1082 {
1083         if(!have_buffer_to_read()) {
1084                 IPC_SDIO_ERR("[MIPC] MIPC Rx Cache Full!\r\n");
1085         }
1086         wait_event(s_rx_fifo_avail, have_buffer_to_read());
1087
1088         //send sdio read request
1089         IPC_SDIO_DEBUG("[MIPC] MIPC Rx Cache Free!\r\n");
1090         s_mipc_rx_event_flags = 0;
1091         s_mipc_rx_req_flag = 1;
1092         wake_up(&s_mux_ipc_sdio_wq);
1093
1094         return 0;
1095 }
1096
1097 #ifdef SDIO_GPIO_TEST
1098
1099 unsigned long s_dbg_cp2ap_cnt = 0;
1100 int s_dbg_cp2ap_last_val;
1101
1102 static int mux_test_cp2ap_rdy(void)
1103 {
1104         int val;
1105         val = cp2ap_req();
1106
1107         IPC_SDIO_DEBUG("[mipc_test] cp2ap_req value after write data:%d\r\n", val);
1108         if(s_dbg_cp2ap_cnt > 10) {
1109                 if(s_dbg_cp2ap_last_val == val) {
1110                         while(1) {
1111                                 IPC_SDIO_ERR("[mipc_test] s_dbg_cp2ap_last_val == val\r\n");
1112                                 msleep(20);
1113                         }
1114                 }
1115         }
1116         s_dbg_cp2ap_cnt++;
1117         s_dbg_cp2ap_last_val = val;
1118
1119         return 0;
1120 }
1121
1122 #endif
1123
1124 #define TX_THRD_GATHER_COND (s_mipc_tx_tansfer.frame_count || ((s_mipc_tx_ctrl.fifo_wr == s_mipc_tx_ctrl.fifo_rd)&& s_tx_flow_info))
1125 static int mux_ipc_tx_thread(void *data)
1126 {
1127         MIPC_TRANSF_FRAME_T*  frame_ptr = NULL;
1128         struct sched_param       param = {.sched_priority = 10};
1129
1130         IPC_SDIO_INFO("mux_ipc_tx_thread");
1131         sched_setscheduler(current, SCHED_FIFO, &param);
1132
1133
1134         while (!kthread_should_stop()) {
1135                 wait_event(s_mux_ipc_tx_wq,  s_mipc_tx_tansfer.counter);
1136
1137                 if(!s_mipc_tx_tansfer.counter || (s_mipc_tx_tansfer.counter > MAX_MIPC_TX_FRAME_SIZE)) {
1138                         IPC_SDIO_DEBUG("[mipc] s_mipc_tx_tansfer.counter:%d\r\n", s_mipc_tx_tansfer.counter);
1139                 }
1140
1141                 while(s_mipc_tx_tansfer.counter) {
1142                         if(_IsTransferFifoEmpty(&s_mipc_tx_tansfer)) {
1143                                 //do not send right now, because now sdio is pending
1144                                 wait_event(s_mux_ipc_tx_wq, TX_THRD_GATHER_COND);
1145                                 IPC_SDIO_DEBUG("[mipc] tx thread wait TX_THRD_GATHER_COND OK!\r\n");
1146                         }
1147                         do {
1148
1149                                 if(_IsTransferFifoEmpty(&s_mipc_tx_tansfer)) {
1150                                         if(_FlushTxTransfer()) {
1151                                                 IPC_SDIO_DEBUG("[mipc] s_mipc_tx_tansfer.counter: %d\n", s_mipc_tx_tansfer.counter);
1152                                                 IPC_SDIO_DEBUG("[mipc] transfer_ptr->cur_frame_ptr: 0x%X\n", s_mipc_tx_tansfer.cur_frame_ptr);
1153                                                 if(s_mipc_tx_tansfer.cur_frame_ptr) {
1154                                                         IPC_SDIO_DEBUG("[mipc] cur_frame_ptr->pos: %d\n", s_mipc_tx_tansfer.cur_frame_ptr->pos);
1155                                                 }
1156                                                 IPC_SDIO_WARN("[mipc] No Data To Send\n");
1157                                                 break;
1158                                         }
1159                                 }
1160
1161                                 if(_GetFrameFromTxTransfer(&frame_ptr)) {
1162                                         IPC_SDIO_ERR("[mipc] Error: Flush Empty Frame \n");
1163                                         break;
1164                                 }
1165
1166                                 _DelDataFromTxTransfer(frame_ptr);
1167
1168                                 IPC_SDIO_DEBUG("[mipc] sending frame count: %d\n", (MAX_MIPC_TX_FRAME_NUM - s_mipc_tx_free_frame_list.counter));
1169                                 put_to_sdio_tx_fifo(frame_ptr);
1170                         } while(0);
1171
1172                 }
1173         }
1174
1175         sprd_sdio_channel_close();
1176         sdhci_hal_gpio_exit();
1177
1178         return 0;
1179 }
1180
1181
1182
1183 static int mux_ipc_xmit_buf(const char *buf, ssize_t len)
1184 {
1185         ssize_t ret = -1;
1186
1187         mutex_lock(&sdio_tx_lock);
1188         do {
1189                 ret = _AddDataToTxTransfer((u8*)buf, len);
1190                 if(!ret) {
1191                         ipc_info_sdio_write_overflow(1);
1192                         IPC_SDIO_WARN("[mipc] mux_ipc_xmit_buf begin _WaitTxTransferFree\n");
1193                         _WaitTxTransferFree();
1194                         IPC_SDIO_WARN("[mipc] mux_ipc_xmit_buf end _WaitTxTransferFree\n");
1195                         if(s_mux_ipc_event_flags & MUX_IPC_WRITE_DISABLE) {
1196                                 break;
1197                         }
1198                 }
1199         } while(!ret);
1200
1201         ipc_info_mux_write(len);
1202
1203         if(s_need_wake_up_tx_thread) {
1204                 s_need_wake_up_tx_thread = 0;
1205                 wake_up(&s_mux_ipc_tx_wq);
1206         }
1207         mutex_unlock(&sdio_tx_lock);
1208         return ret;
1209 }
1210
1211 static int mux_ipc_create_tx_thread(void)
1212 {
1213         IPC_SDIO_INFO("mux_ipc_create_tx_thread enter.\n");
1214         init_waitqueue_head(&s_mux_ipc_tx_wq);
1215         s_mux_ipc_tx_thread = kthread_create(mux_ipc_tx_thread, NULL, "mipc_tx_thread");
1216
1217         if (IS_ERR(s_mux_ipc_tx_thread)) {
1218                 IPC_SDIO_ERR("mux_ipc_tx_thread error!.\n");
1219                 return -1;
1220         }
1221
1222         wake_up_process(s_mux_ipc_tx_thread);
1223
1224         return 0;
1225 }
1226
1227
1228 u32  wake_up_mipc_rx_thread(u32   even_flag)
1229 {
1230         u32 status = 0;
1231         u32 ipc_status = _is_mux_ipc_enable();
1232
1233         wake_lock_timeout(&s_cp_req_wake_lock, HZ / 2);
1234         if(ipc_status && even_flag) {
1235                 s_mipc_rx_event_flags = even_flag;
1236                 wake_up(&s_mux_ipc_rx_wq);
1237                 status = 0;
1238         } else {
1239                 IPC_SDIO_ERR("mux ipc rx invaild wakeup, ipc status:%u, flag:%d\r\n", ipc_status, even_flag);
1240                 status = -1;
1241         }
1242         return  status;
1243 }
1244
1245 static int mux_ipc_rx_thread(void *data)
1246 {
1247         struct sched_param       param = {.sched_priority = 25};
1248         IPC_SDIO_INFO("mux_ipc_rx_thread enter\r\n");
1249         sched_setscheduler(current, SCHED_FIFO, &param);
1250
1251         wait_cp_bootup();
1252         msleep(500);
1253
1254         IPC_SDIO_INFO("mux_ipc_rx_thread start----\r\n");
1255         //check CP status when start up
1256         if(cp2ap_req()) {
1257                 s_mipc_rx_event_flags = 1;
1258         }
1259         //working loop
1260         while (!kthread_should_stop()) {
1261                 wait_event(s_mux_ipc_rx_wq,  s_mipc_rx_event_flags);
1262                 process_modem_packet(0);
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int mux_ipc_create_rx_thread(void)
1269 {
1270         IPC_SDIO_INFO("mux_ipc_rx_create_thread enter.\n");
1271         init_waitqueue_head(&s_mux_ipc_rx_wq);
1272         s_mux_ipc_rx_thread = kthread_create(mux_ipc_rx_thread, NULL, "mipc_rx_thread");
1273
1274         if (IS_ERR(s_mux_ipc_rx_thread)) {
1275                 IPC_SDIO_ERR("ipc_sdio.c:mux_ipc_rx_thread error!.\n");
1276                 return -1;
1277         }
1278
1279         wake_up_process(s_mux_ipc_rx_thread);
1280
1281         return 0;
1282 }
1283
1284 static int do_sdio_rx(u32 *tx_flow_info, u32 *acked_tx_frame)
1285 {
1286         u32 receve_len = 0;
1287         int ret = 0;
1288         int result = SDHCI_TRANSFER_OK;
1289         int resend_count = 0;
1290         struct packet_header *packet = NULL;
1291         u32 rx_buf_len;
1292
1293         rx_buf_len = s_mipc_next_rx_len;
1294         wake_lock(&s_ipc_sdio_wake_lock);
1295         do {
1296                 IPC_SDIO_DEBUG(" sdio_read_modem_data xxxx................\r\n");
1297
1298                 ipc_info_change_status(IPC_RX_CHANNEL, IPC_STATUS_CONNECTED);
1299
1300                 memset(s_mipc_rx_buf, 0xaa, MAX_MIPC_RX_FRAME_SIZE);
1301
1302                 if(!have_buffer_to_read()) {
1303                         panic("do_sdio_rx have no buffer to read!\r\n");
1304                 }
1305
1306 #ifdef SDIO_VARIABLE_DL_LEN
1307                 ret = sdio_read_modem_data(s_mipc_rx_buf,  rx_buf_len, (resend_count != 0));
1308 #else
1309                 ret = sdio_read_modem_data(s_mipc_rx_buf,  MAX_MIPC_RX_FRAME_SIZE, (resend_count != 0));
1310 #endif
1311                 if (!ret) {
1312                         set_cp_awake(true);
1313                         //calc phy read speed
1314 #ifdef SDIO_VARIABLE_DL_LEN
1315                         ipc_info_sdio_read(rx_buf_len);
1316 #else
1317                         ipc_info_sdio_read(MAX_MIPC_RX_FRAME_SIZE);
1318 #endif
1319
1320
1321
1322                         packet=(struct packet_header *)s_mipc_rx_buf;
1323                         if(VerifyPacketHeader(packet, tx_flow_info, acked_tx_frame)) {
1324                                 result = SDHCI_TRANSFER_OK;
1325                         } else {
1326                                 ipc_info_error_status(IPC_RX_CHANNEL, IPC_STATUS_PACKET_ERROR);
1327                                 result = SDHCI_TRANSFER_ERROR;
1328                                 IPC_SDIO_ERR("[mipc] Sdio Rx Packet check error tag:0x%X, len:%d, ul_frame_num:0x%x\n", packet->tag, packet->length, packet->u.ul_frame_num);
1329                         }
1330 #ifdef SDIO_VARIABLE_DL_LEN
1331                         if (packet->length > rx_buf_len) {
1332                                 result = SDHCI_TRANSFER_ERROR;
1333                                 IPC_SDIO_ERR("[mipc]SDIO READ FAIL, packet->length(%d) > rx_buf_len(%d)\r \n", packet->length, rx_buf_len);
1334                                 rx_buf_len = MAX_MIPC_RX_FRAME_SIZE;
1335                         }
1336 #endif
1337                 } else {
1338                         ipc_info_error_status(IPC_RX_CHANNEL, IPC_STATUS_CRC_ERROR);
1339                         result = SDHCI_TRANSFER_ERROR;
1340                         IPC_SDIO_ERR("[mipc]SDIO READ FAIL, ret:%d\r \n", ret);
1341                 }
1342
1343
1344                 ipc_info_change_status(IPC_RX_CHANNEL, IPC_STATUS_DISCONNECTED);
1345
1346                 if(!_is_mux_ipc_enable()) {
1347                         IPC_SDIO_ERR("[mipc] Found mux ipc disabled in do_sdio_rx\r \n", ret);
1348                         break;
1349                 }
1350                 if(result) {
1351                         resend_count++;
1352                         msleep(2);
1353                 }
1354
1355         } while(result && (resend_count < MAX_SDIO_RX_RETRY));
1356
1357         ipc_info_change_status(IPC_RX_CHANNEL, IPC_STATUS_IDLE);
1358
1359         wake_unlock(&s_ipc_sdio_wake_lock);
1360
1361         if(!result) {
1362
1363                 ipc_info_rate(IPC_RX_CHANNEL, packet->length*1000/MAX_MIPC_RX_FRAME_SIZE);
1364                 ipc_info_sdio_read_payload(packet->length);
1365                 receve_len  = packet->length;
1366
1367                 IPC_SDIO_INFO("[mipc] read data len:%d\r\n", receve_len);
1368
1369                 if(sdio_transfer_frame_check_enable && sdio_frame_check(&s_mipc_rx_buf[sizeof(struct packet_header )], packet->length)) {
1370                         IPC_SDIO_ERR("[mipc]:sdio receved data frame error!\r\n");
1371                 }
1372
1373                 if(packet->length) {
1374                         kfifo_in(&s_mipc_rx_cache_kfifo,&s_mipc_rx_buf[sizeof(struct packet_header )], packet->length);
1375
1376                         wake_up(&s_mux_read_rts);
1377                 } else {
1378                         ipc_info_error_status(IPC_RX_CHANNEL, IPC_STATUS_INVALID_PACKET);
1379                 }
1380         } else {
1381                 receve_len  = 0;
1382                 IPC_SDIO_ERR("[mipc] receive data fail! result:%d\r\n", result);
1383         }
1384         return result;
1385 }
1386
1387
1388 static int do_sdio_tx(MIPC_TRANSF_FRAME_T* frame_ptr)
1389 {
1390         u32 write_len = 0;
1391         struct packet_header*   header_ptr = ( struct packet_header* )frame_ptr->buf_ptr;
1392
1393         //write len shall multi - 512 bytes,and min len = 4096
1394         write_len = (frame_ptr->pos <= MIN_MIPC_TX_FRAME_SIZE) ?
1395                     MIN_MIPC_TX_FRAME_SIZE : ((frame_ptr->pos + 0x1FF) & (~0x1FF));
1396
1397         s_last_tx_frame = header_ptr->frame_num;
1398         IPC_SDIO_INFO("[mipc] write data ptr: 0x%x, len:%d\r\n", frame_ptr->buf_ptr, frame_ptr->pos);
1399
1400         IPC_SDIO_DEBUG("[mipc] write data: 0x%x, 0x%x, 0x%x, 0x%x,\r\n", frame_ptr->buf_ptr[8],
1401                        frame_ptr->buf_ptr[9],
1402                        frame_ptr->buf_ptr[10],
1403                        frame_ptr->buf_ptr[11]);
1404         write_len = sdio_write_modem_data(frame_ptr->buf_ptr, write_len);
1405
1406         if(write_len) {
1407                 ipc_info_rate(IPC_TX_CHANNEL, (frame_ptr->pos - sizeof(struct packet_header))*1000/write_len);
1408                 ipc_info_sdio_write(write_len);
1409         }
1410
1411         return write_len;
1412 }
1413
1414 static void init_sdio_gpio_res()
1415 {
1416         int rval;
1417
1418         if(s_sdio_gpio_res_status != SDIO_GPIO_RES_USING) {
1419                 sdhci_hal_gpio_init();
1420                 do {
1421                         rval = sprd_sdio_channel_open();
1422                         IPC_SDIO_INFO("%s() sdio channel opened %d\n", __func__, rval);
1423                 } while(rval);
1424
1425                 sdhci_hal_gpio_irq_init();
1426                 s_sdio_gpio_res_status = SDIO_GPIO_RES_USING;
1427         }
1428
1429 }
1430
1431 static void free_sdio_gpio_res()
1432 {
1433         if(s_sdio_gpio_res_status != SDIO_GPIO_RES_FREE) {
1434                 sdhci_hal_gpio_exit();
1435                 sprd_sdio_channel_close();
1436                 s_sdio_gpio_res_status = SDIO_GPIO_RES_FREE;
1437                 wake_up(&s_sdio_gpio_res_free);
1438         }
1439 }
1440
1441 static int mux_ipc_sdio_thread(void *data)
1442 {
1443         struct sched_param       param = {.sched_priority = 35};
1444         u32                                                     continue_tx_cnt = 0;
1445         IPC_SDIO_INFO("mux_ipc_sdio_thread enter\r\n");
1446         sched_setscheduler(current, SCHED_FIFO, &param);
1447
1448         IPC_SDIO_INFO("mux_ipc_sdio_thread start----\r\n");
1449         while (!kthread_should_stop()) {
1450                 bool force_tx = false;
1451
1452                 //check mux_ipc driver is enabled
1453                 if(!_is_mux_ipc_enable()) {
1454
1455                         IPC_SDIO_WARN("[mipc] found s_mux_ipc_enable == false\r\n");
1456
1457                         free_sdio_gpio_res();
1458
1459                         IPC_SDIO_WARN("[mipc] start to wait bootup in mux_ipc_sdio_thread\r\n");
1460
1461                         wait_cp_bootup();
1462
1463                         IPC_SDIO_WARN("[mipc] wait bootup success in mux_ipc_sdio_thread\r\n");
1464
1465                         init_sdio_gpio_res();
1466                 }
1467
1468                 wait_event_timeout(s_mux_ipc_sdio_wq, (s_mipc_enable_change_flag || s_mipc_rx_req_flag || MIPC_TX_REQ_FLAG),
1469                                    msecs_to_jiffies(MAX_SDIO_SLEEP_TIMEOUT));
1470                 if(s_mipc_enable_change_flag) {
1471                         s_mipc_enable_change_flag = 0;
1472                         continue;
1473                 }
1474
1475                 IPC_SDIO_DEBUG("[mipc] wait_event_timeout rx_req tx_req\r\n");
1476                 if(!(s_mipc_rx_req_flag || MIPC_TX_REQ_FLAG)) {
1477                         //set ap inactive to let cp sleep
1478                         ap2cp_req_disable();
1479                         set_cp_awake(false);
1480
1481                         //wait for requests
1482                         IPC_SDIO_INFO("[mipc] start wait_event rx_req tx_req forever\r\n");
1483                         wait_event(s_mux_ipc_sdio_wq,  (s_mipc_enable_change_flag || s_mipc_rx_req_flag || MIPC_TX_REQ_FLAG));
1484                         if(s_mipc_enable_change_flag) {
1485                                 s_mipc_enable_change_flag = 0;
1486                                 continue;
1487                         }
1488                 }
1489
1490                 //check modem status
1491                 if(!_is_mux_ipc_enable()) {
1492                         continue;
1493                 }
1494
1495                 //set ap2cp active before transfer
1496                 ap2cp_req_enable();
1497                 //make sure cp is awake
1498                 if(!get_cp_awake()) {
1499
1500                         //wait cp ack
1501                         if(!wait_cp_awake(msecs_to_jiffies(MAX_SDIO_CP_ACK_TIMEOUT))) {
1502                                 IPC_SDIO_ERR("[MIPC] SDIO wait cp awake fail!\r\n");
1503
1504                                 //cp no ack, just discard a request
1505                                 ap2cp_req_disable();
1506                                 msleep(2);
1507
1508                                 continue;
1509
1510                         }
1511                         set_cp_awake(true);
1512                         if(MIPC_TX_REQ_FLAG) {
1513                                 force_tx = true;
1514                         }
1515                 }
1516
1517                 //do tx
1518                 if(MIPC_TX_REQ_FLAG) {
1519
1520                         MIPC_TRANSF_FRAME_T* frame = get_from_sdio_tx_fifo();
1521
1522                         if(frame) {
1523                                 do_sdio_tx(frame);
1524                                 continue_tx_cnt++;
1525                         }
1526
1527                         force_tx = false;
1528                 }
1529                 //check modem status
1530                 if(!_is_mux_ipc_enable()) {
1531                         continue;
1532                 }
1533
1534                 //do tx,check again
1535                 if(MIPC_TX_REQ_FLAG) {
1536
1537                         MIPC_TRANSF_FRAME_T* frame = get_from_sdio_tx_fifo();
1538
1539                         if(frame) {
1540                                 do_sdio_tx(frame);
1541                                 continue_tx_cnt++;
1542                         }
1543
1544                         force_tx = false;
1545                 }
1546                 //check modem status
1547                 if(!_is_mux_ipc_enable()) {
1548                         continue;
1549                 }
1550
1551                 //do rx
1552                 if(s_mipc_rx_req_flag && !force_tx) {
1553                         int result;
1554                         u32 last_tx_flow_info = s_tx_flow_info;
1555
1556                         result = do_sdio_rx(&s_tx_flow_info, &s_acked_tx_frame);
1557                         s_mipc_rx_req_flag = 0;
1558                         continue_tx_cnt = 0;
1559
1560                         if(SDHCI_TRANSFER_OK == result) {
1561                                 //out of flow ctrl, wake up tx thread
1562                                 if(!last_tx_flow_info && s_tx_flow_info) {
1563                                         wake_up(&s_mux_ipc_tx_wq);
1564                                         printk("[mipc] exit ul flow ctrl, s_tx_flow_info:%d\n", s_tx_flow_info);
1565                                 } else if(!s_tx_flow_info && last_tx_flow_info) {
1566                                         printk("[mipc] enter ul flow ctrl,s_tx_flow_info:%d\n", s_tx_flow_info);
1567                                 }
1568
1569                                 IPC_SDIO_DEBUG("[mipc] last_ack_frame:%d, s_acked_tx_frame:%d, s_last_tx_frame:%d\n",
1570                                                s_mipc_tx_ctrl.last_ack_frame,
1571                                                s_acked_tx_frame,
1572                                                s_last_tx_frame);
1573
1574                                 if(s_mipc_tx_ctrl.last_ack_frame != s_acked_tx_frame) {
1575
1576                                         ack_tx_frame_num(s_acked_tx_frame);
1577                                 }
1578
1579                                 if(s_acked_tx_frame != s_last_tx_frame) {
1580
1581                                         nack_tx_frame_num();
1582                                 }
1583
1584                                 if(s_tx_flow_info == 0) {
1585                                         ipc_info_error_status(IPC_TX_CHANNEL, IPC_STATUS_FLOW_STOP);
1586                                 }
1587                         }
1588
1589                 }
1590
1591                 //check modem status
1592                 if(!_is_mux_ipc_enable()) {
1593                         continue;
1594                 }
1595
1596
1597
1598                 //check cp read request after one cmd53
1599                 if(cp2ap_req()) {
1600                         continue_tx_cnt = 0;
1601                         if(have_buffer_to_read()) {
1602                                 s_mipc_rx_req_flag = 1;
1603                         } else {
1604                                 wake_up_mipc_rx_thread(1);
1605                         }
1606                 }
1607
1608                 if(continue_tx_cnt >= 2) {
1609                         continue_tx_cnt--;
1610                         //implicit_ack_tx_frame();
1611                 }
1612
1613                 //check need to wake tx_thread, nothing to send, wake up tx thread
1614                 if((s_mipc_tx_ctrl.fifo_wr == s_mipc_tx_ctrl.fifo_rd)
1615                     && s_tx_flow_info
1616                     && s_mipc_tx_tansfer.counter) {
1617                         wake_up(&s_mux_ipc_tx_wq);
1618                 }
1619
1620         }
1621
1622         return 0;
1623 }
1624
1625 static int mux_ipc_create_sdio_thread(void)
1626 {
1627         IPC_SDIO_INFO("mux_ipc_create_sdio_thread enter.\n");
1628         init_waitqueue_head(&s_mux_ipc_sdio_wq);
1629         s_mux_ipc_sdio_thread = kthread_create(mux_ipc_sdio_thread, NULL, "mipc_sdio_thread");
1630
1631         if (IS_ERR(s_mux_ipc_sdio_thread)) {
1632                 IPC_SDIO_ERR("ipc_sdio.c:s_mux_ipc_sdio_thread error!.\n");
1633                 return -1;
1634         }
1635
1636         wake_up_process(s_mux_ipc_sdio_thread);
1637
1638         return 0;
1639 }
1640
1641 #ifdef SDIO_LOOP_TEST
1642
1643 static struct task_struct *s_mux_ipc_test_rx_thread;
1644 static struct task_struct *s_mux_ipc_test_tx_thread;
1645
1646
1647 static int mux_ipc_test_rx_thread(void *data)
1648 {
1649         struct sched_param       param = {.sched_priority = 15};
1650         IPC_SDIO_INFO("mux_ipc_test_rx_thread enter\r\n");
1651         sched_setscheduler(current, SCHED_FIFO, &param);
1652
1653
1654
1655         IPC_SDIO_INFO("mux_ipc_test_rx_thread start----\r\n");
1656         while (!kthread_should_stop()) {
1657                 mux_ipc_sdio_test_read(NULL, 0);
1658         }
1659         return 0;
1660 }
1661
1662 static int mux_ipc_test_tx_thread(void *data)
1663 {
1664         struct sched_param       param = {.sched_priority = 15};
1665         IPC_SDIO_INFO("mux_ipc_test_tx_thread enter\r\n");
1666         sched_setscheduler(current, SCHED_FIFO, &param);
1667
1668
1669
1670         IPC_SDIO_INFO("mux_ipc_test_tx_thread start----\r\n");
1671
1672         msleep(100 * 1000);
1673         while (!kthread_should_stop()) {
1674                 mux_ipc_sdio_write_test(NULL, 0);
1675                 msleep(200);
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int mux_ipc_create_test_tx_thread(void)
1682 {
1683         IPC_SDIO_INFO("mux_ipc_create_test_tx_thread enter.\n");
1684         s_mux_ipc_test_tx_thread = kthread_create(mux_ipc_test_tx_thread, NULL, "mipc_test_tx_thrd");
1685
1686         if (IS_ERR(s_mux_ipc_test_tx_thread)) {
1687                 IPC_SDIO_ERR("ipc_sdio.c:s_mux_ipc_sdio_thread error!.\n");
1688                 return -1;
1689         }
1690
1691         wake_up_process(s_mux_ipc_test_tx_thread);
1692
1693         return 0;
1694 }
1695
1696 static int mux_ipc_create_test_rx_thread(void)
1697 {
1698         IPC_SDIO_INFO("mux_ipc_create_test_rx_thread enter.\n");
1699         s_mux_ipc_test_rx_thread = kthread_create(mux_ipc_test_rx_thread, NULL, "mipc_test_rx_thrd");
1700
1701         if (IS_ERR(s_mux_ipc_test_rx_thread)) {
1702                 IPC_SDIO_ERR("ipc_sdio.c:s_mux_ipc_sdio_thread error!.\n");
1703                 return -1;
1704         }
1705
1706         wake_up_process(s_mux_ipc_test_rx_thread);
1707
1708         return 0;
1709 }
1710
1711 #endif
1712
1713
1714 static int modem_sdio_probe(struct platform_device *pdev)
1715 {
1716         int retval = 0;
1717
1718         IPC_SDIO_INFO("modem_sdio_probe\n");
1719         //debug{
1720         ipc_info_error_status(IPC_RX_CHANNEL, IPC_STATUS_FLOW_STOP);
1721         //}debug
1722
1723         wake_lock_init(&s_ipc_sdio_wake_lock, WAKE_LOCK_SUSPEND, "ipc_sdio_lock");
1724         wake_lock_init(&s_cp_req_wake_lock, WAKE_LOCK_SUSPEND, "sdio_cp_req_lock");
1725         mutex_init(&ipc_mutex);
1726         //atomic_set(&s_mipc_read_pending, 0);
1727         init_cp_awake_status();
1728         init_mipc_tx_ctrl();
1729         mux_ipc_create_sdio_thread();
1730         mux_ipc_create_tx_thread();
1731         mux_ipc_create_rx_thread();
1732
1733 #ifdef SDIO_LOOP_TEST
1734         mux_ipc_create_test_rx_thread();
1735         mux_ipc_create_test_tx_thread();
1736 #endif
1737         return retval;
1738 }
1739
1740 static int modem_sdio_remove(struct platform_device *pdev)
1741 {
1742         return 0;
1743 }
1744
1745
1746 static struct platform_driver modem_sdio_driver = {
1747         .probe = modem_sdio_probe,
1748         .remove = modem_sdio_remove,
1749         .driver = {
1750                 .name = "ipc_sdio",
1751         }
1752 };
1753
1754 static struct sprdmux sprd_iomux = {
1755         .id             = 1,
1756         .io_read        = mux_ipc_sdio_read,
1757         .io_write       = mux_ipc_sdio_write,
1758         .io_stop  =  mux_ipc_sdio_stop,
1759 };
1760
1761 static int __init mux_ipc_sdio_init(void)
1762 {
1763
1764         int retval;
1765         IPC_SDIO_INFO("mux_ipc_sdio_init\n");
1766
1767         _transfer_frame_init();
1768         init_waitqueue_head(&s_mux_read_rts);
1769         init_waitqueue_head(&s_rx_fifo_avail);
1770         init_waitqueue_head(&s_modem_ready);
1771         init_waitqueue_head(&s_sdio_gpio_res_free);
1772         sprdmux_register(&sprd_iomux);
1773         retval = platform_driver_register(&modem_sdio_driver);
1774         if (retval) {
1775                 IPC_SDIO_ERR("[sdio]: register modem_sdio_driver error:%d\r\n", retval);
1776         }
1777
1778         s_mux_ipc_module_inited = 1;
1779
1780         return retval;
1781 }
1782
1783 static void __exit mux_ipc_sdio_exit(void)
1784 {
1785         platform_driver_unregister(&modem_sdio_driver);
1786 }
1787
1788
1789 module_param_named(sdio_transfer_crc_check_enable, sdio_transfer_crc_check_enable, int, S_IRUGO | S_IWUSR);
1790 module_param_named(sdio_transfer_frame_check_enable, sdio_transfer_frame_check_enable, int, S_IRUGO | S_IWUSR);
1791 module_param_named(sdio_tx_wait_time, sdio_tx_wait_time, int, S_IRUGO | S_IWUSR);
1792
1793
1794
1795 module_init(mux_ipc_sdio_init);
1796 module_exit(mux_ipc_sdio_exit);
1797
1798 MODULE_LICENSE("GPL");
1799 MODULE_AUTHOR("Bin.Xu<bin.xu@spreadtrum.com>");
1800 MODULE_DESCRIPTION("MUX SDIO Driver");