drivers/char/hw_random/iproc-rng200.c

   1 /*
   2 * Copyright (C) 2015 Broadcom Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation version 2.
   7 *
   8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9 * kind, whether express or implied; without even the implied warranty
  10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 /*
  14  * DESCRIPTION: The Broadcom iProc RNG200 Driver
  15  */
  16
  17 #include <linux/hw_random.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/delay.h>
  26
  27 /* Registers */
  28 #define RNG_CTRL_OFFSET                                 0x00
  29 #define RNG_CTRL_RNG_RBGEN_MASK                         0x00001FFF
  30 #define RNG_CTRL_RNG_RBGEN_ENABLE                       0x00000001
  31 #define RNG_CTRL_RNG_DIV_CTRL_SHIFT                     13
  32
  33 #define RNG_SOFT_RESET_OFFSET                           0x04
  34 #define RNG_SOFT_RESET                                  0x00000001
  35
  36 #define RBG_SOFT_RESET_OFFSET                           0x08
  37 #define RBG_SOFT_RESET                                  0x00000001
  38
  39 #define RNG_TOTAL_BIT_COUNT_OFFSET                      0x0C
  40
  41 #define RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET            0x10
  42
  43 #define RNG_INT_STATUS_OFFSET                           0x18
  44 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK     0x80000000
  45 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
  46 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK               0x00000020
  47 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK        0x00000001
  48
  49 #define RNG_INT_ENABLE_OFFSET                           0x1C
  50
  51 #define RNG_FIFO_DATA_OFFSET                            0x20
  52
  53 #define RNG_FIFO_COUNT_OFFSET                           0x24
  54 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK              0x000000FF
  55 #define RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT         8
  56
  57 struct iproc_rng200_dev {
  58         struct hwrng rng;
  59         void __iomem *base;
  60 };
  61
  62 #define to_rng_priv(rng)        container_of(rng, struct iproc_rng200_dev, rng)
  63
  64 static void iproc_rng200_enable_set(void __iomem *rng_base, bool enable)
  65 {
  66         u32 val;
  67
  68         val = ioread32(rng_base + RNG_CTRL_OFFSET);
  69         val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  70
  71         if (enable)
  72                 val |= RNG_CTRL_RNG_RBGEN_ENABLE;
  73
  74         iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  75 }
  76
  77 static void iproc_rng200_restart(void __iomem *rng_base)
  78 {
  79         uint32_t val;
  80
  81         iproc_rng200_enable_set(rng_base, false);
  82
  83         /* Clear all interrupt status */
  84         iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
  85
  86         /* Reset RNG and RBG */
  87         val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  88         val |= RBG_SOFT_RESET;
  89         iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  90
  91         val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  92         val |= RNG_SOFT_RESET;
  93         iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  94
  95         val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  96         val &= ~RNG_SOFT_RESET;
  97         iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  98
  99         val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
 100         val &= ~RBG_SOFT_RESET;
 101         iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
 102
 103         iproc_rng200_enable_set(rng_base, true);
 104 }
 105
 106 static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
 107                              bool wait)
 108 {
 109         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 110         uint32_t num_remaining = max;
 111         uint32_t status;
 112
 113         #define MAX_RESETS_PER_READ     1
 114         uint32_t num_resets = 0;
 115
 116         #define MAX_IDLE_TIME   (1 * HZ)
 117         unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
 118
 119         while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
 120
 121                 /* Is RNG sane? If not, reset it. */
 122                 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
 123                 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
 124                         RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
 125
 126                         if (num_resets >= MAX_RESETS_PER_READ)
 127                                 return max - num_remaining;
 128
 129                         iproc_rng200_restart(priv->base);
 130                         num_resets++;
 131                 }
 132
 133                 /* Are there any random numbers available? */
 134                 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
 135                                 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
 136
 137                         if (num_remaining >= sizeof(uint32_t)) {
 138                                 /* Buffer has room to store entire word */
 139                                 *(uint32_t *)buf = ioread32(priv->base +
 140                                                         RNG_FIFO_DATA_OFFSET);
 141                                 buf += sizeof(uint32_t);
 142                                 num_remaining -= sizeof(uint32_t);
 143                         } else {
 144                                 /* Buffer can only store partial word */
 145                                 uint32_t rnd_number = ioread32(priv->base +
 146                                                         RNG_FIFO_DATA_OFFSET);
 147                                 memcpy(buf, &rnd_number, num_remaining);
 148                                 buf += num_remaining;
 149                                 num_remaining = 0;
 150                         }
 151
 152                         /* Reset the IDLE timeout */
 153                         idle_endtime = jiffies + MAX_IDLE_TIME;
 154                 } else {
 155                         if (!wait)
 156                                 /* Cannot wait, return immediately */
 157                                 return max - num_remaining;
 158
 159                         /* Can wait, give others chance to run */
 160                         usleep_range(min(num_remaining * 10, 500U), 500);
 161                 }
 162         }
 163
 164         return max - num_remaining;
 165 }
 166
 167 static int iproc_rng200_init(struct hwrng *rng)
 168 {
 169         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 170
 171         iproc_rng200_enable_set(priv->base, true);
 172
 173         return 0;
 174 }
 175
 176 static int bcm2711_rng200_read(struct hwrng *rng, void *buf, size_t max,
 177                                bool wait)
 178 {
 179         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 180         u32 max_words = max / sizeof(u32);
 181         u32 num_words, count, val;
 182
 183         /* ensure warm up period has elapsed */
 184         while (1) {
 185                 val = ioread32(priv->base + RNG_TOTAL_BIT_COUNT_OFFSET);
 186                 if (val > 16)
 187                         break;
 188                 cpu_relax();
 189         }
 190
 191         /* ensure fifo is not empty */
 192         while (1) {
 193                 num_words = ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
 194                             RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK;
 195                 if (num_words)
 196                         break;
 197                 if (!wait)
 198                         return 0;
 199                 cpu_relax();
 200         }
 201
 202         if (num_words > max_words)
 203                 num_words = max_words;
 204
 205         for (count = 0; count < num_words; count++) {
 206                 ((u32 *)buf)[count] = ioread32(priv->base +
 207                                                RNG_FIFO_DATA_OFFSET);
 208         }
 209
 210         return num_words * sizeof(u32);
 211 }
 212
 213 static int bcm2711_rng200_init(struct hwrng *rng)
 214 {
 215         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 216         uint32_t val;
 217
 218         if (ioread32(priv->base + RNG_CTRL_OFFSET) & RNG_CTRL_RNG_RBGEN_MASK)
 219                 return 0;
 220
 221         /* initial numbers generated are "less random" so will be discarded */
 222         val = 0x40000;
 223         iowrite32(val, priv->base + RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET);
 224         /* min fifo count to generate full interrupt */
 225         val = 2 << RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT;
 226         iowrite32(val, priv->base + RNG_FIFO_COUNT_OFFSET);
 227         /* enable the rng - 1Mhz sample rate */
 228         val = (0x3 << RNG_CTRL_RNG_DIV_CTRL_SHIFT) | RNG_CTRL_RNG_RBGEN_MASK;
 229         iowrite32(val, priv->base + RNG_CTRL_OFFSET);
 230
 231         return 0;
 232 }
 233
 234 static void iproc_rng200_cleanup(struct hwrng *rng)
 235 {
 236         struct iproc_rng200_dev *priv = to_rng_priv(rng);
 237
 238         iproc_rng200_enable_set(priv->base, false);
 239 }
 240
 241 static int iproc_rng200_probe(struct platform_device *pdev)
 242 {
 243         struct iproc_rng200_dev *priv;
 244         struct device *dev = &pdev->dev;
 245         int ret;
 246
 247         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 248         if (!priv)
 249                 return -ENOMEM;
 250
 251         /* Map peripheral */
 252         priv->base = devm_platform_ioremap_resource(pdev, 0);
 253         if (IS_ERR(priv->base)) {
 254                 dev_err(dev, "failed to remap rng regs\n");
 255                 return PTR_ERR(priv->base);
 256         }
 257
 258         priv->rng.name = pdev->name;
 259         priv->rng.cleanup = iproc_rng200_cleanup;
 260
 261         if (of_device_is_compatible(dev->of_node, "brcm,bcm2711-rng200")) {
 262                 priv->rng.init = bcm2711_rng200_init;
 263                 priv->rng.read = bcm2711_rng200_read;
 264         } else {
 265                 priv->rng.init = iproc_rng200_init;
 266                 priv->rng.read = iproc_rng200_read;
 267         }
 268
 269         /* Register driver */
 270         ret = devm_hwrng_register(dev, &priv->rng);
 271         if (ret) {
 272                 dev_err(dev, "hwrng registration failed\n");
 273                 return ret;
 274         }
 275
 276         dev_info(dev, "hwrng registered\n");
 277
 278         return 0;
 279 }
 280
 281 static const struct of_device_id iproc_rng200_of_match[] = {
 282         { .compatible = "brcm,bcm2711-rng200", },
 283         { .compatible = "brcm,bcm7211-rng200", },
 284         { .compatible = "brcm,bcm7278-rng200", },
 285         { .compatible = "brcm,iproc-rng200", },
 286         {},
 287 };
 288 MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
 289
 290 static struct platform_driver iproc_rng200_driver = {
 291         .driver = {
 292                 .name           = "iproc-rng200",
 293                 .of_match_table = iproc_rng200_of_match,
 294         },
 295         .probe          = iproc_rng200_probe,
 296 };
 297 module_platform_driver(iproc_rng200_driver);
 298
 299 MODULE_AUTHOR("Broadcom");
 300 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
 301 MODULE_LICENSE("GPL v2");