drivers/char/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 static int radeon_do_cleanup_cp( drm_device_t *dev );
  40
  41 /* CP microcode (from ATI) */
  42 static u32 R200_cp_microcode[][2] = {
  43         { 0x21007000, 0000000000 },
  44         { 0x20007000, 0000000000 },
  45         { 0x000000ab, 0x00000004 },
  46         { 0x000000af, 0x00000004 },
  47         { 0x66544a49, 0000000000 },
  48         { 0x49494174, 0000000000 },
  49         { 0x54517d83, 0000000000 },
  50         { 0x498d8b64, 0000000000 },
  51         { 0x49494949, 0000000000 },
  52         { 0x49da493c, 0000000000 },
  53         { 0x49989898, 0000000000 },
  54         { 0xd34949d5, 0000000000 },
  55         { 0x9dc90e11, 0000000000 },
  56         { 0xce9b9b9b, 0000000000 },
  57         { 0x000f0000, 0x00000016 },
  58         { 0x352e232c, 0000000000 },
  59         { 0x00000013, 0x00000004 },
  60         { 0x000f0000, 0x00000016 },
  61         { 0x352e272c, 0000000000 },
  62         { 0x000f0001, 0x00000016 },
  63         { 0x3239362f, 0000000000 },
  64         { 0x000077ef, 0x00000002 },
  65         { 0x00061000, 0x00000002 },
  66         { 0x00000020, 0x0000001a },
  67         { 0x00004000, 0x0000001e },
  68         { 0x00061000, 0x00000002 },
  69         { 0x00000020, 0x0000001a },
  70         { 0x00004000, 0x0000001e },
  71         { 0x00061000, 0x00000002 },
  72         { 0x00000020, 0x0000001a },
  73         { 0x00004000, 0x0000001e },
  74         { 0x00000016, 0x00000004 },
  75         { 0x0003802a, 0x00000002 },
  76         { 0x040067e0, 0x00000002 },
  77         { 0x00000016, 0x00000004 },
  78         { 0x000077e0, 0x00000002 },
  79         { 0x00065000, 0x00000002 },
  80         { 0x000037e1, 0x00000002 },
  81         { 0x040067e1, 0x00000006 },
  82         { 0x000077e0, 0x00000002 },
  83         { 0x000077e1, 0x00000002 },
  84         { 0x000077e1, 0x00000006 },
  85         { 0xffffffff, 0000000000 },
  86         { 0x10000000, 0000000000 },
  87         { 0x0003802a, 0x00000002 },
  88         { 0x040067e0, 0x00000006 },
  89         { 0x00007675, 0x00000002 },
  90         { 0x00007676, 0x00000002 },
  91         { 0x00007677, 0x00000002 },
  92         { 0x00007678, 0x00000006 },
  93         { 0x0003802b, 0x00000002 },
  94         { 0x04002676, 0x00000002 },
  95         { 0x00007677, 0x00000002 },
  96         { 0x00007678, 0x00000006 },
  97         { 0x0000002e, 0x00000018 },
  98         { 0x0000002e, 0x00000018 },
  99         { 0000000000, 0x00000006 },
 100         { 0x0000002f, 0x00000018 },
 101         { 0x0000002f, 0x00000018 },
 102         { 0000000000, 0x00000006 },
 103         { 0x01605000, 0x00000002 },
 104         { 0x00065000, 0x00000002 },
 105         { 0x00098000, 0x00000002 },
 106         { 0x00061000, 0x00000002 },
 107         { 0x64c0603d, 0x00000004 },
 108         { 0x00080000, 0x00000016 },
 109         { 0000000000, 0000000000 },
 110         { 0x0400251d, 0x00000002 },
 111         { 0x00007580, 0x00000002 },
 112         { 0x00067581, 0x00000002 },
 113         { 0x04002580, 0x00000002 },
 114         { 0x00067581, 0x00000002 },
 115         { 0x00000046, 0x00000004 },
 116         { 0x00005000, 0000000000 },
 117         { 0x00061000, 0x00000002 },
 118         { 0x0000750e, 0x00000002 },
 119         { 0x00019000, 0x00000002 },
 120         { 0x00011055, 0x00000014 },
 121         { 0x00000055, 0x00000012 },
 122         { 0x0400250f, 0x00000002 },
 123         { 0x0000504a, 0x00000004 },
 124         { 0x00007565, 0x00000002 },
 125         { 0x00007566, 0x00000002 },
 126         { 0x00000051, 0x00000004 },
 127         { 0x01e655b4, 0x00000002 },
 128         { 0x4401b0dc, 0x00000002 },
 129         { 0x01c110dc, 0x00000002 },
 130         { 0x2666705d, 0x00000018 },
 131         { 0x040c2565, 0x00000002 },
 132         { 0x0000005d, 0x00000018 },
 133         { 0x04002564, 0x00000002 },
 134         { 0x00007566, 0x00000002 },
 135         { 0x00000054, 0x00000004 },
 136         { 0x00401060, 0x00000008 },
 137         { 0x00101000, 0x00000002 },
 138         { 0x000d80ff, 0x00000002 },
 139         { 0x00800063, 0x00000008 },
 140         { 0x000f9000, 0x00000002 },
 141         { 0x000e00ff, 0x00000002 },
 142         { 0000000000, 0x00000006 },
 143         { 0x00000080, 0x00000018 },
 144         { 0x00000054, 0x00000004 },
 145         { 0x00007576, 0x00000002 },
 146         { 0x00065000, 0x00000002 },
 147         { 0x00009000, 0x00000002 },
 148         { 0x00041000, 0x00000002 },
 149         { 0x0c00350e, 0x00000002 },
 150         { 0x00049000, 0x00000002 },
 151         { 0x00051000, 0x00000002 },
 152         { 0x01e785f8, 0x00000002 },
 153         { 0x00200000, 0x00000002 },
 154         { 0x00600073, 0x0000000c },
 155         { 0x00007563, 0x00000002 },
 156         { 0x006075f0, 0x00000021 },
 157         { 0x20007068, 0x00000004 },
 158         { 0x00005068, 0x00000004 },
 159         { 0x00007576, 0x00000002 },
 160         { 0x00007577, 0x00000002 },
 161         { 0x0000750e, 0x00000002 },
 162         { 0x0000750f, 0x00000002 },
 163         { 0x00a05000, 0x00000002 },
 164         { 0x00600076, 0x0000000c },
 165         { 0x006075f0, 0x00000021 },
 166         { 0x000075f8, 0x00000002 },
 167         { 0x00000076, 0x00000004 },
 168         { 0x000a750e, 0x00000002 },
 169         { 0x0020750f, 0x00000002 },
 170         { 0x00600079, 0x00000004 },
 171         { 0x00007570, 0x00000002 },
 172         { 0x00007571, 0x00000002 },
 173         { 0x00007572, 0x00000006 },
 174         { 0x00005000, 0x00000002 },
 175         { 0x00a05000, 0x00000002 },
 176         { 0x00007568, 0x00000002 },
 177         { 0x00061000, 0x00000002 },
 178         { 0x00000084, 0x0000000c },
 179         { 0x00058000, 0x00000002 },
 180         { 0x0c607562, 0x00000002 },
 181         { 0x00000086, 0x00000004 },
 182         { 0x00600085, 0x00000004 },
 183         { 0x400070dd, 0000000000 },
 184         { 0x000380dd, 0x00000002 },
 185         { 0x00000093, 0x0000001c },
 186         { 0x00065095, 0x00000018 },
 187         { 0x040025bb, 0x00000002 },
 188         { 0x00061096, 0x00000018 },
 189         { 0x040075bc, 0000000000 },
 190         { 0x000075bb, 0x00000002 },
 191         { 0x000075bc, 0000000000 },
 192         { 0x00090000, 0x00000006 },
 193         { 0x00090000, 0x00000002 },
 194         { 0x000d8002, 0x00000006 },
 195         { 0x00005000, 0x00000002 },
 196         { 0x00007821, 0x00000002 },
 197         { 0x00007800, 0000000000 },
 198         { 0x00007821, 0x00000002 },
 199         { 0x00007800, 0000000000 },
 200         { 0x01665000, 0x00000002 },
 201         { 0x000a0000, 0x00000002 },
 202         { 0x000671cc, 0x00000002 },
 203         { 0x0286f1cd, 0x00000002 },
 204         { 0x000000a3, 0x00000010 },
 205         { 0x21007000, 0000000000 },
 206         { 0x000000aa, 0x0000001c },
 207         { 0x00065000, 0x00000002 },
 208         { 0x000a0000, 0x00000002 },
 209         { 0x00061000, 0x00000002 },
 210         { 0x000b0000, 0x00000002 },
 211         { 0x38067000, 0x00000002 },
 212         { 0x000a00a6, 0x00000004 },
 213         { 0x20007000, 0000000000 },
 214         { 0x01200000, 0x00000002 },
 215         { 0x20077000, 0x00000002 },
 216         { 0x01200000, 0x00000002 },
 217         { 0x20007000, 0000000000 },
 218         { 0x00061000, 0x00000002 },
 219         { 0x0120751b, 0x00000002 },
 220         { 0x8040750a, 0x00000002 },
 221         { 0x8040750b, 0x00000002 },
 222         { 0x00110000, 0x00000002 },
 223         { 0x000380dd, 0x00000002 },
 224         { 0x000000bd, 0x0000001c },
 225         { 0x00061096, 0x00000018 },
 226         { 0x844075bd, 0x00000002 },
 227         { 0x00061095, 0x00000018 },
 228         { 0x840075bb, 0x00000002 },
 229         { 0x00061096, 0x00000018 },
 230         { 0x844075bc, 0x00000002 },
 231         { 0x000000c0, 0x00000004 },
 232         { 0x804075bd, 0x00000002 },
 233         { 0x800075bb, 0x00000002 },
 234         { 0x804075bc, 0x00000002 },
 235         { 0x00108000, 0x00000002 },
 236         { 0x01400000, 0x00000002 },
 237         { 0x006000c4, 0x0000000c },
 238         { 0x20c07000, 0x00000020 },
 239         { 0x000000c6, 0x00000012 },
 240         { 0x00800000, 0x00000006 },
 241         { 0x0080751d, 0x00000006 },
 242         { 0x000025bb, 0x00000002 },
 243         { 0x000040c0, 0x00000004 },
 244         { 0x0000775c, 0x00000002 },
 245         { 0x00a05000, 0x00000002 },
 246         { 0x00661000, 0x00000002 },
 247         { 0x0460275d, 0x00000020 },
 248         { 0x00004000, 0000000000 },
 249         { 0x00007999, 0x00000002 },
 250         { 0x00a05000, 0x00000002 },
 251         { 0x00661000, 0x00000002 },
 252         { 0x0460299b, 0x00000020 },
 253         { 0x00004000, 0000000000 },
 254         { 0x01e00830, 0x00000002 },
 255         { 0x21007000, 0000000000 },
 256         { 0x00005000, 0x00000002 },
 257         { 0x00038042, 0x00000002 },
 258         { 0x040025e0, 0x00000002 },
 259         { 0x000075e1, 0000000000 },
 260         { 0x00000001, 0000000000 },
 261         { 0x000380d9, 0x00000002 },
 262         { 0x04007394, 0000000000 },
 263         { 0000000000, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299 };
 300
 301
 302 static u32 radeon_cp_microcode[][2] = {
 303         { 0x21007000, 0000000000 },
 304         { 0x20007000, 0000000000 },
 305         { 0x000000b4, 0x00000004 },
 306         { 0x000000b8, 0x00000004 },
 307         { 0x6f5b4d4c, 0000000000 },
 308         { 0x4c4c427f, 0000000000 },
 309         { 0x5b568a92, 0000000000 },
 310         { 0x4ca09c6d, 0000000000 },
 311         { 0xad4c4c4c, 0000000000 },
 312         { 0x4ce1af3d, 0000000000 },
 313         { 0xd8afafaf, 0000000000 },
 314         { 0xd64c4cdc, 0000000000 },
 315         { 0x4cd10d10, 0000000000 },
 316         { 0x000f0000, 0x00000016 },
 317         { 0x362f242d, 0000000000 },
 318         { 0x00000012, 0x00000004 },
 319         { 0x000f0000, 0x00000016 },
 320         { 0x362f282d, 0000000000 },
 321         { 0x000380e7, 0x00000002 },
 322         { 0x04002c97, 0x00000002 },
 323         { 0x000f0001, 0x00000016 },
 324         { 0x333a3730, 0000000000 },
 325         { 0x000077ef, 0x00000002 },
 326         { 0x00061000, 0x00000002 },
 327         { 0x00000021, 0x0000001a },
 328         { 0x00004000, 0x0000001e },
 329         { 0x00061000, 0x00000002 },
 330         { 0x00000021, 0x0000001a },
 331         { 0x00004000, 0x0000001e },
 332         { 0x00061000, 0x00000002 },
 333         { 0x00000021, 0x0000001a },
 334         { 0x00004000, 0x0000001e },
 335         { 0x00000017, 0x00000004 },
 336         { 0x0003802b, 0x00000002 },
 337         { 0x040067e0, 0x00000002 },
 338         { 0x00000017, 0x00000004 },
 339         { 0x000077e0, 0x00000002 },
 340         { 0x00065000, 0x00000002 },
 341         { 0x000037e1, 0x00000002 },
 342         { 0x040067e1, 0x00000006 },
 343         { 0x000077e0, 0x00000002 },
 344         { 0x000077e1, 0x00000002 },
 345         { 0x000077e1, 0x00000006 },
 346         { 0xffffffff, 0000000000 },
 347         { 0x10000000, 0000000000 },
 348         { 0x0003802b, 0x00000002 },
 349         { 0x040067e0, 0x00000006 },
 350         { 0x00007675, 0x00000002 },
 351         { 0x00007676, 0x00000002 },
 352         { 0x00007677, 0x00000002 },
 353         { 0x00007678, 0x00000006 },
 354         { 0x0003802c, 0x00000002 },
 355         { 0x04002676, 0x00000002 },
 356         { 0x00007677, 0x00000002 },
 357         { 0x00007678, 0x00000006 },
 358         { 0x0000002f, 0x00000018 },
 359         { 0x0000002f, 0x00000018 },
 360         { 0000000000, 0x00000006 },
 361         { 0x00000030, 0x00000018 },
 362         { 0x00000030, 0x00000018 },
 363         { 0000000000, 0x00000006 },
 364         { 0x01605000, 0x00000002 },
 365         { 0x00065000, 0x00000002 },
 366         { 0x00098000, 0x00000002 },
 367         { 0x00061000, 0x00000002 },
 368         { 0x64c0603e, 0x00000004 },
 369         { 0x000380e6, 0x00000002 },
 370         { 0x040025c5, 0x00000002 },
 371         { 0x00080000, 0x00000016 },
 372         { 0000000000, 0000000000 },
 373         { 0x0400251d, 0x00000002 },
 374         { 0x00007580, 0x00000002 },
 375         { 0x00067581, 0x00000002 },
 376         { 0x04002580, 0x00000002 },
 377         { 0x00067581, 0x00000002 },
 378         { 0x00000049, 0x00000004 },
 379         { 0x00005000, 0000000000 },
 380         { 0x000380e6, 0x00000002 },
 381         { 0x040025c5, 0x00000002 },
 382         { 0x00061000, 0x00000002 },
 383         { 0x0000750e, 0x00000002 },
 384         { 0x00019000, 0x00000002 },
 385         { 0x00011055, 0x00000014 },
 386         { 0x00000055, 0x00000012 },
 387         { 0x0400250f, 0x00000002 },
 388         { 0x0000504f, 0x00000004 },
 389         { 0x000380e6, 0x00000002 },
 390         { 0x040025c5, 0x00000002 },
 391         { 0x00007565, 0x00000002 },
 392         { 0x00007566, 0x00000002 },
 393         { 0x00000058, 0x00000004 },
 394         { 0x000380e6, 0x00000002 },
 395         { 0x040025c5, 0x00000002 },
 396         { 0x01e655b4, 0x00000002 },
 397         { 0x4401b0e4, 0x00000002 },
 398         { 0x01c110e4, 0x00000002 },
 399         { 0x26667066, 0x00000018 },
 400         { 0x040c2565, 0x00000002 },
 401         { 0x00000066, 0x00000018 },
 402         { 0x04002564, 0x00000002 },
 403         { 0x00007566, 0x00000002 },
 404         { 0x0000005d, 0x00000004 },
 405         { 0x00401069, 0x00000008 },
 406         { 0x00101000, 0x00000002 },
 407         { 0x000d80ff, 0x00000002 },
 408         { 0x0080006c, 0x00000008 },
 409         { 0x000f9000, 0x00000002 },
 410         { 0x000e00ff, 0x00000002 },
 411         { 0000000000, 0x00000006 },
 412         { 0x0000008f, 0x00000018 },
 413         { 0x0000005b, 0x00000004 },
 414         { 0x000380e6, 0x00000002 },
 415         { 0x040025c5, 0x00000002 },
 416         { 0x00007576, 0x00000002 },
 417         { 0x00065000, 0x00000002 },
 418         { 0x00009000, 0x00000002 },
 419         { 0x00041000, 0x00000002 },
 420         { 0x0c00350e, 0x00000002 },
 421         { 0x00049000, 0x00000002 },
 422         { 0x00051000, 0x00000002 },
 423         { 0x01e785f8, 0x00000002 },
 424         { 0x00200000, 0x00000002 },
 425         { 0x0060007e, 0x0000000c },
 426         { 0x00007563, 0x00000002 },
 427         { 0x006075f0, 0x00000021 },
 428         { 0x20007073, 0x00000004 },
 429         { 0x00005073, 0x00000004 },
 430         { 0x000380e6, 0x00000002 },
 431         { 0x040025c5, 0x00000002 },
 432         { 0x00007576, 0x00000002 },
 433         { 0x00007577, 0x00000002 },
 434         { 0x0000750e, 0x00000002 },
 435         { 0x0000750f, 0x00000002 },
 436         { 0x00a05000, 0x00000002 },
 437         { 0x00600083, 0x0000000c },
 438         { 0x006075f0, 0x00000021 },
 439         { 0x000075f8, 0x00000002 },
 440         { 0x00000083, 0x00000004 },
 441         { 0x000a750e, 0x00000002 },
 442         { 0x000380e6, 0x00000002 },
 443         { 0x040025c5, 0x00000002 },
 444         { 0x0020750f, 0x00000002 },
 445         { 0x00600086, 0x00000004 },
 446         { 0x00007570, 0x00000002 },
 447         { 0x00007571, 0x00000002 },
 448         { 0x00007572, 0x00000006 },
 449         { 0x000380e6, 0x00000002 },
 450         { 0x040025c5, 0x00000002 },
 451         { 0x00005000, 0x00000002 },
 452         { 0x00a05000, 0x00000002 },
 453         { 0x00007568, 0x00000002 },
 454         { 0x00061000, 0x00000002 },
 455         { 0x00000095, 0x0000000c },
 456         { 0x00058000, 0x00000002 },
 457         { 0x0c607562, 0x00000002 },
 458         { 0x00000097, 0x00000004 },
 459         { 0x000380e6, 0x00000002 },
 460         { 0x040025c5, 0x00000002 },
 461         { 0x00600096, 0x00000004 },
 462         { 0x400070e5, 0000000000 },
 463         { 0x000380e6, 0x00000002 },
 464         { 0x040025c5, 0x00000002 },
 465         { 0x000380e5, 0x00000002 },
 466         { 0x000000a8, 0x0000001c },
 467         { 0x000650aa, 0x00000018 },
 468         { 0x040025bb, 0x00000002 },
 469         { 0x000610ab, 0x00000018 },
 470         { 0x040075bc, 0000000000 },
 471         { 0x000075bb, 0x00000002 },
 472         { 0x000075bc, 0000000000 },
 473         { 0x00090000, 0x00000006 },
 474         { 0x00090000, 0x00000002 },
 475         { 0x000d8002, 0x00000006 },
 476         { 0x00007832, 0x00000002 },
 477         { 0x00005000, 0x00000002 },
 478         { 0x000380e7, 0x00000002 },
 479         { 0x04002c97, 0x00000002 },
 480         { 0x00007820, 0x00000002 },
 481         { 0x00007821, 0x00000002 },
 482         { 0x00007800, 0000000000 },
 483         { 0x01200000, 0x00000002 },
 484         { 0x20077000, 0x00000002 },
 485         { 0x01200000, 0x00000002 },
 486         { 0x20007000, 0x00000002 },
 487         { 0x00061000, 0x00000002 },
 488         { 0x0120751b, 0x00000002 },
 489         { 0x8040750a, 0x00000002 },
 490         { 0x8040750b, 0x00000002 },
 491         { 0x00110000, 0x00000002 },
 492         { 0x000380e5, 0x00000002 },
 493         { 0x000000c6, 0x0000001c },
 494         { 0x000610ab, 0x00000018 },
 495         { 0x844075bd, 0x00000002 },
 496         { 0x000610aa, 0x00000018 },
 497         { 0x840075bb, 0x00000002 },
 498         { 0x000610ab, 0x00000018 },
 499         { 0x844075bc, 0x00000002 },
 500         { 0x000000c9, 0x00000004 },
 501         { 0x804075bd, 0x00000002 },
 502         { 0x800075bb, 0x00000002 },
 503         { 0x804075bc, 0x00000002 },
 504         { 0x00108000, 0x00000002 },
 505         { 0x01400000, 0x00000002 },
 506         { 0x006000cd, 0x0000000c },
 507         { 0x20c07000, 0x00000020 },
 508         { 0x000000cf, 0x00000012 },
 509         { 0x00800000, 0x00000006 },
 510         { 0x0080751d, 0x00000006 },
 511         { 0000000000, 0000000000 },
 512         { 0x0000775c, 0x00000002 },
 513         { 0x00a05000, 0x00000002 },
 514         { 0x00661000, 0x00000002 },
 515         { 0x0460275d, 0x00000020 },
 516         { 0x00004000, 0000000000 },
 517         { 0x01e00830, 0x00000002 },
 518         { 0x21007000, 0000000000 },
 519         { 0x6464614d, 0000000000 },
 520         { 0x69687420, 0000000000 },
 521         { 0x00000073, 0000000000 },
 522         { 0000000000, 0000000000 },
 523         { 0x00005000, 0x00000002 },
 524         { 0x000380d0, 0x00000002 },
 525         { 0x040025e0, 0x00000002 },
 526         { 0x000075e1, 0000000000 },
 527         { 0x00000001, 0000000000 },
 528         { 0x000380e0, 0x00000002 },
 529         { 0x04002394, 0x00000002 },
 530         { 0x00005000, 0000000000 },
 531         { 0000000000, 0000000000 },
 532         { 0000000000, 0000000000 },
 533         { 0x00000008, 0000000000 },
 534         { 0x00000004, 0000000000 },
 535         { 0000000000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559 };
 560
 561 static u32 R300_cp_microcode[][2] = {
 562         { 0x4200e000, 0000000000 },
 563         { 0x4000e000, 0000000000 },
 564         { 0x000000af, 0x00000008 },
 565         { 0x000000b3, 0x00000008 },
 566         { 0x6c5a504f, 0000000000 },
 567         { 0x4f4f497a, 0000000000 },
 568         { 0x5a578288, 0000000000 },
 569         { 0x4f91906a, 0000000000 },
 570         { 0x4f4f4f4f, 0000000000 },
 571         { 0x4fe24f44, 0000000000 },
 572         { 0x4f9c9c9c, 0000000000 },
 573         { 0xdc4f4fde, 0000000000 },
 574         { 0xa1cd4f4f, 0000000000 },
 575         { 0xd29d9d9d, 0000000000 },
 576         { 0x4f0f9fd7, 0000000000 },
 577         { 0x000ca000, 0x00000004 },
 578         { 0x000d0012, 0x00000038 },
 579         { 0x0000e8b4, 0x00000004 },
 580         { 0x000d0014, 0x00000038 },
 581         { 0x0000e8b6, 0x00000004 },
 582         { 0x000d0016, 0x00000038 },
 583         { 0x0000e854, 0x00000004 },
 584         { 0x000d0018, 0x00000038 },
 585         { 0x0000e855, 0x00000004 },
 586         { 0x000d001a, 0x00000038 },
 587         { 0x0000e856, 0x00000004 },
 588         { 0x000d001c, 0x00000038 },
 589         { 0x0000e857, 0x00000004 },
 590         { 0x000d001e, 0x00000038 },
 591         { 0x0000e824, 0x00000004 },
 592         { 0x000d0020, 0x00000038 },
 593         { 0x0000e825, 0x00000004 },
 594         { 0x000d0022, 0x00000038 },
 595         { 0x0000e830, 0x00000004 },
 596         { 0x000d0024, 0x00000038 },
 597         { 0x0000f0c0, 0x00000004 },
 598         { 0x000d0026, 0x00000038 },
 599         { 0x0000f0c1, 0x00000004 },
 600         { 0x000d0028, 0x00000038 },
 601         { 0x0000f041, 0x00000004 },
 602         { 0x000d002a, 0x00000038 },
 603         { 0x0000f184, 0x00000004 },
 604         { 0x000d002c, 0x00000038 },
 605         { 0x0000f185, 0x00000004 },
 606         { 0x000d002e, 0x00000038 },
 607         { 0x0000f186, 0x00000004 },
 608         { 0x000d0030, 0x00000038 },
 609         { 0x0000f187, 0x00000004 },
 610         { 0x000d0032, 0x00000038 },
 611         { 0x0000f180, 0x00000004 },
 612         { 0x000d0034, 0x00000038 },
 613         { 0x0000f393, 0x00000004 },
 614         { 0x000d0036, 0x00000038 },
 615         { 0x0000f38a, 0x00000004 },
 616         { 0x000d0038, 0x00000038 },
 617         { 0x0000f38e, 0x00000004 },
 618         { 0x0000e821, 0x00000004 },
 619         { 0x0140a000, 0x00000004 },
 620         { 0x00000043, 0x00000018 },
 621         { 0x00cce800, 0x00000004 },
 622         { 0x001b0001, 0x00000004 },
 623         { 0x08004800, 0x00000004 },
 624         { 0x001b0001, 0x00000004 },
 625         { 0x08004800, 0x00000004 },
 626         { 0x001b0001, 0x00000004 },
 627         { 0x08004800, 0x00000004 },
 628         { 0x0000003a, 0x00000008 },
 629         { 0x0000a000, 0000000000 },
 630         { 0x02c0a000, 0x00000004 },
 631         { 0x000ca000, 0x00000004 },
 632         { 0x00130000, 0x00000004 },
 633         { 0x000c2000, 0x00000004 },
 634         { 0xc980c045, 0x00000008 },
 635         { 0x2000451d, 0x00000004 },
 636         { 0x0000e580, 0x00000004 },
 637         { 0x000ce581, 0x00000004 },
 638         { 0x08004580, 0x00000004 },
 639         { 0x000ce581, 0x00000004 },
 640         { 0x0000004c, 0x00000008 },
 641         { 0x0000a000, 0000000000 },
 642         { 0x000c2000, 0x00000004 },
 643         { 0x0000e50e, 0x00000004 },
 644         { 0x00032000, 0x00000004 },
 645         { 0x00022056, 0x00000028 },
 646         { 0x00000056, 0x00000024 },
 647         { 0x0800450f, 0x00000004 },
 648         { 0x0000a050, 0x00000008 },
 649         { 0x0000e565, 0x00000004 },
 650         { 0x0000e566, 0x00000004 },
 651         { 0x00000057, 0x00000008 },
 652         { 0x03cca5b4, 0x00000004 },
 653         { 0x05432000, 0x00000004 },
 654         { 0x00022000, 0x00000004 },
 655         { 0x4ccce063, 0x00000030 },
 656         { 0x08274565, 0x00000004 },
 657         { 0x00000063, 0x00000030 },
 658         { 0x08004564, 0x00000004 },
 659         { 0x0000e566, 0x00000004 },
 660         { 0x0000005a, 0x00000008 },
 661         { 0x00802066, 0x00000010 },
 662         { 0x00202000, 0x00000004 },
 663         { 0x001b00ff, 0x00000004 },
 664         { 0x01000069, 0x00000010 },
 665         { 0x001f2000, 0x00000004 },
 666         { 0x001c00ff, 0x00000004 },
 667         { 0000000000, 0x0000000c },
 668         { 0x00000085, 0x00000030 },
 669         { 0x0000005a, 0x00000008 },
 670         { 0x0000e576, 0x00000004 },
 671         { 0x000ca000, 0x00000004 },
 672         { 0x00012000, 0x00000004 },
 673         { 0x00082000, 0x00000004 },
 674         { 0x1800650e, 0x00000004 },
 675         { 0x00092000, 0x00000004 },
 676         { 0x000a2000, 0x00000004 },
 677         { 0x000f0000, 0x00000004 },
 678         { 0x00400000, 0x00000004 },
 679         { 0x00000079, 0x00000018 },
 680         { 0x0000e563, 0x00000004 },
 681         { 0x00c0e5f9, 0x000000c2 },
 682         { 0x0000006e, 0x00000008 },
 683         { 0x0000a06e, 0x00000008 },
 684         { 0x0000e576, 0x00000004 },
 685         { 0x0000e577, 0x00000004 },
 686         { 0x0000e50e, 0x00000004 },
 687         { 0x0000e50f, 0x00000004 },
 688         { 0x0140a000, 0x00000004 },
 689         { 0x0000007c, 0x00000018 },
 690         { 0x00c0e5f9, 0x000000c2 },
 691         { 0x0000007c, 0x00000008 },
 692         { 0x0014e50e, 0x00000004 },
 693         { 0x0040e50f, 0x00000004 },
 694         { 0x00c0007f, 0x00000008 },
 695         { 0x0000e570, 0x00000004 },
 696         { 0x0000e571, 0x00000004 },
 697         { 0x0000e572, 0x0000000c },
 698         { 0x0000a000, 0x00000004 },
 699         { 0x0140a000, 0x00000004 },
 700         { 0x0000e568, 0x00000004 },
 701         { 0x000c2000, 0x00000004 },
 702         { 0x00000089, 0x00000018 },
 703         { 0x000b0000, 0x00000004 },
 704         { 0x18c0e562, 0x00000004 },
 705         { 0x0000008b, 0x00000008 },
 706         { 0x00c0008a, 0x00000008 },
 707         { 0x000700e4, 0x00000004 },
 708         { 0x00000097, 0x00000038 },
 709         { 0x000ca099, 0x00000030 },
 710         { 0x080045bb, 0x00000004 },
 711         { 0x000c209a, 0x00000030 },
 712         { 0x0800e5bc, 0000000000 },
 713         { 0x0000e5bb, 0x00000004 },
 714         { 0x0000e5bc, 0000000000 },
 715         { 0x00120000, 0x0000000c },
 716         { 0x00120000, 0x00000004 },
 717         { 0x001b0002, 0x0000000c },
 718         { 0x0000a000, 0x00000004 },
 719         { 0x0000e821, 0x00000004 },
 720         { 0x0000e800, 0000000000 },
 721         { 0x0000e821, 0x00000004 },
 722         { 0x0000e82e, 0000000000 },
 723         { 0x02cca000, 0x00000004 },
 724         { 0x00140000, 0x00000004 },
 725         { 0x000ce1cc, 0x00000004 },
 726         { 0x050de1cd, 0x00000004 },
 727         { 0x000000a7, 0x00000020 },
 728         { 0x4200e000, 0000000000 },
 729         { 0x000000ae, 0x00000038 },
 730         { 0x000ca000, 0x00000004 },
 731         { 0x00140000, 0x00000004 },
 732         { 0x000c2000, 0x00000004 },
 733         { 0x00160000, 0x00000004 },
 734         { 0x700ce000, 0x00000004 },
 735         { 0x001400aa, 0x00000008 },
 736         { 0x4000e000, 0000000000 },
 737         { 0x02400000, 0x00000004 },
 738         { 0x400ee000, 0x00000004 },
 739         { 0x02400000, 0x00000004 },
 740         { 0x4000e000, 0000000000 },
 741         { 0x000c2000, 0x00000004 },
 742         { 0x0240e51b, 0x00000004 },
 743         { 0x0080e50a, 0x00000005 },
 744         { 0x0080e50b, 0x00000005 },
 745         { 0x00220000, 0x00000004 },
 746         { 0x000700e4, 0x00000004 },
 747         { 0x000000c1, 0x00000038 },
 748         { 0x000c209a, 0x00000030 },
 749         { 0x0880e5bd, 0x00000005 },
 750         { 0x000c2099, 0x00000030 },
 751         { 0x0800e5bb, 0x00000005 },
 752         { 0x000c209a, 0x00000030 },
 753         { 0x0880e5bc, 0x00000005 },
 754         { 0x000000c4, 0x00000008 },
 755         { 0x0080e5bd, 0x00000005 },
 756         { 0x0000e5bb, 0x00000005 },
 757         { 0x0080e5bc, 0x00000005 },
 758         { 0x00210000, 0x00000004 },
 759         { 0x02800000, 0x00000004 },
 760         { 0x00c000c8, 0x00000018 },
 761         { 0x4180e000, 0x00000040 },
 762         { 0x000000ca, 0x00000024 },
 763         { 0x01000000, 0x0000000c },
 764         { 0x0100e51d, 0x0000000c },
 765         { 0x000045bb, 0x00000004 },
 766         { 0x000080c4, 0x00000008 },
 767         { 0x0000f3ce, 0x00000004 },
 768         { 0x0140a000, 0x00000004 },
 769         { 0x00cc2000, 0x00000004 },
 770         { 0x08c053cf, 0x00000040 },
 771         { 0x00008000, 0000000000 },
 772         { 0x0000f3d2, 0x00000004 },
 773         { 0x0140a000, 0x00000004 },
 774         { 0x00cc2000, 0x00000004 },
 775         { 0x08c053d3, 0x00000040 },
 776         { 0x00008000, 0000000000 },
 777         { 0x0000f39d, 0x00000004 },
 778         { 0x0140a000, 0x00000004 },
 779         { 0x00cc2000, 0x00000004 },
 780         { 0x08c0539e, 0x00000040 },
 781         { 0x00008000, 0000000000 },
 782         { 0x03c00830, 0x00000004 },
 783         { 0x4200e000, 0000000000 },
 784         { 0x0000a000, 0x00000004 },
 785         { 0x200045e0, 0x00000004 },
 786         { 0x0000e5e1, 0000000000 },
 787         { 0x00000001, 0000000000 },
 788         { 0x000700e1, 0x00000004 },
 789         { 0x0800e394, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817         { 0000000000, 0000000000 },
 818 };
 819
 820 static int RADEON_READ_PLL(drm_device_t *dev, int addr)
 821 {
 822         drm_radeon_private_t *dev_priv = dev->dev_private;
 823
 824         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 825         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 826 }
 827
 828 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 829 {
 830         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 831         return RADEON_READ(RADEON_PCIE_DATA);
 832 }
 833
 834 #if RADEON_FIFO_DEBUG
 835 static void radeon_status( drm_radeon_private_t *dev_priv )
 836 {
 837         printk( "%s:\n", __FUNCTION__ );
 838         printk( "RBBM_STATUS = 0x%08x\n",
 839                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 840         printk( "CP_RB_RTPR = 0x%08x\n",
 841                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 842         printk( "CP_RB_WTPR = 0x%08x\n",
 843                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 844         printk( "AIC_CNTL = 0x%08x\n",
 845                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 846         printk( "AIC_STAT = 0x%08x\n",
 847                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 848         printk( "AIC_PT_BASE = 0x%08x\n",
 849                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 850         printk( "TLB_ADDR = 0x%08x\n",
 851                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 852         printk( "TLB_DATA = 0x%08x\n",
 853                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 854 }
 855 #endif
 856
 857
 858 /* ================================================================
 859  * Engine, FIFO control
 860  */
 861
 862 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 863 {
 864         u32 tmp;
 865         int i;
 866
 867         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 868
 869         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 870         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 871         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 872
 873         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 874                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 875                        & RADEON_RB2D_DC_BUSY) ) {
 876                         return 0;
 877                 }
 878                 DRM_UDELAY( 1 );
 879         }
 880
 881 #if RADEON_FIFO_DEBUG
 882         DRM_ERROR( "failed!\n" );
 883         radeon_status( dev_priv );
 884 #endif
 885         return DRM_ERR(EBUSY);
 886 }
 887
 888 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 889                                     int entries )
 890 {
 891         int i;
 892
 893         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 894
 895         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 896                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 897                               & RADEON_RBBM_FIFOCNT_MASK );
 898                 if ( slots >= entries ) return 0;
 899                 DRM_UDELAY( 1 );
 900         }
 901
 902 #if RADEON_FIFO_DEBUG
 903         DRM_ERROR( "failed!\n" );
 904         radeon_status( dev_priv );
 905 #endif
 906         return DRM_ERR(EBUSY);
 907 }
 908
 909 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 910 {
 911         int i, ret;
 912
 913         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 914
 915         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 916         if ( ret ) return ret;
 917
 918         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 919                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 920                        & RADEON_RBBM_ACTIVE) ) {
 921                         radeon_do_pixcache_flush( dev_priv );
 922                         return 0;
 923                 }
 924                 DRM_UDELAY( 1 );
 925         }
 926
 927 #if RADEON_FIFO_DEBUG
 928         DRM_ERROR( "failed!\n" );
 929         radeon_status( dev_priv );
 930 #endif
 931         return DRM_ERR(EBUSY);
 932 }
 933
 934
 935 /* ================================================================
 936  * CP control, initialization
 937  */
 938
 939 /* Load the microcode for the CP */
 940 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 941 {
 942         int i;
 943         DRM_DEBUG( "\n" );
 944
 945         radeon_do_wait_for_idle( dev_priv );
 946
 947         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 948
 949         if (dev_priv->microcode_version==UCODE_R200) {
 950                 DRM_INFO("Loading R200 Microcode\n");
 951                 for ( i = 0 ; i < 256 ; i++ )
 952                 {
 953                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 954                                       R200_cp_microcode[i][1] );
 955                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 956                                       R200_cp_microcode[i][0] );
 957                 }
 958         } else if (dev_priv->microcode_version==UCODE_R300) {
 959                 DRM_INFO("Loading R300 Microcode\n");
 960                 for ( i = 0 ; i < 256 ; i++ )
 961                 {
 962                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 963                                       R300_cp_microcode[i][1] );
 964                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 965                                       R300_cp_microcode[i][0] );
 966                 }
 967         } else {
 968                 for ( i = 0 ; i < 256 ; i++ ) {
 969                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 970                                       radeon_cp_microcode[i][1] );
 971                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 972                                       radeon_cp_microcode[i][0] );
 973                 }
 974         }
 975 }
 976
 977 /* Flush any pending commands to the CP.  This should only be used just
 978  * prior to a wait for idle, as it informs the engine that the command
 979  * stream is ending.
 980  */
 981 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 982 {
 983         DRM_DEBUG( "\n" );
 984 #if 0
 985         u32 tmp;
 986
 987         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 988         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 989 #endif
 990 }
 991
 992 /* Wait for the CP to go idle.
 993  */
 994 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 995 {
 996         RING_LOCALS;
 997         DRM_DEBUG( "\n" );
 998
 999         BEGIN_RING( 6 );
1000
1001         RADEON_PURGE_CACHE();
1002         RADEON_PURGE_ZCACHE();
1003         RADEON_WAIT_UNTIL_IDLE();
1004
1005         ADVANCE_RING();
1006         COMMIT_RING();
1007
1008         return radeon_do_wait_for_idle( dev_priv );
1009 }
1010
1011 /* Start the Command Processor.
1012  */
1013 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1014 {
1015         RING_LOCALS;
1016         DRM_DEBUG( "\n" );
1017
1018         radeon_do_wait_for_idle( dev_priv );
1019
1020         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
1021
1022         dev_priv->cp_running = 1;
1023
1024         BEGIN_RING( 6 );
1025
1026         RADEON_PURGE_CACHE();
1027         RADEON_PURGE_ZCACHE();
1028         RADEON_WAIT_UNTIL_IDLE();
1029
1030         ADVANCE_RING();
1031         COMMIT_RING();
1032 }
1033
1034 /* Reset the Command Processor.  This will not flush any pending
1035  * commands, so you must wait for the CP command stream to complete
1036  * before calling this routine.
1037  */
1038 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1039 {
1040         u32 cur_read_ptr;
1041         DRM_DEBUG( "\n" );
1042
1043         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1044         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1045         SET_RING_HEAD( dev_priv, cur_read_ptr );
1046         dev_priv->ring.tail = cur_read_ptr;
1047 }
1048
1049 /* Stop the Command Processor.  This will not flush any pending
1050  * commands, so you must flush the command stream and wait for the CP
1051  * to go idle before calling this routine.
1052  */
1053 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
1054 {
1055         DRM_DEBUG( "\n" );
1056
1057         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
1058
1059         dev_priv->cp_running = 0;
1060 }
1061
1062 /* Reset the engine.  This will stop the CP if it is running.
1063  */
1064 static int radeon_do_engine_reset( drm_device_t *dev )
1065 {
1066         drm_radeon_private_t *dev_priv = dev->dev_private;
1067         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1068         DRM_DEBUG( "\n" );
1069
1070         radeon_do_pixcache_flush( dev_priv );
1071
1072         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1073         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1074
1075         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1076                                               RADEON_FORCEON_MCLKA |
1077                                               RADEON_FORCEON_MCLKB |
1078                                               RADEON_FORCEON_YCLKA |
1079                                               RADEON_FORCEON_YCLKB |
1080                                               RADEON_FORCEON_MC |
1081                                               RADEON_FORCEON_AIC ) );
1082
1083         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1084
1085         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
1086                                                 RADEON_SOFT_RESET_CP |
1087                                                 RADEON_SOFT_RESET_HI |
1088                                                 RADEON_SOFT_RESET_SE |
1089                                                 RADEON_SOFT_RESET_RE |
1090                                                 RADEON_SOFT_RESET_PP |
1091                                                 RADEON_SOFT_RESET_E2 |
1092                                                 RADEON_SOFT_RESET_RB ) );
1093         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1094         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
1095                                                 ~( RADEON_SOFT_RESET_CP |
1096                                                    RADEON_SOFT_RESET_HI |
1097                                                    RADEON_SOFT_RESET_SE |
1098                                                    RADEON_SOFT_RESET_RE |
1099                                                    RADEON_SOFT_RESET_PP |
1100                                                    RADEON_SOFT_RESET_E2 |
1101                                                    RADEON_SOFT_RESET_RB ) ) );
1102         RADEON_READ( RADEON_RBBM_SOFT_RESET );
1103
1104
1105         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1106         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1107         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
1108
1109         /* Reset the CP ring */
1110         radeon_do_cp_reset( dev_priv );
1111
1112         /* The CP is no longer running after an engine reset */
1113         dev_priv->cp_running = 0;
1114
1115         /* Reset any pending vertex, indirect buffers */
1116         radeon_freelist_reset( dev );
1117
1118         return 0;
1119 }
1120
1121 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1122                                         drm_radeon_private_t *dev_priv )
1123 {
1124         u32 ring_start, cur_read_ptr;
1125         u32 tmp;
1126
1127         /* Initialize the memory controller */
1128         RADEON_WRITE( RADEON_MC_FB_LOCATION,
1129                       ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
1130                     | ( dev_priv->fb_location >> 16 ) );
1131
1132 #if __OS_HAS_AGP
1133         if ( !dev_priv->is_pci ) {
1134                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
1135                               (((dev_priv->gart_vm_start - 1 +
1136                                  dev_priv->gart_size) & 0xffff0000) |
1137                                (dev_priv->gart_vm_start >> 16)) );
1138
1139                 ring_start = (dev_priv->cp_ring->offset
1140                               - dev->agp->base
1141                               + dev_priv->gart_vm_start);
1142        } else
1143 #endif
1144                 ring_start = (dev_priv->cp_ring->offset
1145                               - dev->sg->handle
1146                               + dev_priv->gart_vm_start);
1147
1148         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
1149
1150         /* Set the write pointer delay */
1151         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
1152
1153         /* Initialize the ring buffer's read and write pointers */
1154         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1155         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1156         SET_RING_HEAD( dev_priv, cur_read_ptr );
1157         dev_priv->ring.tail = cur_read_ptr;
1158
1159 #if __OS_HAS_AGP
1160         if ( !dev_priv->is_pci ) {
1161                 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1162                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1163                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1164                               dev_priv->ring_rptr->offset
1165                               - dev->agp->base
1166                               + dev_priv->gart_vm_start);
1167         } else
1168 #endif
1169         {
1170                 drm_sg_mem_t *entry = dev->sg;
1171                 unsigned long tmp_ofs, page_ofs;
1172
1173                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1174                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1175
1176                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1177                              entry->busaddr[page_ofs]);
1178                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
1179                            (unsigned long) entry->busaddr[page_ofs],
1180                            entry->handle + tmp_ofs );
1181         }
1182
1183         /* Initialize the scratch register pointer.  This will cause
1184          * the scratch register values to be written out to memory
1185          * whenever they are updated.
1186          *
1187          * We simply put this behind the ring read pointer, this works
1188          * with PCI GART as well as (whatever kind of) AGP GART
1189          */
1190         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
1191                                          + RADEON_SCRATCH_REG_OFFSET );
1192
1193         dev_priv->scratch = ((__volatile__ u32 *)
1194                              dev_priv->ring_rptr->handle +
1195                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1196
1197         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
1198
1199         /* Writeback doesn't seem to work everywhere, test it first */
1200         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
1201         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
1202
1203         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
1204                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
1205                         break;
1206                 DRM_UDELAY( 1 );
1207         }
1208
1209         if ( tmp < dev_priv->usec_timeout ) {
1210                 dev_priv->writeback_works = 1;
1211                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
1212         } else {
1213                 dev_priv->writeback_works = 0;
1214                 DRM_DEBUG( "writeback test failed\n" );
1215         }
1216
1217         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1218         RADEON_WRITE( RADEON_LAST_FRAME_REG,
1219                       dev_priv->sarea_priv->last_frame );
1220
1221         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1222         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
1223                       dev_priv->sarea_priv->last_dispatch );
1224
1225         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1226         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
1227                       dev_priv->sarea_priv->last_clear );
1228
1229         /* Set ring buffer size */
1230 #ifdef __BIG_ENDIAN
1231         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
1232 #else
1233         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
1234 #endif
1235
1236         radeon_do_wait_for_idle( dev_priv );
1237
1238         /* Turn on bus mastering */
1239         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
1240         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
1241
1242         /* Sync everything up */
1243         RADEON_WRITE( RADEON_ISYNC_CNTL,
1244                       (RADEON_ISYNC_ANY2D_IDLE3D |
1245                        RADEON_ISYNC_ANY3D_IDLE2D |
1246                        RADEON_ISYNC_WAIT_IDLEGUI |
1247                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
1248 }
1249
1250 /* Enable or disable PCI-E GART on the chip */
1251 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1252 {
1253         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1254         if (on) {
1255
1256                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1257                           dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr,
1258                           dev_priv->gart_size);
1259                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start);
1260                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr);
1261                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start);
1262                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start
1263                                   + dev_priv->gart_size - 1);
1264
1265                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1266
1267                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN);
1268         } else {
1269                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
1270         }
1271 }
1272
1273 /* Enable or disable PCI GART on the chip */
1274 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1275 {
1276         u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
1277
1278         if (dev_priv->flags & CHIP_IS_PCIE)
1279         {
1280                 radeon_set_pciegart(dev_priv, on);
1281                 return;
1282         }
1283
1284         if ( on ) {
1285                 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
1286
1287                 /* set PCI GART page-table base address
1288                  */
1289                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1290
1291                 /* set address range for PCI address translate
1292                  */
1293                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
1294                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1295                                                   + dev_priv->gart_size - 1);
1296
1297                 /* Turn off AGP aperture -- is this required for PCI GART?
1298                  */
1299                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1300                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1301         } else {
1302                 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1303         }
1304 }
1305
1306 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1307 {
1308         drm_radeon_private_t *dev_priv = dev->dev_private;;
1309         DRM_DEBUG( "\n" );
1310
1311         dev_priv->is_pci = init->is_pci;
1312
1313         if ( dev_priv->is_pci && !dev->sg ) {
1314                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1315                 dev->dev_private = (void *)dev_priv;
1316                 radeon_do_cleanup_cp(dev);
1317                 return DRM_ERR(EINVAL);
1318         }
1319
1320         dev_priv->usec_timeout = init->usec_timeout;
1321         if ( dev_priv->usec_timeout < 1 ||
1322              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1323                 DRM_DEBUG( "TIMEOUT problem!\n" );
1324                 dev->dev_private = (void *)dev_priv;
1325                 radeon_do_cleanup_cp(dev);
1326                 return DRM_ERR(EINVAL);
1327         }
1328
1329         switch(init->func) {
1330         case RADEON_INIT_R200_CP:
1331                 dev_priv->microcode_version=UCODE_R200;
1332                 break;
1333         case RADEON_INIT_R300_CP:
1334                 dev_priv->microcode_version=UCODE_R300;
1335                 break;
1336         default:
1337                 dev_priv->microcode_version=UCODE_R100;
1338         }
1339
1340         dev_priv->do_boxes = 0;
1341         dev_priv->cp_mode = init->cp_mode;
1342
1343         /* We don't support anything other than bus-mastering ring mode,
1344          * but the ring can be in either AGP or PCI space for the ring
1345          * read pointer.
1346          */
1347         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1348              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1349                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1350                 dev->dev_private = (void *)dev_priv;
1351                 radeon_do_cleanup_cp(dev);
1352                 return DRM_ERR(EINVAL);
1353         }
1354
1355         switch ( init->fb_bpp ) {
1356         case 16:
1357                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1358                 break;
1359         case 32:
1360         default:
1361                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1362                 break;
1363         }
1364         dev_priv->front_offset  = init->front_offset;
1365         dev_priv->front_pitch   = init->front_pitch;
1366         dev_priv->back_offset   = init->back_offset;
1367         dev_priv->back_pitch    = init->back_pitch;
1368
1369         switch ( init->depth_bpp ) {
1370         case 16:
1371                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1372                 break;
1373         case 32:
1374         default:
1375                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1376                 break;
1377         }
1378         dev_priv->depth_offset  = init->depth_offset;
1379         dev_priv->depth_pitch   = init->depth_pitch;
1380
1381         /* Hardware state for depth clears.  Remove this if/when we no
1382          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1383          * all values to prevent unwanted 3D state from slipping through
1384          * and screwing with the clear operation.
1385          */
1386         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1387                                            (dev_priv->color_fmt << 10) |
1388                                            (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1389
1390         dev_priv->depth_clear.rb3d_zstencilcntl =
1391                 (dev_priv->depth_fmt |
1392                  RADEON_Z_TEST_ALWAYS |
1393                  RADEON_STENCIL_TEST_ALWAYS |
1394                  RADEON_STENCIL_S_FAIL_REPLACE |
1395                  RADEON_STENCIL_ZPASS_REPLACE |
1396                  RADEON_STENCIL_ZFAIL_REPLACE |
1397                  RADEON_Z_WRITE_ENABLE);
1398
1399         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1400                                          RADEON_BFACE_SOLID |
1401                                          RADEON_FFACE_SOLID |
1402                                          RADEON_FLAT_SHADE_VTX_LAST |
1403                                          RADEON_DIFFUSE_SHADE_FLAT |
1404                                          RADEON_ALPHA_SHADE_FLAT |
1405                                          RADEON_SPECULAR_SHADE_FLAT |
1406                                          RADEON_FOG_SHADE_FLAT |
1407                                          RADEON_VTX_PIX_CENTER_OGL |
1408                                          RADEON_ROUND_MODE_TRUNC |
1409                                          RADEON_ROUND_PREC_8TH_PIX);
1410
1411         DRM_GETSAREA();
1412
1413         dev_priv->fb_offset = init->fb_offset;
1414         dev_priv->mmio_offset = init->mmio_offset;
1415         dev_priv->ring_offset = init->ring_offset;
1416         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1417         dev_priv->buffers_offset = init->buffers_offset;
1418         dev_priv->gart_textures_offset = init->gart_textures_offset;
1419
1420         if(!dev_priv->sarea) {
1421                 DRM_ERROR("could not find sarea!\n");
1422                 dev->dev_private = (void *)dev_priv;
1423                 radeon_do_cleanup_cp(dev);
1424                 return DRM_ERR(EINVAL);
1425         }
1426
1427         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1428         if(!dev_priv->mmio) {
1429                 DRM_ERROR("could not find mmio region!\n");
1430                 dev->dev_private = (void *)dev_priv;
1431                 radeon_do_cleanup_cp(dev);
1432                 return DRM_ERR(EINVAL);
1433         }
1434         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1435         if(!dev_priv->cp_ring) {
1436                 DRM_ERROR("could not find cp ring region!\n");
1437                 dev->dev_private = (void *)dev_priv;
1438                 radeon_do_cleanup_cp(dev);
1439                 return DRM_ERR(EINVAL);
1440         }
1441         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1442         if(!dev_priv->ring_rptr) {
1443                 DRM_ERROR("could not find ring read pointer!\n");
1444                 dev->dev_private = (void *)dev_priv;
1445                 radeon_do_cleanup_cp(dev);
1446                 return DRM_ERR(EINVAL);
1447         }
1448         dev->agp_buffer_token = init->buffers_offset;
1449         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1450         if(!dev->agp_buffer_map) {
1451                 DRM_ERROR("could not find dma buffer region!\n");
1452                 dev->dev_private = (void *)dev_priv;
1453                 radeon_do_cleanup_cp(dev);
1454                 return DRM_ERR(EINVAL);
1455         }
1456
1457         if ( init->gart_textures_offset ) {
1458                 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1459                 if ( !dev_priv->gart_textures ) {
1460                         DRM_ERROR("could not find GART texture region!\n");
1461                         dev->dev_private = (void *)dev_priv;
1462                         radeon_do_cleanup_cp(dev);
1463                         return DRM_ERR(EINVAL);
1464                 }
1465         }
1466
1467         dev_priv->sarea_priv =
1468                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1469                                        init->sarea_priv_offset);
1470
1471 #if __OS_HAS_AGP
1472         if ( !dev_priv->is_pci ) {
1473                 drm_core_ioremap( dev_priv->cp_ring, dev );
1474                 drm_core_ioremap( dev_priv->ring_rptr, dev );
1475                 drm_core_ioremap( dev->agp_buffer_map, dev );
1476                 if(!dev_priv->cp_ring->handle ||
1477                    !dev_priv->ring_rptr->handle ||
1478                    !dev->agp_buffer_map->handle) {
1479                         DRM_ERROR("could not find ioremap agp regions!\n");
1480                         dev->dev_private = (void *)dev_priv;
1481                         radeon_do_cleanup_cp(dev);
1482                         return DRM_ERR(EINVAL);
1483                 }
1484         } else
1485 #endif
1486         {
1487                 dev_priv->cp_ring->handle =
1488                         (void *)dev_priv->cp_ring->offset;
1489                 dev_priv->ring_rptr->handle =
1490                         (void *)dev_priv->ring_rptr->offset;
1491                 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1492
1493                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1494                            dev_priv->cp_ring->handle );
1495                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1496                            dev_priv->ring_rptr->handle );
1497                 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1498                            dev->agp_buffer_map->handle );
1499         }
1500
1501         dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1502                                 & 0xffff ) << 16;
1503
1504         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1505                                         ( ( dev_priv->front_offset
1506                                           + dev_priv->fb_location ) >> 10 ) );
1507
1508         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1509                                        ( ( dev_priv->back_offset
1510                                          + dev_priv->fb_location ) >> 10 ) );
1511
1512         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1513                                         ( ( dev_priv->depth_offset
1514                                           + dev_priv->fb_location ) >> 10 ) );
1515
1516
1517         dev_priv->gart_size = init->gart_size;
1518         dev_priv->gart_vm_start = dev_priv->fb_location
1519                                 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1520
1521 #if __OS_HAS_AGP
1522         if ( !dev_priv->is_pci )
1523                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1524                                                 - dev->agp->base
1525                                                 + dev_priv->gart_vm_start);
1526         else
1527 #endif
1528                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1529                                                 - dev->sg->handle
1530                                                 + dev_priv->gart_vm_start);
1531
1532         DRM_DEBUG( "dev_priv->gart_size %d\n",
1533                    dev_priv->gart_size );
1534         DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1535                    dev_priv->gart_vm_start );
1536         DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1537                    dev_priv->gart_buffers_offset );
1538
1539         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1540         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1541                               + init->ring_size / sizeof(u32));
1542         dev_priv->ring.size = init->ring_size;
1543         dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
1544
1545         dev_priv->ring.tail_mask =
1546                 (dev_priv->ring.size / sizeof(u32)) - 1;
1547
1548         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1549
1550 #if __OS_HAS_AGP
1551         if ( !dev_priv->is_pci ) {
1552                 /* Turn off PCI GART */
1553                 radeon_set_pcigart( dev_priv, 0 );
1554         } else
1555 #endif
1556         {
1557                 /* if we have an offset set from userspace */
1558                 if (dev_priv->pcigart_offset) {
1559                         dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location;
1560                         dev_priv->gart_info.addr = (unsigned long)drm_ioremap(dev_priv->gart_info.bus_addr, RADEON_PCIGART_TABLE_SIZE, dev);
1561
1562                         dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE);
1563                         dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB;
1564
1565                         DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset);
1566                 }
1567                 else {
1568                         dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
1569                         dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr= 0;
1570                         if (dev_priv->flags & CHIP_IS_PCIE)
1571                         {
1572                                 DRM_ERROR("Cannot use PCI Express without GART in FB memory\n");
1573                                 radeon_do_cleanup_cp(dev);
1574                                 return DRM_ERR(EINVAL);
1575                         }
1576                 }
1577
1578                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1579                         DRM_ERROR( "failed to init PCI GART!\n" );
1580                         dev->dev_private = (void *)dev_priv;
1581                         radeon_do_cleanup_cp(dev);
1582                         return DRM_ERR(ENOMEM);
1583                 }
1584
1585                 /* Turn on PCI GART */
1586                 radeon_set_pcigart( dev_priv, 1 );
1587         }
1588
1589         radeon_cp_load_microcode( dev_priv );
1590         radeon_cp_init_ring_buffer( dev, dev_priv );
1591
1592         dev_priv->last_buf = 0;
1593
1594         dev->dev_private = (void *)dev_priv;
1595
1596         radeon_do_engine_reset( dev );
1597
1598         return 0;
1599 }
1600
1601 static int radeon_do_cleanup_cp( drm_device_t *dev )
1602 {
1603         drm_radeon_private_t *dev_priv = dev->dev_private;
1604         DRM_DEBUG( "\n" );
1605
1606         /* Make sure interrupts are disabled here because the uninstall ioctl
1607          * may not have been called from userspace and after dev_private
1608          * is freed, it's too late.
1609          */
1610         if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1611
1612 #if __OS_HAS_AGP
1613         if ( !dev_priv->is_pci ) {
1614                 if ( dev_priv->cp_ring != NULL )
1615                         drm_core_ioremapfree( dev_priv->cp_ring, dev );
1616                 if ( dev_priv->ring_rptr != NULL )
1617                         drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1618                 if ( dev->agp_buffer_map != NULL )
1619                 {
1620                         drm_core_ioremapfree( dev->agp_buffer_map, dev );
1621                         dev->agp_buffer_map = NULL;
1622                 }
1623         } else
1624 #endif
1625         {
1626                 if (dev_priv->gart_info.bus_addr)
1627                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1628                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1629
1630                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1631                 {
1632                         drm_ioremapfree((void *)dev_priv->gart_info.addr, RADEON_PCIGART_TABLE_SIZE, dev);
1633                         dev_priv->gart_info.addr = 0;
1634                 }
1635         }
1636
1637         /* only clear to the start of flags */
1638         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1639
1640         return 0;
1641 }
1642
1643 /* This code will reinit the Radeon CP hardware after a resume from disc.
1644  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1645  * here we make sure that all Radeon hardware initialisation is re-done without
1646  * affecting running applications.
1647  *
1648  * Charl P. Botha <http://cpbotha.net>
1649  */
1650 static int radeon_do_resume_cp( drm_device_t *dev )
1651 {
1652         drm_radeon_private_t *dev_priv = dev->dev_private;
1653
1654         if ( !dev_priv ) {
1655                 DRM_ERROR( "Called with no initialization\n" );
1656                 return DRM_ERR( EINVAL );
1657         }
1658
1659         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1660
1661 #if __OS_HAS_AGP
1662         if ( !dev_priv->is_pci ) {
1663                 /* Turn off PCI GART */
1664                 radeon_set_pcigart( dev_priv, 0 );
1665         } else
1666 #endif
1667         {
1668                 /* Turn on PCI GART */
1669                 radeon_set_pcigart( dev_priv, 1 );
1670         }
1671
1672         radeon_cp_load_microcode( dev_priv );
1673         radeon_cp_init_ring_buffer( dev, dev_priv );
1674
1675         radeon_do_engine_reset( dev );
1676
1677         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1678
1679         return 0;
1680 }
1681
1682
1683 int radeon_cp_init( DRM_IOCTL_ARGS )
1684 {
1685         DRM_DEVICE;
1686         drm_radeon_init_t init;
1687
1688         LOCK_TEST_WITH_RETURN( dev, filp );
1689
1690         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1691
1692         if(init.func == RADEON_INIT_R300_CP)
1693                 r300_init_reg_flags();
1694
1695         switch ( init.func ) {
1696         case RADEON_INIT_CP:
1697         case RADEON_INIT_R200_CP:
1698         case RADEON_INIT_R300_CP:
1699                 return radeon_do_init_cp( dev, &init );
1700         case RADEON_CLEANUP_CP:
1701                 return radeon_do_cleanup_cp( dev );
1702         }
1703
1704         return DRM_ERR(EINVAL);
1705 }
1706
1707 int radeon_cp_start( DRM_IOCTL_ARGS )
1708 {
1709         DRM_DEVICE;
1710         drm_radeon_private_t *dev_priv = dev->dev_private;
1711         DRM_DEBUG( "\n" );
1712
1713         LOCK_TEST_WITH_RETURN( dev, filp );
1714
1715         if ( dev_priv->cp_running ) {
1716                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1717                 return 0;
1718         }
1719         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1720                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1721                            __FUNCTION__, dev_priv->cp_mode );
1722                 return 0;
1723         }
1724
1725         radeon_do_cp_start( dev_priv );
1726
1727         return 0;
1728 }
1729
1730 /* Stop the CP.  The engine must have been idled before calling this
1731  * routine.
1732  */
1733 int radeon_cp_stop( DRM_IOCTL_ARGS )
1734 {
1735         DRM_DEVICE;
1736         drm_radeon_private_t *dev_priv = dev->dev_private;
1737         drm_radeon_cp_stop_t stop;
1738         int ret;
1739         DRM_DEBUG( "\n" );
1740
1741         LOCK_TEST_WITH_RETURN( dev, filp );
1742
1743         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1744
1745         if (!dev_priv->cp_running)
1746                 return 0;
1747
1748         /* Flush any pending CP commands.  This ensures any outstanding
1749          * commands are exectuted by the engine before we turn it off.
1750          */
1751         if ( stop.flush ) {
1752                 radeon_do_cp_flush( dev_priv );
1753         }
1754
1755         /* If we fail to make the engine go idle, we return an error
1756          * code so that the DRM ioctl wrapper can try again.
1757          */
1758         if ( stop.idle ) {
1759                 ret = radeon_do_cp_idle( dev_priv );
1760                 if ( ret ) return ret;
1761         }
1762
1763         /* Finally, we can turn off the CP.  If the engine isn't idle,
1764          * we will get some dropped triangles as they won't be fully
1765          * rendered before the CP is shut down.
1766          */
1767         radeon_do_cp_stop( dev_priv );
1768
1769         /* Reset the engine */
1770         radeon_do_engine_reset( dev );
1771
1772         return 0;
1773 }
1774
1775
1776 void radeon_do_release( drm_device_t *dev )
1777 {
1778         drm_radeon_private_t *dev_priv = dev->dev_private;
1779         int i, ret;
1780
1781         if (dev_priv) {
1782                 if (dev_priv->cp_running) {
1783                         /* Stop the cp */
1784                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1785                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1786 #ifdef __linux__
1787                                 schedule();
1788 #else
1789                                 tsleep(&ret, PZERO, "rdnrel", 1);
1790 #endif
1791                         }
1792                         radeon_do_cp_stop( dev_priv );
1793                         radeon_do_engine_reset( dev );
1794                 }
1795
1796                 /* Disable *all* interrupts */
1797                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1798                         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1799
1800                 if (dev_priv->mmio) {/* remove all surfaces */
1801                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1802                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1803                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1804                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1805                         }
1806                 }
1807
1808                 /* Free memory heap structures */
1809                 radeon_mem_takedown( &(dev_priv->gart_heap) );
1810                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1811
1812                 /* deallocate kernel resources */
1813                 radeon_do_cleanup_cp( dev );
1814         }
1815 }
1816
1817 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1818  */
1819 int radeon_cp_reset( DRM_IOCTL_ARGS )
1820 {
1821         DRM_DEVICE;
1822         drm_radeon_private_t *dev_priv = dev->dev_private;
1823         DRM_DEBUG( "\n" );
1824
1825         LOCK_TEST_WITH_RETURN( dev, filp );
1826
1827         if ( !dev_priv ) {
1828                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1829                 return DRM_ERR(EINVAL);
1830         }
1831
1832         radeon_do_cp_reset( dev_priv );
1833
1834         /* The CP is no longer running after an engine reset */
1835         dev_priv->cp_running = 0;
1836
1837         return 0;
1838 }
1839
1840 int radeon_cp_idle( DRM_IOCTL_ARGS )
1841 {
1842         DRM_DEVICE;
1843         drm_radeon_private_t *dev_priv = dev->dev_private;
1844         DRM_DEBUG( "\n" );
1845
1846         LOCK_TEST_WITH_RETURN( dev, filp );
1847
1848         return radeon_do_cp_idle( dev_priv );
1849 }
1850
1851 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1852  */
1853 int radeon_cp_resume( DRM_IOCTL_ARGS )
1854 {
1855         DRM_DEVICE;
1856
1857         return radeon_do_resume_cp(dev);
1858 }
1859
1860
1861 int radeon_engine_reset( DRM_IOCTL_ARGS )
1862 {
1863         DRM_DEVICE;
1864         DRM_DEBUG( "\n" );
1865
1866         LOCK_TEST_WITH_RETURN( dev, filp );
1867
1868         return radeon_do_engine_reset( dev );
1869 }
1870
1871
1872 /* ================================================================
1873  * Fullscreen mode
1874  */
1875
1876 /* KW: Deprecated to say the least:
1877  */
1878 int radeon_fullscreen( DRM_IOCTL_ARGS )
1879 {
1880         return 0;
1881 }
1882
1883
1884 /* ================================================================
1885  * Freelist management
1886  */
1887
1888 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1889  *   bufs until freelist code is used.  Note this hides a problem with
1890  *   the scratch register * (used to keep track of last buffer
1891  *   completed) being written to before * the last buffer has actually
1892  *   completed rendering.
1893  *
1894  * KW:  It's also a good way to find free buffers quickly.
1895  *
1896  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1897  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1898  * we essentially have to do this, else old clients will break.
1899  *
1900  * However, it does leave open a potential deadlock where all the
1901  * buffers are held by other clients, which can't release them because
1902  * they can't get the lock.
1903  */
1904
1905 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1906 {
1907         drm_device_dma_t *dma = dev->dma;
1908         drm_radeon_private_t *dev_priv = dev->dev_private;
1909         drm_radeon_buf_priv_t *buf_priv;
1910         drm_buf_t *buf;
1911         int i, t;
1912         int start;
1913
1914         if ( ++dev_priv->last_buf >= dma->buf_count )
1915                 dev_priv->last_buf = 0;
1916
1917         start = dev_priv->last_buf;
1918
1919         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1920                 u32 done_age = GET_SCRATCH( 1 );
1921                 DRM_DEBUG("done_age = %d\n",done_age);
1922                 for ( i = start ; i < dma->buf_count ; i++ ) {
1923                         buf = dma->buflist[i];
1924                         buf_priv = buf->dev_private;
1925                         if ( buf->filp == 0 || (buf->pending &&
1926                                                buf_priv->age <= done_age) ) {
1927                                 dev_priv->stats.requested_bufs++;
1928                                 buf->pending = 0;
1929                                 return buf;
1930                         }
1931                         start = 0;
1932                 }
1933
1934                 if (t) {
1935                         DRM_UDELAY( 1 );
1936                         dev_priv->stats.freelist_loops++;
1937                 }
1938         }
1939
1940         DRM_DEBUG( "returning NULL!\n" );
1941         return NULL;
1942 }
1943 #if 0
1944 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1945 {
1946         drm_device_dma_t *dma = dev->dma;
1947         drm_radeon_private_t *dev_priv = dev->dev_private;
1948         drm_radeon_buf_priv_t *buf_priv;
1949         drm_buf_t *buf;
1950         int i, t;
1951         int start;
1952         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1953
1954         if ( ++dev_priv->last_buf >= dma->buf_count )
1955                 dev_priv->last_buf = 0;
1956
1957         start = dev_priv->last_buf;
1958         dev_priv->stats.freelist_loops++;
1959
1960         for ( t = 0 ; t < 2 ; t++ ) {
1961                 for ( i = start ; i < dma->buf_count ; i++ ) {
1962                         buf = dma->buflist[i];
1963                         buf_priv = buf->dev_private;
1964                         if ( buf->filp == 0 || (buf->pending &&
1965                                                buf_priv->age <= done_age) ) {
1966                                 dev_priv->stats.requested_bufs++;
1967                                 buf->pending = 0;
1968                                 return buf;
1969                         }
1970                 }
1971                 start = 0;
1972         }
1973
1974         return NULL;
1975 }
1976 #endif
1977
1978 void radeon_freelist_reset( drm_device_t *dev )
1979 {
1980         drm_device_dma_t *dma = dev->dma;
1981         drm_radeon_private_t *dev_priv = dev->dev_private;
1982         int i;
1983
1984         dev_priv->last_buf = 0;
1985         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1986                 drm_buf_t *buf = dma->buflist[i];
1987                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1988                 buf_priv->age = 0;
1989         }
1990 }
1991
1992
1993 /* ================================================================
1994  * CP command submission
1995  */
1996
1997 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1998 {
1999         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2000         int i;
2001         u32 last_head = GET_RING_HEAD( dev_priv );
2002
2003         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
2004                 u32 head = GET_RING_HEAD( dev_priv );
2005
2006                 ring->space = (head - ring->tail) * sizeof(u32);
2007                 if ( ring->space <= 0 )
2008                         ring->space += ring->size;
2009                 if ( ring->space > n )
2010                         return 0;
2011
2012                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2013
2014                 if (head != last_head)
2015                         i = 0;
2016                 last_head = head;
2017
2018                 DRM_UDELAY( 1 );
2019         }
2020
2021         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2022 #if RADEON_FIFO_DEBUG
2023         radeon_status( dev_priv );
2024         DRM_ERROR( "failed!\n" );
2025 #endif
2026         return DRM_ERR(EBUSY);
2027 }
2028
2029 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
2030 {
2031         int i;
2032         drm_buf_t *buf;
2033
2034         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
2035                 buf = radeon_freelist_get( dev );
2036                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
2037
2038                 buf->filp = filp;
2039
2040                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
2041                                    sizeof(buf->idx) ) )
2042                         return DRM_ERR(EFAULT);
2043                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
2044                                    sizeof(buf->total) ) )
2045                         return DRM_ERR(EFAULT);
2046
2047                 d->granted_count++;
2048         }
2049         return 0;
2050 }
2051
2052 int radeon_cp_buffers( DRM_IOCTL_ARGS )
2053 {
2054         DRM_DEVICE;
2055         drm_device_dma_t *dma = dev->dma;
2056         int ret = 0;
2057         drm_dma_t __user *argp = (void __user *)data;
2058         drm_dma_t d;
2059
2060         LOCK_TEST_WITH_RETURN( dev, filp );
2061
2062         DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
2063
2064         /* Please don't send us buffers.
2065          */
2066         if ( d.send_count != 0 ) {
2067                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
2068                            DRM_CURRENTPID, d.send_count );
2069                 return DRM_ERR(EINVAL);
2070         }
2071
2072         /* We'll send you buffers.
2073          */
2074         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
2075                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
2076                            DRM_CURRENTPID, d.request_count, dma->buf_count );
2077                 return DRM_ERR(EINVAL);
2078         }
2079
2080         d.granted_count = 0;
2081
2082         if ( d.request_count ) {
2083                 ret = radeon_cp_get_buffers( filp, dev, &d );
2084         }
2085
2086         DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
2087
2088         return ret;
2089 }
2090
2091 int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2092 {
2093         drm_radeon_private_t *dev_priv;
2094         int ret = 0;
2095
2096         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2097         if (dev_priv == NULL)
2098                 return DRM_ERR(ENOMEM);
2099
2100         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2101         dev->dev_private = (void *)dev_priv;
2102         dev_priv->flags = flags;
2103
2104         switch (flags & CHIP_FAMILY_MASK) {
2105         case CHIP_R100:
2106         case CHIP_RV200:
2107         case CHIP_R200:
2108         case CHIP_R300:
2109         case CHIP_R420:
2110                 dev_priv->flags |= CHIP_HAS_HIERZ;
2111                 break;
2112         default:
2113         /* all other chips have no hierarchical z buffer */
2114                 break;
2115         }
2116
2117         if (drm_device_is_agp(dev))
2118                 dev_priv->flags |= CHIP_IS_AGP;
2119
2120         if (drm_device_is_pcie(dev))
2121                 dev_priv->flags |= CHIP_IS_PCIE;
2122
2123         DRM_DEBUG("%s card detected\n",
2124                   ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2125         return ret;
2126 }
2127
2128 int radeon_presetup(struct drm_device *dev)
2129 {
2130         int ret;
2131         drm_local_map_t *map;
2132         drm_radeon_private_t *dev_priv = dev->dev_private;
2133
2134         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2135                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2136                          _DRM_READ_ONLY, &dev_priv->mmio);
2137         if (ret != 0)
2138                 return ret;
2139
2140         ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2141                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2142                          _DRM_WRITE_COMBINING, &map);
2143         if (ret != 0)
2144                 return ret;
2145
2146         return 0;
2147 }
2148
2149 int radeon_driver_postcleanup(struct drm_device *dev)
2150 {
2151         drm_radeon_private_t *dev_priv = dev->dev_private;
2152
2153         DRM_DEBUG("\n");
2154
2155         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2156
2157         dev->dev_private = NULL;
2158         return 0;
2159 }