1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/cpu_pm.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21 #include <linux/timekeeping.h>
22 #include <linux/iopoll.h>
24 #include <linux/platform_data/ti-sysc.h>
26 #include <dt-bindings/bus/ti-sysc.h>
28 #define DIS_ISP BIT(2)
29 #define DIS_IVA BIT(1)
30 #define DIS_SGX BIT(0)
32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
34 #define MAX_MODULE_SOFTRESET_WAIT 10000
53 struct list_head node;
58 struct list_head node;
61 struct sysc_soc_info {
62 unsigned long general_purpose:1;
64 struct mutex list_lock; /* disabled and restored modules list lock */
65 struct list_head disabled_modules;
66 struct list_head restored_modules;
67 struct notifier_block nb;
84 static struct sysc_soc_info *sysc_soc;
85 static const char * const reg_names[] = { "rev", "sysc", "syss", };
86 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
88 "opt5", "opt6", "opt7",
91 #define SYSC_IDLEMODE_MASK 3
92 #define SYSC_CLOCKACTIVITY_MASK 3
95 * struct sysc - TI sysc interconnect target module registers and capabilities
96 * @dev: struct device pointer
97 * @module_pa: physical address of the interconnect target module
98 * @module_size: size of the interconnect target module
99 * @module_va: virtual address of the interconnect target module
100 * @offsets: register offsets from module base
101 * @mdata: ti-sysc to hwmod translation data for a module
102 * @clocks: clocks used by the interconnect target module
103 * @clock_roles: clock role names for the found clocks
104 * @nr_clocks: number of clocks used by the interconnect target module
105 * @rsts: resets used by the interconnect target module
106 * @legacy_mode: configured for legacy mode if set
107 * @cap: interconnect target module capabilities
108 * @cfg: interconnect target module configuration
109 * @cookie: data used by legacy platform callbacks
110 * @name: name if available
111 * @revision: interconnect target module revision
112 * @reserved: target module is reserved and already in use
113 * @enabled: sysc runtime enabled status
114 * @needs_resume: runtime resume needed on resume from suspend
115 * @child_needs_resume: runtime resume needed for child on resume from suspend
116 * @disable_on_idle: status flag used for disabling modules with resets
117 * @idle_work: work structure used to perform delayed idle on a module
118 * @pre_reset_quirk: module specific pre-reset quirk
119 * @post_reset_quirk: module specific post-reset quirk
120 * @reset_done_quirk: module specific reset done quirk
121 * @module_enable_quirk: module specific enable quirk
122 * @module_disable_quirk: module specific disable quirk
123 * @module_unlock_quirk: module specific sysconfig unlock quirk
124 * @module_lock_quirk: module specific sysconfig lock quirk
130 void __iomem *module_va;
131 int offsets[SYSC_MAX_REGS];
132 struct ti_sysc_module_data *mdata;
134 const char **clock_roles;
136 struct reset_control *rsts;
137 const char *legacy_mode;
138 const struct sysc_capabilities *cap;
139 struct sysc_config cfg;
140 struct ti_sysc_cookie cookie;
144 unsigned int reserved:1;
145 unsigned int enabled:1;
146 unsigned int needs_resume:1;
147 unsigned int child_needs_resume:1;
148 struct delayed_work idle_work;
149 void (*pre_reset_quirk)(struct sysc *sysc);
150 void (*post_reset_quirk)(struct sysc *sysc);
151 void (*reset_done_quirk)(struct sysc *sysc);
152 void (*module_enable_quirk)(struct sysc *sysc);
153 void (*module_disable_quirk)(struct sysc *sysc);
154 void (*module_unlock_quirk)(struct sysc *sysc);
155 void (*module_lock_quirk)(struct sysc *sysc);
158 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
160 static int sysc_reset(struct sysc *ddata);
162 static void sysc_write(struct sysc *ddata, int offset, u32 value)
164 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
165 writew_relaxed(value & 0xffff, ddata->module_va + offset);
167 /* Only i2c revision has LO and HI register with stride of 4 */
168 if (ddata->offsets[SYSC_REVISION] >= 0 &&
169 offset == ddata->offsets[SYSC_REVISION]) {
170 u16 hi = value >> 16;
172 writew_relaxed(hi, ddata->module_va + offset + 4);
178 writel_relaxed(value, ddata->module_va + offset);
181 static u32 sysc_read(struct sysc *ddata, int offset)
183 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
186 val = readw_relaxed(ddata->module_va + offset);
188 /* Only i2c revision has LO and HI register with stride of 4 */
189 if (ddata->offsets[SYSC_REVISION] >= 0 &&
190 offset == ddata->offsets[SYSC_REVISION]) {
191 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
199 return readl_relaxed(ddata->module_va + offset);
202 static bool sysc_opt_clks_needed(struct sysc *ddata)
204 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
207 static u32 sysc_read_revision(struct sysc *ddata)
209 int offset = ddata->offsets[SYSC_REVISION];
214 return sysc_read(ddata, offset);
217 static u32 sysc_read_sysconfig(struct sysc *ddata)
219 int offset = ddata->offsets[SYSC_SYSCONFIG];
224 return sysc_read(ddata, offset);
227 static u32 sysc_read_sysstatus(struct sysc *ddata)
229 int offset = ddata->offsets[SYSC_SYSSTATUS];
234 return sysc_read(ddata, offset);
237 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
240 u32 syss_done, rstval;
242 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
245 syss_done = ddata->cfg.syss_mask;
247 if (likely(!timekeeping_suspended)) {
248 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
249 rstval, (rstval & ddata->cfg.syss_mask) ==
250 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
252 retries = MAX_MODULE_SOFTRESET_WAIT;
254 rstval = sysc_read_sysstatus(ddata);
255 if ((rstval & ddata->cfg.syss_mask) == syss_done)
257 udelay(2); /* Account for udelay flakeyness */
265 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
268 u32 sysc_mask, rstval;
270 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
272 if (likely(!timekeeping_suspended)) {
273 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
274 rstval, !(rstval & sysc_mask),
275 100, MAX_MODULE_SOFTRESET_WAIT);
277 retries = MAX_MODULE_SOFTRESET_WAIT;
279 rstval = sysc_read_sysconfig(ddata);
280 if (!(rstval & sysc_mask))
282 udelay(2); /* Account for udelay flakeyness */
290 /* Poll on reset status */
291 static int sysc_wait_softreset(struct sysc *ddata)
293 int syss_offset, error = 0;
295 if (ddata->cap->regbits->srst_shift < 0)
298 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
300 if (syss_offset >= 0)
301 error = sysc_poll_reset_sysstatus(ddata);
302 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
303 error = sysc_poll_reset_sysconfig(ddata);
308 static int sysc_add_named_clock_from_child(struct sysc *ddata,
310 const char *optfck_name)
312 struct device_node *np = ddata->dev->of_node;
313 struct device_node *child;
314 struct clk_lookup *cl;
323 /* Does the clock alias already exist? */
324 clock = of_clk_get_by_name(np, n);
325 if (!IS_ERR(clock)) {
331 child = of_get_next_available_child(np, NULL);
335 clock = devm_get_clk_from_child(ddata->dev, child, name);
337 return PTR_ERR(clock);
340 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
341 * limit for clk_get(). If cl ever needs to be freed, it should be done
342 * with clkdev_drop().
344 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
349 cl->dev_id = dev_name(ddata->dev);
358 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
360 const char *optfck_name;
363 if (ddata->nr_clocks < SYSC_OPTFCK0)
364 index = SYSC_OPTFCK0;
366 index = ddata->nr_clocks;
371 optfck_name = clock_names[index];
373 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
377 ddata->clock_roles[index] = optfck_name;
383 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
385 int error, i, index = -ENODEV;
387 if (!strncmp(clock_names[SYSC_FCK], name, 3))
389 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
393 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
394 if (!ddata->clocks[i]) {
402 dev_err(ddata->dev, "clock %s not added\n", name);
406 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
407 if (IS_ERR(ddata->clocks[index])) {
408 dev_err(ddata->dev, "clock get error for %s: %li\n",
409 name, PTR_ERR(ddata->clocks[index]));
411 return PTR_ERR(ddata->clocks[index]);
414 error = clk_prepare(ddata->clocks[index]);
416 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
425 static int sysc_get_clocks(struct sysc *ddata)
427 struct device_node *np = ddata->dev->of_node;
428 struct property *prop;
430 int nr_fck = 0, nr_ick = 0, i, error = 0;
432 ddata->clock_roles = devm_kcalloc(ddata->dev,
434 sizeof(*ddata->clock_roles),
436 if (!ddata->clock_roles)
439 of_property_for_each_string(np, "clock-names", prop, name) {
440 if (!strncmp(clock_names[SYSC_FCK], name, 3))
442 if (!strncmp(clock_names[SYSC_ICK], name, 3))
444 ddata->clock_roles[ddata->nr_clocks] = name;
448 if (ddata->nr_clocks < 1)
451 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
452 error = sysc_init_ext_opt_clock(ddata, NULL);
457 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
458 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
463 if (nr_fck > 1 || nr_ick > 1) {
464 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
469 /* Always add a slot for main clocks fck and ick even if unused */
475 ddata->clocks = devm_kcalloc(ddata->dev,
476 ddata->nr_clocks, sizeof(*ddata->clocks),
481 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
482 const char *name = ddata->clock_roles[i];
487 error = sysc_get_one_clock(ddata, name);
495 static int sysc_enable_main_clocks(struct sysc *ddata)
503 for (i = 0; i < SYSC_OPTFCK0; i++) {
504 clock = ddata->clocks[i];
506 /* Main clocks may not have ick */
507 if (IS_ERR_OR_NULL(clock))
510 error = clk_enable(clock);
518 for (i--; i >= 0; i--) {
519 clock = ddata->clocks[i];
521 /* Main clocks may not have ick */
522 if (IS_ERR_OR_NULL(clock))
531 static void sysc_disable_main_clocks(struct sysc *ddata)
539 for (i = 0; i < SYSC_OPTFCK0; i++) {
540 clock = ddata->clocks[i];
541 if (IS_ERR_OR_NULL(clock))
548 static int sysc_enable_opt_clocks(struct sysc *ddata)
553 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
556 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
557 clock = ddata->clocks[i];
559 /* Assume no holes for opt clocks */
560 if (IS_ERR_OR_NULL(clock))
563 error = clk_enable(clock);
571 for (i--; i >= 0; i--) {
572 clock = ddata->clocks[i];
573 if (IS_ERR_OR_NULL(clock))
582 static void sysc_disable_opt_clocks(struct sysc *ddata)
587 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
590 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
591 clock = ddata->clocks[i];
593 /* Assume no holes for opt clocks */
594 if (IS_ERR_OR_NULL(clock))
601 static void sysc_clkdm_deny_idle(struct sysc *ddata)
603 struct ti_sysc_platform_data *pdata;
605 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
608 pdata = dev_get_platdata(ddata->dev);
609 if (pdata && pdata->clkdm_deny_idle)
610 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
613 static void sysc_clkdm_allow_idle(struct sysc *ddata)
615 struct ti_sysc_platform_data *pdata;
617 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
620 pdata = dev_get_platdata(ddata->dev);
621 if (pdata && pdata->clkdm_allow_idle)
622 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
626 * sysc_init_resets - init rstctrl reset line if configured
627 * @ddata: device driver data
629 * See sysc_rstctrl_reset_deassert().
631 static int sysc_init_resets(struct sysc *ddata)
634 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
636 return PTR_ERR_OR_ZERO(ddata->rsts);
640 * sysc_parse_and_check_child_range - parses module IO region from ranges
641 * @ddata: device driver data
643 * In general we only need rev, syss, and sysc registers and not the whole
644 * module range. But we do want the offsets for these registers from the
645 * module base. This allows us to check them against the legacy hwmod
646 * platform data. Let's also check the ranges are configured properly.
648 static int sysc_parse_and_check_child_range(struct sysc *ddata)
650 struct device_node *np = ddata->dev->of_node;
651 const __be32 *ranges;
652 u32 nr_addr, nr_size;
655 ranges = of_get_property(np, "ranges", &len);
657 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
662 len /= sizeof(*ranges);
665 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
670 error = of_property_read_u32(np, "#address-cells", &nr_addr);
674 error = of_property_read_u32(np, "#size-cells", &nr_size);
678 if (nr_addr != 1 || nr_size != 1) {
679 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
685 ddata->module_pa = of_translate_address(np, ranges++);
686 ddata->module_size = be32_to_cpup(ranges);
691 /* Interconnect instances to probe before l4_per instances */
692 static struct resource early_bus_ranges[] = {
694 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
695 /* omap4/5 and dra7 l4_cfg */
696 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
698 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
699 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
700 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
703 static atomic_t sysc_defer = ATOMIC_INIT(10);
706 * sysc_defer_non_critical - defer non_critical interconnect probing
707 * @ddata: device driver data
709 * We want to probe l4_cfg and l4_wkup interconnect instances before any
710 * l4_per instances as l4_per instances depend on resources on l4_cfg and
711 * l4_wkup interconnects.
713 static int sysc_defer_non_critical(struct sysc *ddata)
715 struct resource *res;
718 if (!atomic_read(&sysc_defer))
721 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
722 res = &early_bus_ranges[i];
723 if (ddata->module_pa >= res->start &&
724 ddata->module_pa <= res->end) {
725 atomic_set(&sysc_defer, 0);
731 atomic_dec_if_positive(&sysc_defer);
733 return -EPROBE_DEFER;
736 static struct device_node *stdout_path;
738 static void sysc_init_stdout_path(struct sysc *ddata)
740 struct device_node *np = NULL;
743 if (IS_ERR(stdout_path))
749 np = of_find_node_by_path("/chosen");
753 uart = of_get_property(np, "stdout-path", NULL);
757 np = of_find_node_by_path(uart);
766 stdout_path = ERR_PTR(-ENODEV);
769 static void sysc_check_quirk_stdout(struct sysc *ddata,
770 struct device_node *np)
772 sysc_init_stdout_path(ddata);
773 if (np != stdout_path)
776 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
777 SYSC_QUIRK_NO_RESET_ON_INIT;
781 * sysc_check_one_child - check child configuration
782 * @ddata: device driver data
783 * @np: child device node
785 * Let's avoid messy situations where we have new interconnect target
786 * node but children have "ti,hwmods". These belong to the interconnect
787 * target node and are managed by this driver.
789 static void sysc_check_one_child(struct sysc *ddata,
790 struct device_node *np)
794 name = of_get_property(np, "ti,hwmods", NULL);
795 if (name && !of_device_is_compatible(np, "ti,sysc"))
796 dev_warn(ddata->dev, "really a child ti,hwmods property?");
798 sysc_check_quirk_stdout(ddata, np);
799 sysc_parse_dts_quirks(ddata, np, true);
802 static void sysc_check_children(struct sysc *ddata)
804 struct device_node *child;
806 for_each_child_of_node(ddata->dev->of_node, child)
807 sysc_check_one_child(ddata, child);
811 * So far only I2C uses 16-bit read access with clockactivity with revision
812 * in two registers with stride of 4. We can detect this based on the rev
813 * register size to configure things far enough to be able to properly read
814 * the revision register.
816 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
818 if (resource_size(res) == 8)
819 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
823 * sysc_parse_one - parses the interconnect target module registers
824 * @ddata: device driver data
825 * @reg: register to parse
827 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
829 struct resource *res;
836 name = reg_names[reg];
842 res = platform_get_resource_byname(to_platform_device(ddata->dev),
843 IORESOURCE_MEM, name);
845 ddata->offsets[reg] = -ENODEV;
850 ddata->offsets[reg] = res->start - ddata->module_pa;
851 if (reg == SYSC_REVISION)
852 sysc_check_quirk_16bit(ddata, res);
857 static int sysc_parse_registers(struct sysc *ddata)
861 for (i = 0; i < SYSC_MAX_REGS; i++) {
862 error = sysc_parse_one(ddata, i);
871 * sysc_check_registers - check for misconfigured register overlaps
872 * @ddata: device driver data
874 static int sysc_check_registers(struct sysc *ddata)
876 int i, j, nr_regs = 0, nr_matches = 0;
878 for (i = 0; i < SYSC_MAX_REGS; i++) {
879 if (ddata->offsets[i] < 0)
882 if (ddata->offsets[i] > (ddata->module_size - 4)) {
883 dev_err(ddata->dev, "register outside module range");
888 for (j = 0; j < SYSC_MAX_REGS; j++) {
889 if (ddata->offsets[j] < 0)
892 if (ddata->offsets[i] == ddata->offsets[j])
898 if (nr_matches > nr_regs) {
899 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
900 nr_regs, nr_matches);
909 * sysc_ioremap - ioremap register space for the interconnect target module
910 * @ddata: device driver data
912 * Note that the interconnect target module registers can be anywhere
913 * within the interconnect target module range. For example, SGX has
914 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
915 * has them at offset 0x1200 in the CPSW_WR child. Usually the
916 * the interconnect target module registers are at the beginning of
917 * the module range though.
919 static int sysc_ioremap(struct sysc *ddata)
923 if (ddata->offsets[SYSC_REVISION] < 0 &&
924 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
925 ddata->offsets[SYSC_SYSSTATUS] < 0) {
926 size = ddata->module_size;
928 size = max3(ddata->offsets[SYSC_REVISION],
929 ddata->offsets[SYSC_SYSCONFIG],
930 ddata->offsets[SYSC_SYSSTATUS]);
935 if ((size + sizeof(u32)) > ddata->module_size)
936 size = ddata->module_size;
939 ddata->module_va = devm_ioremap(ddata->dev,
942 if (!ddata->module_va)
949 * sysc_map_and_check_registers - ioremap and check device registers
950 * @ddata: device driver data
952 static int sysc_map_and_check_registers(struct sysc *ddata)
954 struct device_node *np = ddata->dev->of_node;
957 error = sysc_parse_and_check_child_range(ddata);
961 error = sysc_defer_non_critical(ddata);
965 sysc_check_children(ddata);
967 if (!of_get_property(np, "reg", NULL))
970 error = sysc_parse_registers(ddata);
974 error = sysc_ioremap(ddata);
978 error = sysc_check_registers(ddata);
986 * sysc_show_rev - read and show interconnect target module revision
987 * @bufp: buffer to print the information to
988 * @ddata: device driver data
990 static int sysc_show_rev(char *bufp, struct sysc *ddata)
994 if (ddata->offsets[SYSC_REVISION] < 0)
995 return sprintf(bufp, ":NA");
997 len = sprintf(bufp, ":%08x", ddata->revision);
1002 static int sysc_show_reg(struct sysc *ddata,
1003 char *bufp, enum sysc_registers reg)
1005 if (ddata->offsets[reg] < 0)
1006 return sprintf(bufp, ":NA");
1008 return sprintf(bufp, ":%x", ddata->offsets[reg]);
1011 static int sysc_show_name(char *bufp, struct sysc *ddata)
1016 return sprintf(bufp, ":%s", ddata->name);
1020 * sysc_show_registers - show information about interconnect target module
1021 * @ddata: device driver data
1023 static void sysc_show_registers(struct sysc *ddata)
1029 for (i = 0; i < SYSC_MAX_REGS; i++)
1030 bufp += sysc_show_reg(ddata, bufp, i);
1032 bufp += sysc_show_rev(bufp, ddata);
1033 bufp += sysc_show_name(bufp, ddata);
1035 dev_dbg(ddata->dev, "%llx:%x%s\n",
1036 ddata->module_pa, ddata->module_size,
1041 * sysc_write_sysconfig - handle sysconfig quirks for register write
1042 * @ddata: device driver data
1043 * @value: register value
1045 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1047 if (ddata->module_unlock_quirk)
1048 ddata->module_unlock_quirk(ddata);
1050 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1052 if (ddata->module_lock_quirk)
1053 ddata->module_lock_quirk(ddata);
1056 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1057 #define SYSC_CLOCACT_ICK 2
1059 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1060 static int sysc_enable_module(struct device *dev)
1063 const struct sysc_regbits *regbits;
1064 u32 reg, idlemodes, best_mode;
1067 ddata = dev_get_drvdata(dev);
1070 * Some modules like DSS reset automatically on idle. Enable optional
1071 * reset clocks and wait for OCP softreset to complete.
1073 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1074 error = sysc_enable_opt_clocks(ddata);
1077 "Optional clocks failed for enable: %i\n",
1083 * Some modules like i2c and hdq1w have unusable reset status unless
1084 * the module reset quirk is enabled. Skip status check on enable.
1086 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1087 error = sysc_wait_softreset(ddata);
1089 dev_warn(ddata->dev, "OCP softreset timed out\n");
1091 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1092 sysc_disable_opt_clocks(ddata);
1095 * Some subsystem private interconnects, like DSS top level module,
1096 * need only the automatic OCP softreset handling with no sysconfig
1097 * register bits to configure.
1099 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1102 regbits = ddata->cap->regbits;
1103 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1106 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1107 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1108 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1110 if (regbits->clkact_shift >= 0 &&
1111 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1112 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1114 /* Set SIDLE mode */
1115 idlemodes = ddata->cfg.sidlemodes;
1116 if (!idlemodes || regbits->sidle_shift < 0)
1119 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1120 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1121 best_mode = SYSC_IDLE_NO;
1123 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1124 if (best_mode > SYSC_IDLE_MASK) {
1125 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1130 if (regbits->enwkup_shift >= 0 &&
1131 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1132 reg |= BIT(regbits->enwkup_shift);
1135 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1136 reg |= best_mode << regbits->sidle_shift;
1137 sysc_write_sysconfig(ddata, reg);
1140 /* Set MIDLE mode */
1141 idlemodes = ddata->cfg.midlemodes;
1142 if (!idlemodes || regbits->midle_shift < 0)
1145 best_mode = fls(ddata->cfg.midlemodes) - 1;
1146 if (best_mode > SYSC_IDLE_MASK) {
1147 dev_err(dev, "%s: invalid midlemode\n", __func__);
1152 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1153 best_mode = SYSC_IDLE_NO;
1155 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1156 reg |= best_mode << regbits->midle_shift;
1157 sysc_write_sysconfig(ddata, reg);
1160 /* Autoidle bit must enabled separately if available */
1161 if (regbits->autoidle_shift >= 0 &&
1162 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1163 reg |= 1 << regbits->autoidle_shift;
1164 sysc_write_sysconfig(ddata, reg);
1170 /* Save context and flush posted write */
1171 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1173 if (ddata->module_enable_quirk)
1174 ddata->module_enable_quirk(ddata);
1179 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1181 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1182 *best_mode = SYSC_IDLE_SMART_WKUP;
1183 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1184 *best_mode = SYSC_IDLE_SMART;
1185 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1186 *best_mode = SYSC_IDLE_FORCE;
1193 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1194 static int sysc_disable_module(struct device *dev)
1197 const struct sysc_regbits *regbits;
1198 u32 reg, idlemodes, best_mode;
1201 ddata = dev_get_drvdata(dev);
1202 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1205 if (ddata->module_disable_quirk)
1206 ddata->module_disable_quirk(ddata);
1208 regbits = ddata->cap->regbits;
1209 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1211 /* Set MIDLE mode */
1212 idlemodes = ddata->cfg.midlemodes;
1213 if (!idlemodes || regbits->midle_shift < 0)
1216 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1218 dev_err(dev, "%s: invalid midlemode\n", __func__);
1222 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1223 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1224 best_mode = SYSC_IDLE_FORCE;
1226 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1227 reg |= best_mode << regbits->midle_shift;
1228 sysc_write_sysconfig(ddata, reg);
1231 /* Set SIDLE mode */
1232 idlemodes = ddata->cfg.sidlemodes;
1233 if (!idlemodes || regbits->sidle_shift < 0) {
1238 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1239 best_mode = SYSC_IDLE_FORCE;
1241 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1243 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1249 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1250 reg |= best_mode << regbits->sidle_shift;
1251 if (regbits->autoidle_shift >= 0 &&
1252 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1253 reg |= 1 << regbits->autoidle_shift;
1254 sysc_write_sysconfig(ddata, reg);
1259 /* Save context and flush posted write */
1260 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1265 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1268 struct ti_sysc_platform_data *pdata;
1271 pdata = dev_get_platdata(ddata->dev);
1275 if (!pdata->idle_module)
1278 error = pdata->idle_module(dev, &ddata->cookie);
1280 dev_err(dev, "%s: could not idle: %i\n",
1283 reset_control_assert(ddata->rsts);
1288 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1291 struct ti_sysc_platform_data *pdata;
1294 pdata = dev_get_platdata(ddata->dev);
1298 if (!pdata->enable_module)
1301 error = pdata->enable_module(dev, &ddata->cookie);
1303 dev_err(dev, "%s: could not enable: %i\n",
1306 reset_control_deassert(ddata->rsts);
1311 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1316 ddata = dev_get_drvdata(dev);
1318 if (!ddata->enabled)
1321 sysc_clkdm_deny_idle(ddata);
1323 if (ddata->legacy_mode) {
1324 error = sysc_runtime_suspend_legacy(dev, ddata);
1326 goto err_allow_idle;
1328 error = sysc_disable_module(dev);
1330 goto err_allow_idle;
1333 sysc_disable_main_clocks(ddata);
1335 if (sysc_opt_clks_needed(ddata))
1336 sysc_disable_opt_clocks(ddata);
1338 ddata->enabled = false;
1341 sysc_clkdm_allow_idle(ddata);
1343 reset_control_assert(ddata->rsts);
1348 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1353 ddata = dev_get_drvdata(dev);
1359 sysc_clkdm_deny_idle(ddata);
1361 if (sysc_opt_clks_needed(ddata)) {
1362 error = sysc_enable_opt_clocks(ddata);
1364 goto err_allow_idle;
1367 error = sysc_enable_main_clocks(ddata);
1369 goto err_opt_clocks;
1371 reset_control_deassert(ddata->rsts);
1373 if (ddata->legacy_mode) {
1374 error = sysc_runtime_resume_legacy(dev, ddata);
1376 goto err_main_clocks;
1378 error = sysc_enable_module(dev);
1380 goto err_main_clocks;
1383 ddata->enabled = true;
1385 sysc_clkdm_allow_idle(ddata);
1390 sysc_disable_main_clocks(ddata);
1392 if (sysc_opt_clks_needed(ddata))
1393 sysc_disable_opt_clocks(ddata);
1395 sysc_clkdm_allow_idle(ddata);
1401 * Checks if device context was lost. Assumes the sysconfig register value
1402 * after lost context is different from the configured value. Only works for
1405 * Eventually we may want to also add support to using the context lost
1406 * registers that some SoCs have.
1408 static int sysc_check_context(struct sysc *ddata)
1412 if (!ddata->enabled)
1415 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1416 if (reg == ddata->sysconfig)
1422 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1424 struct device *dev = ddata->dev;
1427 if (ddata->enabled) {
1428 /* Nothing to do if enabled and context not lost */
1429 error = sysc_check_context(ddata);
1433 /* Disable target module if it is enabled */
1434 error = sysc_runtime_suspend(dev);
1436 dev_warn(dev, "reinit suspend failed: %i\n", error);
1439 /* Enable target module */
1440 error = sysc_runtime_resume(dev);
1442 dev_warn(dev, "reinit resume failed: %i\n", error);
1444 /* Some modules like am335x gpmc need reset and restore of sysconfig */
1445 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) {
1446 error = sysc_reset(ddata);
1448 dev_warn(dev, "reinit reset failed: %i\n", error);
1450 sysc_write_sysconfig(ddata, ddata->sysconfig);
1456 /* Disable target module if no leave_enabled was set */
1457 error = sysc_runtime_suspend(dev);
1459 dev_warn(dev, "reinit suspend failed: %i\n", error);
1464 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1468 ddata = dev_get_drvdata(dev);
1470 if (ddata->cfg.quirks &
1471 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1474 if (!ddata->enabled)
1477 ddata->needs_resume = 1;
1479 return sysc_runtime_suspend(dev);
1482 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1487 ddata = dev_get_drvdata(dev);
1489 if (ddata->cfg.quirks &
1490 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1493 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1494 error = sysc_reinit_module(ddata, ddata->needs_resume);
1496 dev_warn(dev, "noirq_resume failed: %i\n", error);
1497 } else if (ddata->needs_resume) {
1498 error = sysc_runtime_resume(dev);
1500 dev_warn(dev, "noirq_resume failed: %i\n", error);
1503 ddata->needs_resume = 0;
1508 static const struct dev_pm_ops sysc_pm_ops = {
1509 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1510 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1511 sysc_runtime_resume,
1515 /* Module revision register based quirks */
1516 struct sysc_revision_quirk {
1527 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1528 optrev_val, optrevmask, optquirkmask) \
1530 .name = (optname), \
1531 .base = (optbase), \
1532 .rev_offset = (optrev), \
1533 .sysc_offset = (optsysc), \
1534 .syss_offset = (optsyss), \
1535 .revision = (optrev_val), \
1536 .revision_mask = (optrevmask), \
1537 .quirks = (optquirkmask), \
1540 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1541 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1542 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1543 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1544 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1545 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1546 /* Uarts on omap4 and later */
1547 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1548 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1549 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1550 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1552 /* Quirks that need to be set based on the module address */
1553 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1554 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1555 SYSC_QUIRK_SWSUP_SIDLE),
1557 /* Quirks that need to be set based on detected module */
1558 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1559 SYSC_MODULE_QUIRK_AESS),
1560 /* Errata i893 handling for dra7 dcan1 and 2 */
1561 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1562 SYSC_QUIRK_CLKDM_NOAUTO),
1563 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1564 SYSC_QUIRK_CLKDM_NOAUTO),
1565 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1566 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1567 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1568 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1569 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1570 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1571 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1572 SYSC_QUIRK_CLKDM_NOAUTO),
1573 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1574 SYSC_QUIRK_CLKDM_NOAUTO),
1575 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1576 SYSC_QUIRK_OPT_CLKS_IN_RESET),
1577 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1578 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST |
1579 SYSC_QUIRK_GPMC_DEBUG),
1580 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1581 SYSC_QUIRK_OPT_CLKS_NEEDED),
1582 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1583 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1584 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1585 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1586 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1587 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1588 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1589 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1590 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1591 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1592 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1593 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1594 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1595 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1596 SYSC_MODULE_QUIRK_SGX),
1597 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1598 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1599 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1600 SYSC_QUIRK_SWSUP_SIDLE),
1601 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1602 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1603 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1604 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1605 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1606 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1607 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1608 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1609 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1610 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1611 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1612 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1613 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1614 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1615 SYSC_MODULE_QUIRK_OTG),
1616 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1617 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1618 SYSC_QUIRK_REINIT_ON_CTX_LOST),
1619 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1620 SYSC_MODULE_QUIRK_WDT),
1621 /* PRUSS on am3, am4 and am5 */
1622 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1623 SYSC_MODULE_QUIRK_PRUSS),
1624 /* Watchdog on am3 and am4 */
1625 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1626 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1629 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1630 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1631 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1632 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1633 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1635 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1636 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1637 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1638 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1639 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1640 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1641 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1642 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1643 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1644 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1645 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1646 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1647 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1648 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1649 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1650 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1651 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1652 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1653 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1654 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1655 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1656 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1657 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1658 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1659 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1660 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1661 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1662 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1663 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1664 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1665 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1666 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1667 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1668 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1669 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1670 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1671 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1672 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1673 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1674 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1675 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1676 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1677 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1678 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1679 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1680 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1681 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1682 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1683 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0),
1684 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1685 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1686 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1687 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1688 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1689 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1690 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1691 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1692 /* Some timers on omap4 and later */
1693 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1694 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1695 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1696 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1697 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1698 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1699 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1700 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1701 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1702 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1707 * Early quirks based on module base and register offsets only that are
1708 * needed before the module revision can be read
1710 static void sysc_init_early_quirks(struct sysc *ddata)
1712 const struct sysc_revision_quirk *q;
1715 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1716 q = &sysc_revision_quirks[i];
1721 if (q->base != ddata->module_pa)
1724 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1727 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1730 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1733 ddata->name = q->name;
1734 ddata->cfg.quirks |= q->quirks;
1738 /* Quirks that also consider the revision register value */
1739 static void sysc_init_revision_quirks(struct sysc *ddata)
1741 const struct sysc_revision_quirk *q;
1744 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1745 q = &sysc_revision_quirks[i];
1747 if (q->base && q->base != ddata->module_pa)
1750 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1753 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1756 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1759 if (q->revision == ddata->revision ||
1760 (q->revision & q->revision_mask) ==
1761 (ddata->revision & q->revision_mask)) {
1762 ddata->name = q->name;
1763 ddata->cfg.quirks |= q->quirks;
1769 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1770 * enabled DSS interrupts. Eventually we may be able to do this on
1771 * dispc init rather than top-level DSS init.
1773 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1776 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1777 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1779 bool framedonetv_irq = true;
1780 u32 val, irq_mask = 0;
1782 switch (sysc_soc->soc) {
1783 case SOC_2420 ... SOC_3630:
1785 framedonetv_irq = false;
1787 case SOC_4430 ... SOC_4470:
1796 framedonetv_irq = false;
1803 /* Remap the whole module range to be able to reset dispc outputs */
1804 devm_iounmap(ddata->dev, ddata->module_va);
1805 ddata->module_va = devm_ioremap(ddata->dev,
1807 ddata->module_size);
1808 if (!ddata->module_va)
1811 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */
1812 val = sysc_read(ddata, dispc_offset + 0x40);
1813 lcd_en = val & lcd_en_mask;
1814 digit_en = val & digit_en_mask;
1816 irq_mask |= BIT(0); /* FRAMEDONE */
1818 if (framedonetv_irq)
1819 irq_mask |= BIT(24); /* FRAMEDONETV */
1821 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1823 if (disable && (lcd_en || digit_en))
1824 sysc_write(ddata, dispc_offset + 0x40,
1825 val & ~(lcd_en_mask | digit_en_mask));
1827 if (manager_count <= 2)
1830 /* DISPC_CONTROL2 */
1831 val = sysc_read(ddata, dispc_offset + 0x238);
1832 lcd2_en = val & lcd_en_mask;
1834 irq_mask |= BIT(22); /* FRAMEDONE2 */
1835 if (disable && lcd2_en)
1836 sysc_write(ddata, dispc_offset + 0x238,
1837 val & ~lcd_en_mask);
1839 if (manager_count <= 3)
1842 /* DISPC_CONTROL3 */
1843 val = sysc_read(ddata, dispc_offset + 0x848);
1844 lcd3_en = val & lcd_en_mask;
1846 irq_mask |= BIT(30); /* FRAMEDONE3 */
1847 if (disable && lcd3_en)
1848 sysc_write(ddata, dispc_offset + 0x848,
1849 val & ~lcd_en_mask);
1854 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1855 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1857 const int dispc_offset = 0x1000;
1861 /* Get enabled outputs */
1862 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1866 /* Clear IRQSTATUS */
1867 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1869 /* Disable outputs */
1870 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1872 /* Poll IRQSTATUS */
1873 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1874 val, val != irq_mask, 100, 50);
1876 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1877 __func__, val, irq_mask);
1879 if (sysc_soc->soc == SOC_3430) {
1880 /* Clear DSS_SDI_CONTROL */
1881 sysc_write(ddata, 0x44, 0);
1883 /* Clear DSS_PLL_CONTROL */
1884 sysc_write(ddata, 0x48, 0);
1887 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1888 sysc_write(ddata, 0x40, 0);
1891 /* 1-wire needs module's internal clocks enabled for reset */
1892 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1894 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1897 val = sysc_read(ddata, offset);
1899 sysc_write(ddata, offset, val);
1902 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1903 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1905 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1907 sysc_write(ddata, offset, 1);
1910 /* I2C needs to be disabled for reset */
1911 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1916 /* I2C_CON, omap2/3 is different from omap4 and later */
1917 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1923 val = sysc_read(ddata, offset);
1928 sysc_write(ddata, offset, val);
1931 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1933 sysc_clk_quirk_i2c(ddata, false);
1936 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1938 sysc_clk_quirk_i2c(ddata, true);
1941 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1942 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1944 u32 val, kick0_val = 0, kick1_val = 0;
1945 unsigned long flags;
1949 kick0_val = 0x83e70b13;
1950 kick1_val = 0x95a4f1e0;
1953 local_irq_save(flags);
1954 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1955 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1956 !(val & BIT(0)), 100, 50);
1958 dev_warn(ddata->dev, "rtc busy timeout\n");
1959 /* Now we have ~15 microseconds to read/write various registers */
1960 sysc_write(ddata, 0x6c, kick0_val);
1961 sysc_write(ddata, 0x70, kick1_val);
1962 local_irq_restore(flags);
1965 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1967 sysc_quirk_rtc(ddata, false);
1970 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1972 sysc_quirk_rtc(ddata, true);
1975 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */
1976 static void sysc_module_enable_quirk_otg(struct sysc *ddata)
1978 int offset = 0x414; /* OTG_FORCESTDBY */
1980 sysc_write(ddata, offset, 0);
1983 static void sysc_module_disable_quirk_otg(struct sysc *ddata)
1985 int offset = 0x414; /* OTG_FORCESTDBY */
1986 u32 val = BIT(0); /* ENABLEFORCE */
1988 sysc_write(ddata, offset, val);
1991 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1992 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1994 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1995 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1997 sysc_write(ddata, offset, val);
2000 /* Watchdog timer needs a disable sequence after reset */
2001 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
2003 int wps, spr, error;
2009 sysc_write(ddata, spr, 0xaaaa);
2010 error = readl_poll_timeout(ddata->module_va + wps, val,
2012 MAX_MODULE_SOFTRESET_WAIT);
2014 dev_warn(ddata->dev, "wdt disable step1 failed\n");
2016 sysc_write(ddata, spr, 0x5555);
2017 error = readl_poll_timeout(ddata->module_va + wps, val,
2019 MAX_MODULE_SOFTRESET_WAIT);
2021 dev_warn(ddata->dev, "wdt disable step2 failed\n");
2024 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
2025 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
2029 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2030 reg |= SYSC_PRUSS_STANDBY_INIT;
2031 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2034 static void sysc_init_module_quirks(struct sysc *ddata)
2036 if (ddata->legacy_mode || !ddata->name)
2039 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
2040 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
2045 #ifdef CONFIG_OMAP_GPMC_DEBUG
2046 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2047 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
2053 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2054 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2055 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2060 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2061 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2063 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2064 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2066 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2067 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2068 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2073 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) {
2074 ddata->module_enable_quirk = sysc_module_enable_quirk_otg;
2075 ddata->module_disable_quirk = sysc_module_disable_quirk_otg;
2078 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2079 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2081 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2082 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2083 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2086 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2087 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2090 static int sysc_clockdomain_init(struct sysc *ddata)
2092 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2093 struct clk *fck = NULL, *ick = NULL;
2096 if (!pdata || !pdata->init_clockdomain)
2099 switch (ddata->nr_clocks) {
2101 ick = ddata->clocks[SYSC_ICK];
2104 fck = ddata->clocks[SYSC_FCK];
2110 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2111 if (!error || error == -ENODEV)
2118 * Note that pdata->init_module() typically does a reset first. After
2119 * pdata->init_module() is done, PM runtime can be used for the interconnect
2122 static int sysc_legacy_init(struct sysc *ddata)
2124 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2127 if (!pdata || !pdata->init_module)
2130 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2131 if (error == -EEXIST)
2138 * Note that the caller must ensure the interconnect target module is enabled
2139 * before calling reset. Otherwise reset will not complete.
2141 static int sysc_reset(struct sysc *ddata)
2143 int sysc_offset, sysc_val, error;
2146 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2148 if (ddata->legacy_mode ||
2149 ddata->cap->regbits->srst_shift < 0 ||
2150 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2153 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2155 if (ddata->pre_reset_quirk)
2156 ddata->pre_reset_quirk(ddata);
2158 if (sysc_offset >= 0) {
2159 sysc_val = sysc_read_sysconfig(ddata);
2160 sysc_val |= sysc_mask;
2161 sysc_write(ddata, sysc_offset, sysc_val);
2162 /* Flush posted write */
2163 sysc_val = sysc_read_sysconfig(ddata);
2166 if (ddata->cfg.srst_udelay)
2167 usleep_range(ddata->cfg.srst_udelay,
2168 ddata->cfg.srst_udelay * 2);
2170 if (ddata->post_reset_quirk)
2171 ddata->post_reset_quirk(ddata);
2173 error = sysc_wait_softreset(ddata);
2175 dev_warn(ddata->dev, "OCP softreset timed out\n");
2177 if (ddata->reset_done_quirk)
2178 ddata->reset_done_quirk(ddata);
2184 * At this point the module is configured enough to read the revision but
2185 * module may not be completely configured yet to use PM runtime. Enable
2186 * all clocks directly during init to configure the quirks needed for PM
2187 * runtime based on the revision register.
2189 static int sysc_init_module(struct sysc *ddata)
2191 bool rstctrl_deasserted = false;
2194 error = sysc_clockdomain_init(ddata);
2198 sysc_clkdm_deny_idle(ddata);
2201 * Always enable clocks. The bootloader may or may not have enabled
2202 * the related clocks.
2204 error = sysc_enable_opt_clocks(ddata);
2208 error = sysc_enable_main_clocks(ddata);
2210 goto err_opt_clocks;
2212 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2213 error = reset_control_deassert(ddata->rsts);
2215 goto err_main_clocks;
2216 rstctrl_deasserted = true;
2219 ddata->revision = sysc_read_revision(ddata);
2220 sysc_init_revision_quirks(ddata);
2221 sysc_init_module_quirks(ddata);
2223 if (ddata->legacy_mode) {
2224 error = sysc_legacy_init(ddata);
2226 goto err_main_clocks;
2229 if (!ddata->legacy_mode) {
2230 error = sysc_enable_module(ddata->dev);
2232 goto err_main_clocks;
2235 error = sysc_reset(ddata);
2237 dev_err(ddata->dev, "Reset failed with %d\n", error);
2239 if (error && !ddata->legacy_mode)
2240 sysc_disable_module(ddata->dev);
2244 sysc_disable_main_clocks(ddata);
2246 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2248 sysc_disable_opt_clocks(ddata);
2249 sysc_clkdm_allow_idle(ddata);
2252 if (error && rstctrl_deasserted &&
2253 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2254 reset_control_assert(ddata->rsts);
2259 static int sysc_init_sysc_mask(struct sysc *ddata)
2261 struct device_node *np = ddata->dev->of_node;
2265 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2269 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2274 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2277 struct device_node *np = ddata->dev->of_node;
2278 struct property *prop;
2282 of_property_for_each_u32(np, name, prop, p, val) {
2283 if (val >= SYSC_NR_IDLEMODES) {
2284 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2287 *idlemodes |= (1 << val);
2293 static int sysc_init_idlemodes(struct sysc *ddata)
2297 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2302 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2311 * Only some devices on omap4 and later have SYSCONFIG reset done
2312 * bit. We can detect this if there is no SYSSTATUS at all, or the
2313 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2314 * have multiple bits for the child devices like OHCI and EHCI.
2315 * Depends on SYSC being parsed first.
2317 static int sysc_init_syss_mask(struct sysc *ddata)
2319 struct device_node *np = ddata->dev->of_node;
2323 error = of_property_read_u32(np, "ti,syss-mask", &val);
2325 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2326 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2327 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2328 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2333 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2334 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2336 ddata->cfg.syss_mask = val;
2342 * Many child device drivers need to have fck and opt clocks available
2343 * to get the clock rate for device internal configuration etc.
2345 static int sysc_child_add_named_clock(struct sysc *ddata,
2346 struct device *child,
2350 struct clk_lookup *l;
2356 clk = clk_get(child, name);
2362 clk = clk_get(ddata->dev, name);
2366 l = clkdev_create(clk, name, dev_name(child));
2375 static int sysc_child_add_clocks(struct sysc *ddata,
2376 struct device *child)
2380 for (i = 0; i < ddata->nr_clocks; i++) {
2381 error = sysc_child_add_named_clock(ddata,
2383 ddata->clock_roles[i]);
2384 if (error && error != -EEXIST) {
2385 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2386 ddata->clock_roles[i], error);
2395 static struct device_type sysc_device_type = {
2398 static struct sysc *sysc_child_to_parent(struct device *dev)
2400 struct device *parent = dev->parent;
2402 if (!parent || parent->type != &sysc_device_type)
2405 return dev_get_drvdata(parent);
2408 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2413 ddata = sysc_child_to_parent(dev);
2415 error = pm_generic_runtime_suspend(dev);
2419 if (!ddata->enabled)
2422 return sysc_runtime_suspend(ddata->dev);
2425 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2430 ddata = sysc_child_to_parent(dev);
2432 if (!ddata->enabled) {
2433 error = sysc_runtime_resume(ddata->dev);
2436 "%s error: %i\n", __func__, error);
2439 return pm_generic_runtime_resume(dev);
2442 #ifdef CONFIG_PM_SLEEP
2443 static int sysc_child_suspend_noirq(struct device *dev)
2448 ddata = sysc_child_to_parent(dev);
2450 dev_dbg(ddata->dev, "%s %s\n", __func__,
2451 ddata->name ? ddata->name : "");
2453 error = pm_generic_suspend_noirq(dev);
2455 dev_err(dev, "%s error at %i: %i\n",
2456 __func__, __LINE__, error);
2461 if (!pm_runtime_status_suspended(dev)) {
2462 error = pm_generic_runtime_suspend(dev);
2464 dev_dbg(dev, "%s busy at %i: %i\n",
2465 __func__, __LINE__, error);
2470 error = sysc_runtime_suspend(ddata->dev);
2472 dev_err(dev, "%s error at %i: %i\n",
2473 __func__, __LINE__, error);
2478 ddata->child_needs_resume = true;
2484 static int sysc_child_resume_noirq(struct device *dev)
2489 ddata = sysc_child_to_parent(dev);
2491 dev_dbg(ddata->dev, "%s %s\n", __func__,
2492 ddata->name ? ddata->name : "");
2494 if (ddata->child_needs_resume) {
2495 ddata->child_needs_resume = false;
2497 error = sysc_runtime_resume(ddata->dev);
2500 "%s runtime resume error: %i\n",
2503 error = pm_generic_runtime_resume(dev);
2506 "%s generic runtime resume: %i\n",
2510 return pm_generic_resume_noirq(dev);
2514 static struct dev_pm_domain sysc_child_pm_domain = {
2516 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2517 sysc_child_runtime_resume,
2519 USE_PLATFORM_PM_SLEEP_OPS
2520 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2521 sysc_child_resume_noirq)
2525 /* Caller needs to take list_lock if ever used outside of cpu_pm */
2526 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2528 struct sysc_module *module;
2529 struct list_head *pos;
2532 list_for_each(pos, &sysc_soc->restored_modules) {
2533 module = list_entry(pos, struct sysc_module, node);
2534 ddata = module->ddata;
2535 sysc_reinit_module(ddata, ddata->enabled);
2540 * sysc_context_notifier - optionally reset and restore module after idle
2541 * @nb: notifier block
2545 * Some interconnect target modules need to be restored, or reset and restored
2546 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2547 * OTG and GPMC target modules even if the modules are unused.
2549 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2552 struct sysc_soc_info *soc;
2554 soc = container_of(nb, struct sysc_soc_info, nb);
2557 case CPU_CLUSTER_PM_ENTER:
2559 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2561 case CPU_CLUSTER_PM_EXIT:
2562 sysc_reinit_modules(soc);
2570 * sysc_add_restored - optionally add reset and restore quirk hanlling
2571 * @ddata: device data
2573 static void sysc_add_restored(struct sysc *ddata)
2575 struct sysc_module *restored_module;
2577 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2578 if (!restored_module)
2581 restored_module->ddata = ddata;
2583 mutex_lock(&sysc_soc->list_lock);
2585 list_add(&restored_module->node, &sysc_soc->restored_modules);
2587 if (sysc_soc->nb.notifier_call)
2590 sysc_soc->nb.notifier_call = sysc_context_notifier;
2591 cpu_pm_register_notifier(&sysc_soc->nb);
2594 mutex_unlock(&sysc_soc->list_lock);
2598 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2599 * @ddata: device driver data
2600 * @child: child device driver
2602 * Allow idle for child devices as done with _od_runtime_suspend().
2603 * Otherwise many child devices will not idle because of the permanent
2604 * parent usecount set in pm_runtime_irq_safe().
2606 * Note that the long term solution is to just modify the child device
2607 * drivers to not set pm_runtime_irq_safe() and then this can be just
2610 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2612 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2613 dev_pm_domain_set(child, &sysc_child_pm_domain);
2616 static int sysc_notifier_call(struct notifier_block *nb,
2617 unsigned long event, void *device)
2619 struct device *dev = device;
2623 ddata = sysc_child_to_parent(dev);
2628 case BUS_NOTIFY_ADD_DEVICE:
2629 error = sysc_child_add_clocks(ddata, dev);
2632 sysc_legacy_idle_quirk(ddata, dev);
2641 static struct notifier_block sysc_nb = {
2642 .notifier_call = sysc_notifier_call,
2645 /* Device tree configured quirks */
2646 struct sysc_dts_quirk {
2651 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2652 { .name = "ti,no-idle-on-init",
2653 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2654 { .name = "ti,no-reset-on-init",
2655 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2656 { .name = "ti,no-idle",
2657 .mask = SYSC_QUIRK_NO_IDLE, },
2660 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2663 const struct property *prop;
2666 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2667 const char *name = sysc_dts_quirks[i].name;
2669 prop = of_get_property(np, name, &len);
2673 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2675 dev_warn(ddata->dev,
2676 "dts flag should be at module level for %s\n",
2682 static int sysc_init_dts_quirks(struct sysc *ddata)
2684 struct device_node *np = ddata->dev->of_node;
2688 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2690 sysc_parse_dts_quirks(ddata, np, false);
2691 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2694 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2698 ddata->cfg.srst_udelay = (u8)val;
2704 static void sysc_unprepare(struct sysc *ddata)
2711 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2712 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2713 clk_unprepare(ddata->clocks[i]);
2718 * Common sysc register bits found on omap2, also known as type1
2720 static const struct sysc_regbits sysc_regbits_omap2 = {
2721 .dmadisable_shift = -ENODEV,
2728 .autoidle_shift = 0,
2731 static const struct sysc_capabilities sysc_omap2 = {
2732 .type = TI_SYSC_OMAP2,
2733 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2734 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2735 SYSC_OMAP2_AUTOIDLE,
2736 .regbits = &sysc_regbits_omap2,
2739 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2740 static const struct sysc_capabilities sysc_omap2_timer = {
2741 .type = TI_SYSC_OMAP2_TIMER,
2742 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2743 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2744 SYSC_OMAP2_AUTOIDLE,
2745 .regbits = &sysc_regbits_omap2,
2746 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2750 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2751 * with different sidle position
2753 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2754 .dmadisable_shift = -ENODEV,
2755 .midle_shift = -ENODEV,
2757 .clkact_shift = -ENODEV,
2758 .enwkup_shift = -ENODEV,
2760 .autoidle_shift = 0,
2761 .emufree_shift = -ENODEV,
2764 static const struct sysc_capabilities sysc_omap3_sham = {
2765 .type = TI_SYSC_OMAP3_SHAM,
2766 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2767 .regbits = &sysc_regbits_omap3_sham,
2771 * AES register bits found on omap3 and later, a variant of
2772 * sysc_regbits_omap2 with different sidle position
2774 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2775 .dmadisable_shift = -ENODEV,
2776 .midle_shift = -ENODEV,
2778 .clkact_shift = -ENODEV,
2779 .enwkup_shift = -ENODEV,
2781 .autoidle_shift = 0,
2782 .emufree_shift = -ENODEV,
2785 static const struct sysc_capabilities sysc_omap3_aes = {
2786 .type = TI_SYSC_OMAP3_AES,
2787 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2788 .regbits = &sysc_regbits_omap3_aes,
2792 * Common sysc register bits found on omap4, also known as type2
2794 static const struct sysc_regbits sysc_regbits_omap4 = {
2795 .dmadisable_shift = 16,
2798 .clkact_shift = -ENODEV,
2799 .enwkup_shift = -ENODEV,
2802 .autoidle_shift = -ENODEV,
2805 static const struct sysc_capabilities sysc_omap4 = {
2806 .type = TI_SYSC_OMAP4,
2807 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2808 SYSC_OMAP4_SOFTRESET,
2809 .regbits = &sysc_regbits_omap4,
2812 static const struct sysc_capabilities sysc_omap4_timer = {
2813 .type = TI_SYSC_OMAP4_TIMER,
2814 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2815 SYSC_OMAP4_SOFTRESET,
2816 .regbits = &sysc_regbits_omap4,
2820 * Common sysc register bits found on omap4, also known as type3
2822 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2823 .dmadisable_shift = -ENODEV,
2826 .clkact_shift = -ENODEV,
2827 .enwkup_shift = -ENODEV,
2828 .srst_shift = -ENODEV,
2829 .emufree_shift = -ENODEV,
2830 .autoidle_shift = -ENODEV,
2833 static const struct sysc_capabilities sysc_omap4_simple = {
2834 .type = TI_SYSC_OMAP4_SIMPLE,
2835 .regbits = &sysc_regbits_omap4_simple,
2839 * SmartReflex sysc found on omap34xx
2841 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2842 .dmadisable_shift = -ENODEV,
2843 .midle_shift = -ENODEV,
2844 .sidle_shift = -ENODEV,
2846 .enwkup_shift = -ENODEV,
2847 .srst_shift = -ENODEV,
2848 .emufree_shift = -ENODEV,
2849 .autoidle_shift = -ENODEV,
2852 static const struct sysc_capabilities sysc_34xx_sr = {
2853 .type = TI_SYSC_OMAP34XX_SR,
2854 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2855 .regbits = &sysc_regbits_omap34xx_sr,
2856 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2857 SYSC_QUIRK_LEGACY_IDLE,
2861 * SmartReflex sysc found on omap36xx and later
2863 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2864 .dmadisable_shift = -ENODEV,
2865 .midle_shift = -ENODEV,
2867 .clkact_shift = -ENODEV,
2869 .srst_shift = -ENODEV,
2870 .emufree_shift = -ENODEV,
2871 .autoidle_shift = -ENODEV,
2874 static const struct sysc_capabilities sysc_36xx_sr = {
2875 .type = TI_SYSC_OMAP36XX_SR,
2876 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2877 .regbits = &sysc_regbits_omap36xx_sr,
2878 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2881 static const struct sysc_capabilities sysc_omap4_sr = {
2882 .type = TI_SYSC_OMAP4_SR,
2883 .regbits = &sysc_regbits_omap36xx_sr,
2884 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2888 * McASP register bits found on omap4 and later
2890 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2891 .dmadisable_shift = -ENODEV,
2892 .midle_shift = -ENODEV,
2894 .clkact_shift = -ENODEV,
2895 .enwkup_shift = -ENODEV,
2896 .srst_shift = -ENODEV,
2897 .emufree_shift = -ENODEV,
2898 .autoidle_shift = -ENODEV,
2901 static const struct sysc_capabilities sysc_omap4_mcasp = {
2902 .type = TI_SYSC_OMAP4_MCASP,
2903 .regbits = &sysc_regbits_omap4_mcasp,
2904 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2908 * McASP found on dra7 and later
2910 static const struct sysc_capabilities sysc_dra7_mcasp = {
2911 .type = TI_SYSC_OMAP4_SIMPLE,
2912 .regbits = &sysc_regbits_omap4_simple,
2913 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2917 * FS USB host found on omap4 and later
2919 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2920 .dmadisable_shift = -ENODEV,
2921 .midle_shift = -ENODEV,
2923 .clkact_shift = -ENODEV,
2925 .srst_shift = -ENODEV,
2926 .emufree_shift = -ENODEV,
2927 .autoidle_shift = -ENODEV,
2930 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2931 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2932 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2933 .regbits = &sysc_regbits_omap4_usb_host_fs,
2936 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2937 .dmadisable_shift = -ENODEV,
2938 .midle_shift = -ENODEV,
2939 .sidle_shift = -ENODEV,
2940 .clkact_shift = -ENODEV,
2943 .emufree_shift = -ENODEV,
2944 .autoidle_shift = -ENODEV,
2947 static const struct sysc_capabilities sysc_dra7_mcan = {
2948 .type = TI_SYSC_DRA7_MCAN,
2949 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2950 .regbits = &sysc_regbits_dra7_mcan,
2951 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2955 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2957 static const struct sysc_capabilities sysc_pruss = {
2958 .type = TI_SYSC_PRUSS,
2959 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2960 .regbits = &sysc_regbits_omap4_simple,
2961 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2964 static int sysc_init_pdata(struct sysc *ddata)
2966 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2967 struct ti_sysc_module_data *mdata;
2972 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2976 if (ddata->legacy_mode) {
2977 mdata->name = ddata->legacy_mode;
2978 mdata->module_pa = ddata->module_pa;
2979 mdata->module_size = ddata->module_size;
2980 mdata->offsets = ddata->offsets;
2981 mdata->nr_offsets = SYSC_MAX_REGS;
2982 mdata->cap = ddata->cap;
2983 mdata->cfg = &ddata->cfg;
2986 ddata->mdata = mdata;
2991 static int sysc_init_match(struct sysc *ddata)
2993 const struct sysc_capabilities *cap;
2995 cap = of_device_get_match_data(ddata->dev);
3001 ddata->cfg.quirks |= ddata->cap->mod_quirks;
3006 static void ti_sysc_idle(struct work_struct *work)
3010 ddata = container_of(work, struct sysc, idle_work.work);
3013 * One time decrement of clock usage counts if left on from init.
3014 * Note that we disable opt clocks unconditionally in this case
3015 * as they are enabled unconditionally during init without
3016 * considering sysc_opt_clks_needed() at that point.
3018 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3019 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
3020 sysc_disable_main_clocks(ddata);
3021 sysc_disable_opt_clocks(ddata);
3022 sysc_clkdm_allow_idle(ddata);
3025 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
3026 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
3030 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
3031 * and SYSC_QUIRK_NO_RESET_ON_INIT
3033 if (pm_runtime_active(ddata->dev))
3034 pm_runtime_put_sync(ddata->dev);
3038 * SoC model and features detection. Only needed for SoCs that need
3039 * special handling for quirks, no need to list others.
3041 static const struct soc_device_attribute sysc_soc_match[] = {
3042 SOC_FLAG("OMAP242*", SOC_2420),
3043 SOC_FLAG("OMAP243*", SOC_2430),
3044 SOC_FLAG("OMAP3[45]*", SOC_3430),
3045 SOC_FLAG("OMAP3[67]*", SOC_3630),
3046 SOC_FLAG("OMAP443*", SOC_4430),
3047 SOC_FLAG("OMAP446*", SOC_4460),
3048 SOC_FLAG("OMAP447*", SOC_4470),
3049 SOC_FLAG("OMAP54*", SOC_5430),
3050 SOC_FLAG("AM433", SOC_AM3),
3051 SOC_FLAG("AM43*", SOC_AM4),
3052 SOC_FLAG("DRA7*", SOC_DRA7),
3058 * List of SoCs variants with disabled features. By default we assume all
3059 * devices in the device tree are available so no need to list those SoCs.
3061 static const struct soc_device_attribute sysc_soc_feat_match[] = {
3062 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
3063 SOC_FLAG("AM3505", DIS_SGX),
3064 SOC_FLAG("OMAP3525", DIS_SGX),
3065 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
3066 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
3068 /* OMAP3630/DM3730 variants with some accelerators disabled */
3069 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
3070 SOC_FLAG("DM3725", DIS_SGX),
3071 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
3072 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
3073 SOC_FLAG("OMAP3621", DIS_ISP),
3078 static int sysc_add_disabled(unsigned long base)
3080 struct sysc_address *disabled_module;
3082 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
3083 if (!disabled_module)
3086 disabled_module->base = base;
3088 mutex_lock(&sysc_soc->list_lock);
3089 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3090 mutex_unlock(&sysc_soc->list_lock);
3096 * One time init to detect the booted SoC, disable unavailable features
3097 * and initialize list for optional cpu_pm notifier.
3099 * Note that we initialize static data shared across all ti-sysc instances
3100 * so ddata is only used for SoC type. This can be called from module_init
3101 * once we no longer need to rely on platform data.
3103 static int sysc_init_static_data(struct sysc *ddata)
3105 const struct soc_device_attribute *match;
3106 struct ti_sysc_platform_data *pdata;
3107 unsigned long features = 0;
3108 struct device_node *np;
3113 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3117 mutex_init(&sysc_soc->list_lock);
3118 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3119 INIT_LIST_HEAD(&sysc_soc->restored_modules);
3120 sysc_soc->general_purpose = true;
3122 pdata = dev_get_platdata(ddata->dev);
3123 if (pdata && pdata->soc_type_gp)
3124 sysc_soc->general_purpose = pdata->soc_type_gp();
3126 match = soc_device_match(sysc_soc_match);
3127 if (match && match->data)
3128 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3131 * Check and warn about possible old incomplete dtb. We now want to see
3132 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3134 switch (sysc_soc->soc) {
3137 case SOC_4430 ... SOC_4470:
3140 np = of_find_node_by_path("/ocp");
3141 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3142 "ti-sysc: Incomplete old dtb, please update\n");
3148 /* Ignore devices that are not available on HS and EMU SoCs */
3149 if (!sysc_soc->general_purpose) {
3150 switch (sysc_soc->soc) {
3151 case SOC_3430 ... SOC_3630:
3152 sysc_add_disabled(0x48304000); /* timer12 */
3155 sysc_add_disabled(0x48310000); /* rng */
3162 match = soc_device_match(sysc_soc_feat_match);
3167 features = (unsigned long)match->data;
3170 * Add disabled devices to the list based on the module base.
3171 * Note that this must be done before we attempt to access the
3172 * device and have module revision checks working.
3174 if (features & DIS_ISP)
3175 sysc_add_disabled(0x480bd400);
3176 if (features & DIS_IVA)
3177 sysc_add_disabled(0x5d000000);
3178 if (features & DIS_SGX)
3179 sysc_add_disabled(0x50000000);
3184 static void sysc_cleanup_static_data(void)
3186 struct sysc_module *restored_module;
3187 struct sysc_address *disabled_module;
3188 struct list_head *pos, *tmp;
3193 if (sysc_soc->nb.notifier_call)
3194 cpu_pm_unregister_notifier(&sysc_soc->nb);
3196 mutex_lock(&sysc_soc->list_lock);
3197 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3198 restored_module = list_entry(pos, struct sysc_module, node);
3200 kfree(restored_module);
3202 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3203 disabled_module = list_entry(pos, struct sysc_address, node);
3205 kfree(disabled_module);
3207 mutex_unlock(&sysc_soc->list_lock);
3210 static int sysc_check_disabled_devices(struct sysc *ddata)
3212 struct sysc_address *disabled_module;
3213 struct list_head *pos;
3216 mutex_lock(&sysc_soc->list_lock);
3217 list_for_each(pos, &sysc_soc->disabled_modules) {
3218 disabled_module = list_entry(pos, struct sysc_address, node);
3219 if (ddata->module_pa == disabled_module->base) {
3220 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3225 mutex_unlock(&sysc_soc->list_lock);
3231 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3232 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3233 * are needed, we could also look at the timer register configuration.
3235 static int sysc_check_active_timer(struct sysc *ddata)
3239 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3240 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3244 * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3245 * Revision C and later are fixed with commit 23885389dbbb ("ARM:
3246 * dts: Fix timer regression for beagleboard revision c"). This all
3247 * can be dropped if we stop supporting old beagleboard revisions
3248 * A to B4 at some point.
3250 if (sysc_soc->soc == SOC_3430)
3255 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3256 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3262 static const struct of_device_id sysc_match_table[] = {
3263 { .compatible = "simple-bus", },
3267 static int sysc_probe(struct platform_device *pdev)
3269 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3273 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3277 ddata->offsets[SYSC_REVISION] = -ENODEV;
3278 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3279 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3280 ddata->dev = &pdev->dev;
3281 platform_set_drvdata(pdev, ddata);
3283 error = sysc_init_static_data(ddata);
3287 error = sysc_init_match(ddata);
3291 error = sysc_init_dts_quirks(ddata);
3295 error = sysc_map_and_check_registers(ddata);
3299 error = sysc_init_sysc_mask(ddata);
3303 error = sysc_init_idlemodes(ddata);
3307 error = sysc_init_syss_mask(ddata);
3311 error = sysc_init_pdata(ddata);
3315 sysc_init_early_quirks(ddata);
3317 error = sysc_check_disabled_devices(ddata);
3321 error = sysc_check_active_timer(ddata);
3322 if (error == -ENXIO)
3323 ddata->reserved = true;
3327 error = sysc_get_clocks(ddata);
3331 error = sysc_init_resets(ddata);
3335 error = sysc_init_module(ddata);
3339 pm_runtime_enable(ddata->dev);
3340 error = pm_runtime_resume_and_get(ddata->dev);
3342 pm_runtime_disable(ddata->dev);
3346 /* Balance use counts as PM runtime should have enabled these all */
3347 if (!(ddata->cfg.quirks &
3348 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3349 sysc_disable_main_clocks(ddata);
3350 sysc_disable_opt_clocks(ddata);
3351 sysc_clkdm_allow_idle(ddata);
3354 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3355 reset_control_assert(ddata->rsts);
3357 sysc_show_registers(ddata);
3359 ddata->dev->type = &sysc_device_type;
3361 if (!ddata->reserved) {
3362 error = of_platform_populate(ddata->dev->of_node,
3364 pdata ? pdata->auxdata : NULL,
3370 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3372 /* At least earlycon won't survive without deferred idle */
3373 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3374 SYSC_QUIRK_NO_IDLE_ON_INIT |
3375 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3376 schedule_delayed_work(&ddata->idle_work, 3000);
3378 pm_runtime_put(&pdev->dev);
3381 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3382 sysc_add_restored(ddata);
3387 pm_runtime_put_sync(&pdev->dev);
3388 pm_runtime_disable(&pdev->dev);
3390 sysc_unprepare(ddata);
3395 static int sysc_remove(struct platform_device *pdev)
3397 struct sysc *ddata = platform_get_drvdata(pdev);
3400 /* Device can still be enabled, see deferred idle quirk in probe */
3401 if (cancel_delayed_work_sync(&ddata->idle_work))
3402 ti_sysc_idle(&ddata->idle_work.work);
3404 error = pm_runtime_resume_and_get(ddata->dev);
3406 pm_runtime_disable(ddata->dev);
3410 of_platform_depopulate(&pdev->dev);
3412 pm_runtime_put_sync(&pdev->dev);
3413 pm_runtime_disable(&pdev->dev);
3415 if (!reset_control_status(ddata->rsts))
3416 reset_control_assert(ddata->rsts);
3419 sysc_unprepare(ddata);
3424 static const struct of_device_id sysc_match[] = {
3425 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3426 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3427 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3428 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3429 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3430 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3431 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3432 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3433 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3434 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3435 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3436 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3437 { .compatible = "ti,sysc-usb-host-fs",
3438 .data = &sysc_omap4_usb_host_fs, },
3439 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3440 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3443 MODULE_DEVICE_TABLE(of, sysc_match);
3445 static struct platform_driver sysc_driver = {
3446 .probe = sysc_probe,
3447 .remove = sysc_remove,
3450 .of_match_table = sysc_match,
3455 static int __init sysc_init(void)
3457 bus_register_notifier(&platform_bus_type, &sysc_nb);
3459 return platform_driver_register(&sysc_driver);
3461 module_init(sysc_init);
3463 static void __exit sysc_exit(void)
3465 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3466 platform_driver_unregister(&sysc_driver);
3467 sysc_cleanup_static_data();
3469 module_exit(sysc_exit);
3471 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3472 MODULE_LICENSE("GPL v2");