1 // SPDX-License-Identifier: GPL-2.0-only
3 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
4 * 370/XP, Dove, Orion5x and MV78xx0)
6 * The Marvell EBU SoCs have a configurable physical address space:
7 * the physical address at which certain devices (PCIe, NOR, NAND,
8 * etc.) sit can be configured. The configuration takes place through
9 * two sets of registers:
11 * - One to configure the access of the CPU to the devices. Depending
12 * on the families, there are between 8 and 20 configurable windows,
13 * each can be use to create a physical memory window that maps to a
14 * specific device. Devices are identified by a tuple (target,
17 * - One to configure the access to the CPU to the SDRAM. There are
18 * either 2 (for Dove) or 4 (for other families) windows to map the
19 * SDRAM into the physical address space.
23 * - Reads out the SDRAM address decoding windows at initialization
24 * time, and fills the mvebu_mbus_dram_info structure with these
25 * information. The exported function mv_mbus_dram_info() allow
26 * device drivers to get those information related to the SDRAM
27 * address decoding windows. This is because devices also have their
28 * own windows (configured through registers that are part of each
29 * device register space), and therefore the drivers for Marvell
30 * devices have to configure those device -> SDRAM windows to ensure
31 * that DMA works properly.
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
35 * device accesses. This API is mvebu_mbus_add_window_by_id(),
36 * mvebu_mbus_add_window_remap_by_id() and
37 * mvebu_mbus_del_window().
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40 * see the list of CPU -> SDRAM windows and their configuration
41 * (file 'sdram') and the list of CPU -> devices windows and their
42 * configuration (file 'devices').
45 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/init.h>
50 #include <linux/mbus.h>
52 #include <linux/ioport.h>
54 #include <linux/of_address.h>
55 #include <linux/debugfs.h>
56 #include <linux/log2.h>
57 #include <linux/memblock.h>
58 #include <linux/syscore_ops.h>
61 * DDR target is the same on all platforms.
66 * CPU Address Decode Windows registers
68 #define WIN_CTRL_OFF 0x0000
69 #define WIN_CTRL_ENABLE BIT(0)
70 /* Only on HW I/O coherency capable platforms */
71 #define WIN_CTRL_SYNCBARRIER BIT(1)
72 #define WIN_CTRL_TGT_MASK 0xf0
73 #define WIN_CTRL_TGT_SHIFT 4
74 #define WIN_CTRL_ATTR_MASK 0xff00
75 #define WIN_CTRL_ATTR_SHIFT 8
76 #define WIN_CTRL_SIZE_MASK 0xffff0000
77 #define WIN_CTRL_SIZE_SHIFT 16
78 #define WIN_BASE_OFF 0x0004
79 #define WIN_BASE_LOW 0xffff0000
80 #define WIN_BASE_HIGH 0xf
81 #define WIN_REMAP_LO_OFF 0x0008
82 #define WIN_REMAP_LOW 0xffff0000
83 #define WIN_REMAP_HI_OFF 0x000c
85 #define UNIT_SYNC_BARRIER_OFF 0x84
86 #define UNIT_SYNC_BARRIER_ALL 0xFFFF
88 #define ATTR_HW_COHERENCY (0x1 << 4)
90 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
91 #define DDR_BASE_CS_HIGH_MASK 0xf
92 #define DDR_BASE_CS_LOW_MASK 0xff000000
93 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
94 #define DDR_SIZE_ENABLED BIT(0)
95 #define DDR_SIZE_CS_MASK 0x1c
96 #define DDR_SIZE_CS_SHIFT 2
97 #define DDR_SIZE_MASK 0xff000000
99 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
101 /* Relative to mbusbridge_base */
102 #define MBUS_BRIDGE_CTRL_OFF 0x0
103 #define MBUS_BRIDGE_BASE_OFF 0x4
105 /* Maximum number of windows, for all known platforms */
106 #define MBUS_WINS_MAX 20
108 struct mvebu_mbus_state;
110 struct mvebu_mbus_soc_data {
111 unsigned int num_wins;
112 bool has_mbus_bridge;
113 unsigned int (*win_cfg_offset)(const int win);
114 unsigned int (*win_remap_offset)(const int win);
115 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
116 int (*save_cpu_target)(struct mvebu_mbus_state *s,
117 u32 __iomem *store_addr);
118 int (*show_cpu_target)(struct mvebu_mbus_state *s,
119 struct seq_file *seq, void *v);
123 * Used to store the state of one MBus window across suspend/resume.
125 struct mvebu_mbus_win_data {
132 struct mvebu_mbus_state {
133 void __iomem *mbuswins_base;
134 void __iomem *sdramwins_base;
135 void __iomem *mbusbridge_base;
136 phys_addr_t sdramwins_phys_base;
137 struct dentry *debugfs_root;
138 struct dentry *debugfs_sdram;
139 struct dentry *debugfs_devs;
140 struct resource pcie_mem_aperture;
141 struct resource pcie_io_aperture;
142 const struct mvebu_mbus_soc_data *soc;
145 /* Used during suspend/resume */
146 u32 mbus_bridge_ctrl;
147 u32 mbus_bridge_base;
148 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
151 static struct mvebu_mbus_state mbus_state;
154 * We provide two variants of the mv_mbus_dram_info() function:
156 * - The normal one, where the described DRAM ranges may overlap with
157 * the I/O windows, but for which the DRAM ranges are guaranteed to
158 * have a power of two size. Such ranges are suitable for the DMA
159 * masters that only DMA between the RAM and the device, which is
160 * actually all devices except the crypto engines.
162 * - The 'nooverlap' one, where the described DRAM ranges are
163 * guaranteed to not overlap with the I/O windows, but for which the
164 * DRAM ranges will not have power of two sizes. They will only be
165 * aligned on a 64 KB boundary, and have a size multiple of 64
166 * KB. Such ranges are suitable for the DMA masters that DMA between
167 * the crypto SRAM (which is mapped through an I/O window) and a
168 * device. This is the case for the crypto engines.
171 static struct mbus_dram_target_info mvebu_mbus_dram_info;
172 static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
174 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
176 return &mvebu_mbus_dram_info;
178 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
180 const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
182 return &mvebu_mbus_dram_info_nooverlap;
184 EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
186 /* Checks whether the given window has remap capability */
187 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
190 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
194 * Functions to manipulate the address decoding windows
197 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
198 int win, int *enabled, u64 *base,
199 u32 *size, u8 *target, u8 *attr,
202 void __iomem *addr = mbus->mbuswins_base +
203 mbus->soc->win_cfg_offset(win);
204 u32 basereg = readl(addr + WIN_BASE_OFF);
205 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
207 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
213 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
214 *base |= (basereg & WIN_BASE_LOW);
215 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
218 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
221 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
224 if (mvebu_mbus_window_is_remappable(mbus, win)) {
225 u32 remap_low, remap_hi;
226 void __iomem *addr_rmp = mbus->mbuswins_base +
227 mbus->soc->win_remap_offset(win);
228 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
229 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
230 *remap = ((u64)remap_hi << 32) | remap_low;
236 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
241 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
242 writel(0, addr + WIN_BASE_OFF);
243 writel(0, addr + WIN_CTRL_OFF);
245 if (mvebu_mbus_window_is_remappable(mbus, win)) {
246 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
247 writel(0, addr + WIN_REMAP_LO_OFF);
248 writel(0, addr + WIN_REMAP_HI_OFF);
252 /* Checks whether the given window number is available */
254 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
257 void __iomem *addr = mbus->mbuswins_base +
258 mbus->soc->win_cfg_offset(win);
259 u32 ctrl = readl(addr + WIN_CTRL_OFF);
261 return !(ctrl & WIN_CTRL_ENABLE);
265 * Checks whether the given (base, base+size) area doesn't overlap an
268 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
269 phys_addr_t base, size_t size,
272 u64 end = (u64)base + size;
275 for (win = 0; win < mbus->soc->num_wins; win++) {
281 mvebu_mbus_read_window(mbus, win,
282 &enabled, &wbase, &wsize,
283 &wtarget, &wattr, NULL);
288 wend = wbase + wsize;
291 * Check if the current window overlaps with the
292 * proposed physical range
294 if ((u64)base < wend && end > wbase)
301 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
302 phys_addr_t base, size_t size)
306 for (win = 0; win < mbus->soc->num_wins; win++) {
311 mvebu_mbus_read_window(mbus, win,
312 &enabled, &wbase, &wsize,
318 if (base == wbase && size == wsize)
325 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
326 int win, phys_addr_t base, size_t size,
327 phys_addr_t remap, u8 target,
330 void __iomem *addr = mbus->mbuswins_base +
331 mbus->soc->win_cfg_offset(win);
332 u32 ctrl, remap_addr;
334 if (!is_power_of_2(size)) {
335 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
339 if ((base & (phys_addr_t)(size - 1)) != 0) {
340 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
345 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
346 (attr << WIN_CTRL_ATTR_SHIFT) |
347 (target << WIN_CTRL_TGT_SHIFT) |
349 if (mbus->hw_io_coherency)
350 ctrl |= WIN_CTRL_SYNCBARRIER;
352 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
353 writel(ctrl, addr + WIN_CTRL_OFF);
355 if (mvebu_mbus_window_is_remappable(mbus, win)) {
356 void __iomem *addr_rmp = mbus->mbuswins_base +
357 mbus->soc->win_remap_offset(win);
359 if (remap == MVEBU_MBUS_NO_REMAP)
363 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
364 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
370 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
371 phys_addr_t base, size_t size,
372 phys_addr_t remap, u8 target,
377 if (remap == MVEBU_MBUS_NO_REMAP) {
378 for (win = 0; win < mbus->soc->num_wins; win++) {
379 if (mvebu_mbus_window_is_remappable(mbus, win))
382 if (mvebu_mbus_window_is_free(mbus, win))
383 return mvebu_mbus_setup_window(mbus, win, base,
389 for (win = 0; win < mbus->soc->num_wins; win++) {
390 /* Skip window if need remap but is not supported */
391 if ((remap != MVEBU_MBUS_NO_REMAP) &&
392 !mvebu_mbus_window_is_remappable(mbus, win))
395 if (mvebu_mbus_window_is_free(mbus, win))
396 return mvebu_mbus_setup_window(mbus, win, base, size,
397 remap, target, attr);
407 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
408 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
409 struct seq_file *seq, void *v)
413 for (i = 0; i < 4; i++) {
414 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
415 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
419 if (!(sizereg & DDR_SIZE_ENABLED)) {
420 seq_printf(seq, "[%d] disabled\n", i);
424 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
425 base |= basereg & DDR_BASE_CS_LOW_MASK;
426 size = (sizereg | ~DDR_SIZE_MASK);
428 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
429 i, (unsigned long long)base,
430 (unsigned long long)base + size + 1,
431 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
437 /* Special function for Dove */
438 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
439 struct seq_file *seq, void *v)
443 for (i = 0; i < 2; i++) {
444 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
449 seq_printf(seq, "[%d] disabled\n", i);
453 base = map & 0xff800000;
454 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
456 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
457 i, (unsigned long long)base,
458 (unsigned long long)base + size, i);
464 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
466 struct mvebu_mbus_state *mbus = &mbus_state;
467 return mbus->soc->show_cpu_target(mbus, seq, v);
469 DEFINE_SHOW_ATTRIBUTE(mvebu_sdram_debug);
471 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
473 struct mvebu_mbus_state *mbus = &mbus_state;
476 for (win = 0; win < mbus->soc->num_wins; win++) {
482 mvebu_mbus_read_window(mbus, win,
483 &enabled, &wbase, &wsize,
484 &wtarget, &wattr, &wremap);
487 seq_printf(seq, "[%02d] disabled\n", win);
491 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
492 win, (unsigned long long)wbase,
493 (unsigned long long)(wbase + wsize), wtarget, wattr);
495 if (!is_power_of_2(wsize) ||
496 ((wbase & (u64)(wsize - 1)) != 0))
497 seq_puts(seq, " (Invalid base/size!!)");
499 if (mvebu_mbus_window_is_remappable(mbus, win)) {
500 seq_printf(seq, " (remap %016llx)\n",
501 (unsigned long long)wremap);
503 seq_printf(seq, "\n");
508 DEFINE_SHOW_ATTRIBUTE(mvebu_devs_debug);
511 * SoC-specific functions and definitions
514 static unsigned int generic_mbus_win_cfg_offset(int win)
519 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
521 /* The register layout is a bit annoying and the below code
522 * tries to cope with it.
523 * - At offset 0x0, there are the registers for the first 8
524 * windows, with 4 registers of 32 bits per window (ctrl,
525 * base, remap low, remap high)
526 * - Then at offset 0x80, there is a hole of 0x10 bytes for
527 * the internal registers base address and internal units
528 * sync barrier register.
529 * - Then at offset 0x90, there the registers for 12
530 * windows, with only 2 registers of 32 bits per window
536 return 0x90 + ((win - 8) << 3);
539 static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
544 return 0x900 + ((win - 8) << 4);
547 static unsigned int generic_mbus_win_remap_2_offset(int win)
550 return generic_mbus_win_cfg_offset(win);
552 return MVEBU_MBUS_NO_REMAP;
555 static unsigned int generic_mbus_win_remap_4_offset(int win)
558 return generic_mbus_win_cfg_offset(win);
560 return MVEBU_MBUS_NO_REMAP;
563 static unsigned int generic_mbus_win_remap_8_offset(int win)
566 return generic_mbus_win_cfg_offset(win);
568 return MVEBU_MBUS_NO_REMAP;
571 static unsigned int armada_xp_mbus_win_remap_offset(int win)
574 return generic_mbus_win_cfg_offset(win);
576 return 0xF0 - WIN_REMAP_LO_OFF;
578 return MVEBU_MBUS_NO_REMAP;
582 * Use the memblock information to find the MBus bridge hole in the
583 * physical address space.
586 mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
588 phys_addr_t reg_start, reg_end;
591 for_each_mem_range(i, ®_start, ®_end) {
593 * This part of the memory is above 4 GB, so we don't
594 * care for the MBus bridge hole.
596 if ((u64)reg_start >= 0x100000000ULL)
600 * The MBus bridge hole is at the end of the RAM under
608 *end = 0x100000000ULL;
612 * This function fills in the mvebu_mbus_dram_info_nooverlap data
613 * structure, by looking at the mvebu_mbus_dram_info data, and
614 * removing the parts of it that overlap with I/O windows.
617 mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
619 uint64_t mbus_bridge_base, mbus_bridge_end;
620 int cs_nooverlap = 0;
623 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
625 for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
626 struct mbus_dram_window *w;
629 w = &mvebu_mbus_dram_info.cs[i];
635 * The CS is fully enclosed inside the MBus bridge
636 * area, so ignore it.
638 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
642 * Beginning of CS overlaps with end of MBus, raise CS
643 * base address, and shrink its size.
645 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
646 size -= mbus_bridge_end - base;
647 base = mbus_bridge_end;
651 * End of CS overlaps with beginning of MBus, shrink
654 if (base < mbus_bridge_base && end > mbus_bridge_base)
655 size -= end - mbus_bridge_base;
657 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
659 w->mbus_attr = 0xf & ~(1 << i);
660 if (mbus->hw_io_coherency)
661 w->mbus_attr |= ATTR_HW_COHERENCY;
666 mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
667 mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
671 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
676 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
678 for (i = 0, cs = 0; i < 4; i++) {
679 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
680 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
683 * We only take care of entries for which the chip
684 * select is enabled, and that don't have high base
685 * address bits set (devices can only access the first
686 * 32 bits of the memory).
688 if ((size & DDR_SIZE_ENABLED) &&
689 !(base & DDR_BASE_CS_HIGH_MASK)) {
690 struct mbus_dram_window *w;
692 w = &mvebu_mbus_dram_info.cs[cs++];
694 w->mbus_attr = 0xf & ~(1 << i);
695 if (mbus->hw_io_coherency)
696 w->mbus_attr |= ATTR_HW_COHERENCY;
697 w->base = base & DDR_BASE_CS_LOW_MASK;
698 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
701 mvebu_mbus_dram_info.num_cs = cs;
705 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
706 u32 __iomem *store_addr)
710 for (i = 0; i < 4; i++) {
711 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
712 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
714 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
716 writel(base, store_addr++);
717 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
719 writel(size, store_addr++);
722 /* We've written 16 words to the store address */
727 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
732 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
734 for (i = 0, cs = 0; i < 2; i++) {
735 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
738 * Chip select enabled?
741 struct mbus_dram_window *w;
743 w = &mvebu_mbus_dram_info.cs[cs++];
745 w->mbus_attr = 0; /* CS address decoding done inside */
746 /* the DDR controller, no need to */
747 /* provide attributes */
748 w->base = map & 0xff800000;
749 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
753 mvebu_mbus_dram_info.num_cs = cs;
757 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
758 u32 __iomem *store_addr)
762 for (i = 0; i < 2; i++) {
763 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
765 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
767 writel(map, store_addr++);
770 /* We've written 4 words to the store address */
774 int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
776 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
779 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
781 .has_mbus_bridge = true,
782 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
783 .win_remap_offset = generic_mbus_win_remap_8_offset,
784 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
785 .show_cpu_target = mvebu_sdram_debug_show_orion,
786 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
789 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
791 .has_mbus_bridge = true,
792 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
793 .win_remap_offset = armada_xp_mbus_win_remap_offset,
794 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
795 .show_cpu_target = mvebu_sdram_debug_show_orion,
796 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
799 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
801 .win_cfg_offset = generic_mbus_win_cfg_offset,
802 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
803 .win_remap_offset = generic_mbus_win_remap_4_offset,
804 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
805 .show_cpu_target = mvebu_sdram_debug_show_orion,
808 static const struct mvebu_mbus_soc_data dove_mbus_data = {
810 .win_cfg_offset = generic_mbus_win_cfg_offset,
811 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
812 .win_remap_offset = generic_mbus_win_remap_4_offset,
813 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
814 .show_cpu_target = mvebu_sdram_debug_show_dove,
818 * Some variants of Orion5x have 4 remappable windows, some other have
821 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
823 .win_cfg_offset = generic_mbus_win_cfg_offset,
824 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
825 .win_remap_offset = generic_mbus_win_remap_4_offset,
826 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
827 .show_cpu_target = mvebu_sdram_debug_show_orion,
830 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
832 .win_cfg_offset = generic_mbus_win_cfg_offset,
833 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
834 .win_remap_offset = generic_mbus_win_remap_2_offset,
835 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
836 .show_cpu_target = mvebu_sdram_debug_show_orion,
839 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
841 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
842 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
843 .win_remap_offset = generic_mbus_win_remap_8_offset,
844 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
845 .show_cpu_target = mvebu_sdram_debug_show_orion,
848 static const struct of_device_id of_mvebu_mbus_ids[] = {
849 { .compatible = "marvell,armada370-mbus",
850 .data = &armada_370_mbus_data, },
851 { .compatible = "marvell,armada375-mbus",
852 .data = &armada_xp_mbus_data, },
853 { .compatible = "marvell,armada380-mbus",
854 .data = &armada_xp_mbus_data, },
855 { .compatible = "marvell,armadaxp-mbus",
856 .data = &armada_xp_mbus_data, },
857 { .compatible = "marvell,kirkwood-mbus",
858 .data = &kirkwood_mbus_data, },
859 { .compatible = "marvell,dove-mbus",
860 .data = &dove_mbus_data, },
861 { .compatible = "marvell,orion5x-88f5281-mbus",
862 .data = &orion5x_4win_mbus_data, },
863 { .compatible = "marvell,orion5x-88f5182-mbus",
864 .data = &orion5x_2win_mbus_data, },
865 { .compatible = "marvell,orion5x-88f5181-mbus",
866 .data = &orion5x_2win_mbus_data, },
867 { .compatible = "marvell,orion5x-88f6183-mbus",
868 .data = &orion5x_4win_mbus_data, },
869 { .compatible = "marvell,mv78xx0-mbus",
870 .data = &mv78xx0_mbus_data, },
875 * Public API of the driver
877 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
878 unsigned int attribute,
879 phys_addr_t base, size_t size,
882 struct mvebu_mbus_state *s = &mbus_state;
884 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
885 pr_err("cannot add window '%x:%x', conflicts with another window\n",
890 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
892 EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id);
894 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
895 phys_addr_t base, size_t size)
897 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
898 size, MVEBU_MBUS_NO_REMAP);
900 EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id);
902 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
906 win = mvebu_mbus_find_window(&mbus_state, base, size);
910 mvebu_mbus_disable_window(&mbus_state, win);
913 EXPORT_SYMBOL_GPL(mvebu_mbus_del_window);
915 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
919 *res = mbus_state.pcie_mem_aperture;
921 EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture);
923 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
927 *res = mbus_state.pcie_io_aperture;
929 EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture);
931 int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
933 const struct mbus_dram_target_info *dram;
937 dram = mv_mbus_dram_info();
939 pr_err("missing DRAM information\n");
943 /* Try to find matching DRAM window for phyaddr */
944 for (i = 0; i < dram->num_cs; i++) {
945 const struct mbus_dram_window *cs = dram->cs + i;
947 if (cs->base <= phyaddr &&
948 phyaddr <= (cs->base + cs->size - 1)) {
949 *target = dram->mbus_dram_target_id;
950 *attr = cs->mbus_attr;
955 pr_err("invalid dram address %pa\n", &phyaddr);
958 EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
960 int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
965 for (win = 0; win < mbus_state.soc->num_wins; win++) {
969 mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
970 size, target, attr, NULL);
975 if (wbase <= phyaddr && phyaddr <= wbase + *size)
981 EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
983 static __init int mvebu_mbus_debugfs_init(void)
985 struct mvebu_mbus_state *s = &mbus_state;
988 * If no base has been initialized, doesn't make sense to
989 * register the debugfs entries. We may be on a multiplatform
990 * kernel that isn't running a Marvell EBU SoC.
992 if (!s->mbuswins_base)
995 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
996 if (s->debugfs_root) {
997 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
998 s->debugfs_root, NULL,
999 &mvebu_sdram_debug_fops);
1000 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
1001 s->debugfs_root, NULL,
1002 &mvebu_devs_debug_fops);
1007 fs_initcall(mvebu_mbus_debugfs_init);
1009 static int mvebu_mbus_suspend(void)
1011 struct mvebu_mbus_state *s = &mbus_state;
1014 if (!s->mbusbridge_base)
1017 for (win = 0; win < s->soc->num_wins; win++) {
1018 void __iomem *addr = s->mbuswins_base +
1019 s->soc->win_cfg_offset(win);
1020 void __iomem *addr_rmp;
1022 s->wins[win].base = readl(addr + WIN_BASE_OFF);
1023 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
1025 if (!mvebu_mbus_window_is_remappable(s, win))
1028 addr_rmp = s->mbuswins_base +
1029 s->soc->win_remap_offset(win);
1031 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
1032 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
1035 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
1036 MBUS_BRIDGE_CTRL_OFF);
1037 s->mbus_bridge_base = readl(s->mbusbridge_base +
1038 MBUS_BRIDGE_BASE_OFF);
1043 static void mvebu_mbus_resume(void)
1045 struct mvebu_mbus_state *s = &mbus_state;
1048 writel(s->mbus_bridge_ctrl,
1049 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
1050 writel(s->mbus_bridge_base,
1051 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
1053 for (win = 0; win < s->soc->num_wins; win++) {
1054 void __iomem *addr = s->mbuswins_base +
1055 s->soc->win_cfg_offset(win);
1056 void __iomem *addr_rmp;
1058 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1059 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
1061 if (!mvebu_mbus_window_is_remappable(s, win))
1064 addr_rmp = s->mbuswins_base +
1065 s->soc->win_remap_offset(win);
1067 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
1068 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
1072 static struct syscore_ops mvebu_mbus_syscore_ops = {
1073 .suspend = mvebu_mbus_suspend,
1074 .resume = mvebu_mbus_resume,
1077 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1078 phys_addr_t mbuswins_phys_base,
1079 size_t mbuswins_size,
1080 phys_addr_t sdramwins_phys_base,
1081 size_t sdramwins_size,
1082 phys_addr_t mbusbridge_phys_base,
1083 size_t mbusbridge_size,
1088 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1089 if (!mbus->mbuswins_base)
1092 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1093 if (!mbus->sdramwins_base) {
1094 iounmap(mbus->mbuswins_base);
1098 mbus->sdramwins_phys_base = sdramwins_phys_base;
1100 if (mbusbridge_phys_base) {
1101 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1103 if (!mbus->mbusbridge_base) {
1104 iounmap(mbus->sdramwins_base);
1105 iounmap(mbus->mbuswins_base);
1109 mbus->mbusbridge_base = NULL;
1111 for (win = 0; win < mbus->soc->num_wins; win++)
1112 mvebu_mbus_disable_window(mbus, win);
1114 mbus->soc->setup_cpu_target(mbus);
1115 mvebu_mbus_setup_cpu_target_nooverlap(mbus);
1118 writel(UNIT_SYNC_BARRIER_ALL,
1119 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1121 register_syscore_ops(&mvebu_mbus_syscore_ops);
1126 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1127 size_t mbuswins_size,
1128 phys_addr_t sdramwins_phys_base,
1129 size_t sdramwins_size)
1131 const struct of_device_id *of_id;
1133 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1134 if (!strcmp(of_id->compatible, soc))
1137 if (!of_id->compatible[0]) {
1138 pr_err("could not find a matching SoC family\n");
1142 mbus_state.soc = of_id->data;
1144 return mvebu_mbus_common_init(&mbus_state,
1147 sdramwins_phys_base,
1148 sdramwins_size, 0, 0, false);
1153 * The window IDs in the ranges DT property have the following format:
1154 * - bits 28 to 31: MBus custom field
1155 * - bits 24 to 27: window target ID
1156 * - bits 16 to 23: window attribute ID
1157 * - bits 0 to 15: unused
1159 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1160 #define TARGET(id) (((id) & 0x0F000000) >> 24)
1161 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
1163 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1167 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1168 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1173 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1175 pr_err("cannot add window '%04x:%04x', too many windows\n",
1182 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1183 struct device_node *np)
1186 struct of_range_parser parser;
1187 struct of_range range;
1189 ret = of_range_parser_init(&parser, np);
1193 for_each_of_range(&parser, &range) {
1194 u32 windowid = upper_32_bits(range.bus_addr);
1198 * An entry with a non-zero custom field do not
1199 * correspond to a static window, so skip it.
1201 if (CUSTOM(windowid))
1204 target = TARGET(windowid);
1205 attr = ATTR(windowid);
1207 ret = mbus_dt_setup_win(mbus, range.cpu_addr, range.size, target, attr);
1214 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1215 struct resource *mem,
1216 struct resource *io)
1222 * These are optional, so we make sure that resource_size(x) will
1225 memset(mem, 0, sizeof(struct resource));
1227 memset(io, 0, sizeof(struct resource));
1230 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1232 mem->start = reg[0];
1233 mem->end = mem->start + reg[1] - 1;
1234 mem->flags = IORESOURCE_MEM;
1237 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1240 io->end = io->start + reg[1] - 1;
1241 io->flags = IORESOURCE_IO;
1245 int __init mvebu_mbus_dt_init(bool is_coherent)
1247 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1248 struct device_node *np, *controller;
1249 const struct of_device_id *of_id;
1253 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1255 pr_err("could not find a matching SoC family\n");
1259 mbus_state.soc = of_id->data;
1261 prop = of_get_property(np, "controller", NULL);
1263 pr_err("required 'controller' property missing\n");
1267 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1269 pr_err("could not find an 'mbus-controller' node\n");
1273 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1274 pr_err("cannot get MBUS register address\n");
1278 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1279 pr_err("cannot get SDRAM register address\n");
1284 * Set the resource to 0 so that it can be left unmapped by
1285 * mvebu_mbus_common_init() if the DT doesn't carry the
1286 * necessary information. This is needed to preserve backward
1289 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1291 if (mbus_state.soc->has_mbus_bridge) {
1292 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1293 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1296 mbus_state.hw_io_coherency = is_coherent;
1298 /* Get optional pcie-{mem,io}-aperture properties */
1299 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1300 &mbus_state.pcie_io_aperture);
1302 ret = mvebu_mbus_common_init(&mbus_state,
1304 resource_size(&mbuswins_res),
1305 sdramwins_res.start,
1306 resource_size(&sdramwins_res),
1307 mbusbridge_res.start,
1308 resource_size(&mbusbridge_res),
1313 /* Setup statically declared windows in the DT */
1314 return mbus_dt_setup(&mbus_state, np);