2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Author: Tang Yuantian <b29983@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/byteorder.h>
33 /* Convert sectorsize to wordsize */
34 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
35 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
37 static struct sata_info sata_info;
39 static struct pci_device_id supported[] = {
40 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
41 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
42 {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
46 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
48 printf("Status FIS dump:\n");
49 printf("fis_type: %02x\n", s->fis_type);
50 printf("pm_port_i: %02x\n", s->pm_port_i);
51 printf("status: %02x\n", s->status);
52 printf("error: %02x\n", s->error);
53 printf("lba_low: %02x\n", s->lba_low);
54 printf("lba_mid: %02x\n", s->lba_mid);
55 printf("lba_high: %02x\n", s->lba_high);
56 printf("device: %02x\n", s->device);
57 printf("lba_low_exp: %02x\n", s->lba_low_exp);
58 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
59 printf("lba_high_exp: %02x\n", s->lba_high_exp);
60 printf("res1: %02x\n", s->res1);
61 printf("sector_count: %02x\n", s->sector_count);
62 printf("sector_count_exp: %02x\n", s->sector_count_exp);
65 static const char *sata_spd_string(unsigned int speed)
67 static const char * const spd_str[] = {
76 return spd_str[speed - 1];
79 static u32 ata_wait_register(void *reg, u32 mask,
80 u32 val, int timeout_msec)
85 while ((tmp & mask) == val && timeout_msec > 0) {
94 static void sil_config_port(void *port)
96 /* configure IRQ WoC */
97 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
99 /* zero error counters. */
100 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
101 writew(0x8000, port + PORT_CRC_ERR_THRESH);
102 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
103 writew(0x0000, port + PORT_DECODE_ERR_CNT);
104 writew(0x0000, port + PORT_CRC_ERR_CNT);
105 writew(0x0000, port + PORT_HSHK_ERR_CNT);
107 /* always use 64bit activation */
108 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
110 /* clear port multiplier enable and resume bits */
111 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
114 static int sil_init_port(void *port)
118 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
119 ata_wait_register(port + PORT_CTRL_STAT,
120 PORT_CS_INIT, PORT_CS_INIT, 100);
121 tmp = ata_wait_register(port + PORT_CTRL_STAT,
122 PORT_CS_RDY, 0, 100);
124 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
130 static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
132 struct sil_sata *sata = sata_dev_desc[dev].priv;
133 void *port = sata->port;
138 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
139 src = (u32 *)&prb->fis;
141 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
142 *dst++ = readl(src++);
145 static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
147 struct sil_sata *sata = sata_dev_desc[dev].priv;
148 void *port = sata->port;
149 u64 paddr = virt_to_bus(sata->devno, pcmd);
150 u32 irq_mask, irq_stat;
153 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
155 /* better to add momery barrior here */
156 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
157 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
159 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
160 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
164 writel(irq_mask, port + PORT_IRQ_STAT);
165 irq_stat >>= PORT_IRQ_RAW_SHIFT;
167 if (irq_stat & PORT_IRQ_COMPLETE)
170 /* force port into known state */
172 if (irq_stat & PORT_IRQ_ERROR)
181 static int sil_cmd_set_feature(int dev)
183 struct sil_sata *sata = sata_dev_desc[dev].priv;
184 struct sil_cmd_block cmdb, *pcmd = &cmdb;
185 struct sata_fis_d2h fis;
189 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
190 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
191 pcmd->prb.fis.pm_port_c = (1 << 7);
192 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
193 pcmd->prb.fis.features = SETFEATURES_XFER;
195 /* First check the device capablity */
196 udma_cap = (u8)(sata->udma & 0xff);
197 debug("udma_cap %02x\n", udma_cap);
199 if (udma_cap == ATA_UDMA6)
200 pcmd->prb.fis.sector_count = XFER_UDMA_6;
201 if (udma_cap == ATA_UDMA5)
202 pcmd->prb.fis.sector_count = XFER_UDMA_5;
203 if (udma_cap == ATA_UDMA4)
204 pcmd->prb.fis.sector_count = XFER_UDMA_4;
205 if (udma_cap == ATA_UDMA3)
206 pcmd->prb.fis.sector_count = XFER_UDMA_3;
208 ret = sil_exec_cmd(dev, pcmd, 0);
210 sil_read_fis(dev, 0, &fis);
211 printf("Err: exe cmd(0x%x).\n",
212 readl(sata->port + PORT_SERROR));
213 sil_sata_dump_fis(&fis);
220 static int sil_cmd_identify_device(int dev, u16 *id)
222 struct sil_sata *sata = sata_dev_desc[dev].priv;
223 struct sil_cmd_block cmdb, *pcmd = &cmdb;
224 struct sata_fis_d2h fis;
227 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
228 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
229 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
230 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
231 pcmd->prb.fis.pm_port_c = (1 << 7);
232 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
233 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
234 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
235 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
237 ret = sil_exec_cmd(dev, pcmd, 0);
239 sil_read_fis(dev, 0, &fis);
240 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
241 sil_sata_dump_fis(&fis);
244 ata_swap_buf_le16(id, ATA_ID_WORDS);
249 static int sil_cmd_soft_reset(int dev)
251 struct sil_cmd_block cmdb, *pcmd = &cmdb;
252 struct sil_sata *sata = sata_dev_desc[dev].priv;
253 struct sata_fis_d2h fis;
254 void *port = sata->port;
257 /* put the port into known state */
258 if (sil_init_port(port)) {
259 printf("SRST: port %d not ready\n", dev);
263 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
265 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
266 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
267 pcmd->prb.fis.pm_port_c = 0xf;
269 ret = sil_exec_cmd(dev, &cmdb, 0);
271 sil_read_fis(dev, 0, &fis);
272 printf("SRST cmd error.\n");
273 sil_sata_dump_fis(&fis);
280 static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
281 u8 *buffer, int is_write)
283 struct sil_sata *sata = sata_dev_desc[dev].priv;
284 struct sil_cmd_block cmdb, *pcmd = &cmdb;
285 struct sata_fis_d2h fis;
290 memset(pcmd, 0, sizeof(struct sil_cmd_block));
291 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
292 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
293 pcmd->prb.fis.pm_port_c = (1 << 7);
295 pcmd->prb.fis.command = ATA_CMD_WRITE;
296 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
298 pcmd->prb.fis.command = ATA_CMD_READ;
299 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
302 pcmd->prb.fis.device = ATA_LBA;
303 pcmd->prb.fis.device |= (block >> 24) & 0xf;
304 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
305 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
306 pcmd->prb.fis.lba_low = block & 0xff;
307 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
309 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
310 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
311 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
313 ret = sil_exec_cmd(dev, pcmd, 0);
315 sil_read_fis(dev, 0, &fis);
316 printf("Err: rw cmd(0x%08x).\n",
317 readl(sata->port + PORT_SERROR));
318 sil_sata_dump_fis(&fis);
325 static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
326 u8 *buffer, int is_write)
328 struct sil_sata *sata = sata_dev_desc[dev].priv;
329 struct sil_cmd_block cmdb, *pcmd = &cmdb;
330 struct sata_fis_d2h fis;
335 memset(pcmd, 0, sizeof(struct sil_cmd_block));
336 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
337 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
338 pcmd->prb.fis.pm_port_c = (1 << 7);
340 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
341 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
343 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
344 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
347 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
348 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
349 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
350 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
351 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
352 pcmd->prb.fis.lba_low = block & 0xff;
353 pcmd->prb.fis.device = ATA_LBA;
354 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
355 pcmd->prb.fis.sector_count = blkcnt & 0xff;
357 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
358 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
359 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
361 ret = sil_exec_cmd(dev, pcmd, 0);
363 sil_read_fis(dev, 0, &fis);
364 printf("Err: rw ext cmd(0x%08x).\n",
365 readl(sata->port + PORT_SERROR));
366 sil_sata_dump_fis(&fis);
373 static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
374 const void *buffer, int is_write)
376 ulong start, blks, max_blks;
383 max_blks = ATA_MAX_SECTORS;
385 if (blks > max_blks) {
386 sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
389 addr += ATA_SECT_SIZE * max_blks;
391 sil_sata_rw_cmd(dev, start, blks, addr, is_write);
394 addr += ATA_SECT_SIZE * blks;
401 static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
402 const void *buffer, int is_write)
404 ulong start, blks, max_blks;
411 max_blks = ATA_MAX_SECTORS_LBA48;
413 if (blks > max_blks) {
414 sil_sata_rw_cmd_ext(dev, start, max_blks,
418 addr += ATA_SECT_SIZE * max_blks;
420 sil_sata_rw_cmd_ext(dev, start, blks,
424 addr += ATA_SECT_SIZE * blks;
431 static void sil_sata_cmd_flush_cache(int dev)
433 struct sil_cmd_block cmdb, *pcmd = &cmdb;
435 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
436 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
437 pcmd->prb.fis.pm_port_c = (1 << 7);
438 pcmd->prb.fis.command = ATA_CMD_FLUSH;
440 sil_exec_cmd(dev, pcmd, 0);
443 static void sil_sata_cmd_flush_cache_ext(int dev)
445 struct sil_cmd_block cmdb, *pcmd = &cmdb;
447 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
448 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
449 pcmd->prb.fis.pm_port_c = (1 << 7);
450 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
452 sil_exec_cmd(dev, pcmd, 0);
455 static void sil_sata_init_wcache(int dev, u16 *id)
457 struct sil_sata *sata = sata_dev_desc[dev].priv;
459 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
461 if (ata_id_has_flush(id))
463 if (ata_id_has_flush_ext(id))
467 static int sil_sata_get_wcache(int dev)
469 struct sil_sata *sata = sata_dev_desc[dev].priv;
474 static int sil_sata_get_flush(int dev)
476 struct sil_sata *sata = sata_dev_desc[dev].priv;
481 static int sil_sata_get_flush_ext(int dev)
483 struct sil_sata *sata = sata_dev_desc[dev].priv;
485 return sata->flush_ext;
489 * SATA interface between low level driver and command layer
491 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
493 struct sil_sata *sata = sata_dev_desc[dev].priv;
497 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
499 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
505 * SATA interface between low level driver and command layer
507 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
509 struct sil_sata *sata = sata_dev_desc[dev].priv;
513 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
514 if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
515 sil_sata_cmd_flush_cache_ext(dev);
517 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
518 if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
519 sil_sata_cmd_flush_cache(dev);
526 * SATA interface between low level driver and command layer
528 int init_sata(int dev)
530 static int init_done, idx;
534 if (init_done == 1 && dev < sata_info.maxport)
539 /* Find PCI device(s) */
540 devno = pci_find_devices(supported, idx++);
544 pci_read_config_word(devno, PCI_DEVICE_ID, &word);
546 /* get the port count */
549 sata_info.portbase = sata_info.maxport;
550 sata_info.maxport = sata_info.portbase + word;
551 sata_info.devno = devno;
553 /* Read out all BARs */
554 sata_info.iobase[0] = (ulong)pci_map_bar(devno,
555 PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
556 sata_info.iobase[1] = (ulong)pci_map_bar(devno,
557 PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
558 sata_info.iobase[2] = (ulong)pci_map_bar(devno,
559 PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
561 /* mask out the unused bits */
562 sata_info.iobase[0] &= 0xffffff80;
563 sata_info.iobase[1] &= 0xfffffc00;
564 sata_info.iobase[2] &= 0xffffff80;
566 /* Enable Bus Mastering and memory region */
567 pci_write_config_word(devno, PCI_COMMAND,
568 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
570 /* Check if mem accesses and Bus Mastering are enabled. */
571 pci_read_config_word(devno, PCI_COMMAND, &word);
572 if (!(word & PCI_COMMAND_MEMORY) ||
573 (!(word & PCI_COMMAND_MASTER))) {
574 printf("Error: Can not enable MEM access or Bus Mastering.\n");
575 debug("PCI command: %04x\n", word);
580 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
581 /* clear global reset & mask interrupts during initialization */
582 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
588 * SATA interface between low level driver and command layer
590 int scan_sata(int dev)
592 unsigned char serial[ATA_ID_SERNO_LEN + 1];
593 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
594 unsigned char product[ATA_ID_PROD_LEN + 1];
595 struct sil_sata *sata;
601 if (dev >= sata_info.maxport) {
602 printf("SATA#%d is not present\n", dev);
606 printf("SATA#%d\n", dev);
607 port = (void *)sata_info.iobase[1] +
608 PORT_REGS_SIZE * (dev - sata_info.portbase);
610 /* Initial PHY setting */
611 writel(0x20c, port + PORT_PHY_CFG);
614 tmp = readl(port + PORT_CTRL_STAT);
615 if (tmp & PORT_CS_PORT_RST) {
616 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
617 tmp = ata_wait_register(port + PORT_CTRL_STAT,
618 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
619 if (tmp & PORT_CS_PORT_RST)
620 printf("Err: Failed to clear port RST\n");
623 /* Check if device is present */
624 for (cnt = 0; cnt < 100; cnt++) {
625 tmp = readl(port + PORT_SSTATUS);
626 if ((tmp & 0xF) == 0x3)
631 tmp = readl(port + PORT_SSTATUS);
632 if ((tmp & 0xf) != 0x3) {
633 printf(" (No RDY)\n");
637 /* Wait for port ready */
638 tmp = ata_wait_register(port + PORT_CTRL_STAT,
639 PORT_CS_RDY, PORT_CS_RDY, 100);
640 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
641 printf("%d port not ready.\n", dev);
646 sil_config_port(port);
649 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
650 readl(port + PORT_CTRL_STAT);
651 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
652 PORT_CS_DEV_RST, 100);
653 if (tmp & PORT_CS_DEV_RST) {
654 printf("%d port reset failed.\n", dev);
658 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
660 printf("%d no memory.\n", dev);
663 memset((void *)sata, 0, sizeof(struct sil_sata));
665 /* turn on port interrupt */
666 tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
667 tmp |= (1 << (dev - sata_info.portbase));
668 writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
670 /* Save the private struct to block device struct */
671 sata_dev_desc[dev].priv = (void *)sata;
673 sata->devno = sata_info.devno;
674 sprintf(sata->name, "SATA#%d", dev);
675 sil_cmd_soft_reset(dev);
676 tmp = readl(port + PORT_SSTATUS);
677 tmp = (tmp >> 4) & 0xf;
678 printf(" (%s)\n", sata_spd_string(tmp));
680 id = (u16 *)malloc(ATA_ID_WORDS * 2);
682 printf("Id malloc failed\n");
686 sil_cmd_identify_device(dev, id);
689 /* Check if support LBA48 */
690 if (ata_id_has_lba48(id)) {
691 sata_dev_desc[dev].lba48 = 1;
693 debug("Device supports LBA48\n");
695 debug("Device supports LBA28\n");
699 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
700 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
702 /* Firmware version */
703 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
704 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
707 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
708 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
711 sata_dev_desc[dev].lba = ata_id_n_sectors(id);
713 sil_sata_init_wcache(dev, id);
714 sil_cmd_set_feature(dev);
717 sil_cmd_identify_device(dev, id);