drivers/block/rsxx/rsxx_priv.h

   1 /*
   2 * Filename: rsxx_priv.h
   3 *
   4 *
   5 * Authors: Joshua Morris <josh.h.morris@us.ibm.com>
   6 *       Philip Kelleher <pjk1939@linux.vnet.ibm.com>
   7 *
   8 * (C) Copyright 2013 IBM Corporation
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of the
  13 * License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful, but
  16 * WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18 * General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software Foundation,
  22 * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23 */
  24
  25 #ifndef __RSXX_PRIV_H__
  26 #define __RSXX_PRIV_H__
  27
  28 #include <linux/version.h>
  29 #include <linux/semaphore.h>
  30
  31 #include <linux/fs.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/mutex.h>
  34 #include <linux/pci.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/sysfs.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/bio.h>
  39 #include <linux/vmalloc.h>
  40 #include <linux/timer.h>
  41 #include <linux/ioctl.h>
  42
  43 #include "rsxx.h"
  44 #include "rsxx_cfg.h"
  45
  46 struct proc_cmd;
  47
  48 #define PCI_DEVICE_ID_FS70_FLASH        0x04A9
  49 #define PCI_DEVICE_ID_FS80_FLASH        0x04AA
  50
  51 #define RS70_PCI_REV_SUPPORTED  4
  52
  53 #define DRIVER_NAME "rsxx"
  54 #define DRIVER_VERSION "4.0"
  55
  56 /* Block size is 4096 */
  57 #define RSXX_HW_BLK_SHIFT               12
  58 #define RSXX_HW_BLK_SIZE                (1 << RSXX_HW_BLK_SHIFT)
  59 #define RSXX_HW_BLK_MASK                (RSXX_HW_BLK_SIZE - 1)
  60
  61 #define MAX_CREG_DATA8  32
  62 #define LOG_BUF_SIZE8   128
  63
  64 #define RSXX_MAX_OUTSTANDING_CMDS       255
  65 #define RSXX_CS_IDX_MASK                0xff
  66
  67 #define STATUS_BUFFER_SIZE8     4096
  68 #define COMMAND_BUFFER_SIZE8    4096
  69
  70 #define RSXX_MAX_TARGETS        8
  71
  72 struct dma_tracker_list;
  73
  74 /* DMA Command/Status Buffer structure */
  75 struct rsxx_cs_buffer {
  76         dma_addr_t      dma_addr;
  77         void            *buf;
  78         u32             idx;
  79 };
  80
  81 struct rsxx_dma_stats {
  82         u32 crc_errors;
  83         u32 hard_errors;
  84         u32 soft_errors;
  85         u32 writes_issued;
  86         u32 writes_failed;
  87         u32 reads_issued;
  88         u32 reads_failed;
  89         u32 reads_retried;
  90         u32 discards_issued;
  91         u32 discards_failed;
  92         u32 done_rescheduled;
  93         u32 issue_rescheduled;
  94         u32 dma_sw_err;
  95         u32 dma_hw_fault;
  96         u32 dma_cancelled;
  97         u32 sw_q_depth;         /* Number of DMAs on the SW queue. */
  98         atomic_t hw_q_depth;    /* Number of DMAs queued to HW. */
  99 };
 100
 101 struct rsxx_dma_ctrl {
 102         struct rsxx_cardinfo            *card;
 103         int                             id;
 104         void                            __iomem *regmap;
 105         struct rsxx_cs_buffer           status;
 106         struct rsxx_cs_buffer           cmd;
 107         u16                             e_cnt;
 108         spinlock_t                      queue_lock;
 109         struct list_head                queue;
 110         struct workqueue_struct         *issue_wq;
 111         struct work_struct              issue_dma_work;
 112         struct workqueue_struct         *done_wq;
 113         struct work_struct              dma_done_work;
 114         struct timer_list               activity_timer;
 115         struct dma_tracker_list         *trackers;
 116         struct rsxx_dma_stats           stats;
 117 };
 118
 119 struct rsxx_cardinfo {
 120         struct pci_dev          *dev;
 121         unsigned int            halt;
 122         unsigned int            eeh_state;
 123
 124         void                    __iomem *regmap;
 125         spinlock_t              irq_lock;
 126         unsigned int            isr_mask;
 127         unsigned int            ier_mask;
 128
 129         struct rsxx_card_cfg    config;
 130         int                     config_valid;
 131
 132         /* Embedded CPU Communication */
 133         struct {
 134                 spinlock_t              lock;
 135                 bool                    active;
 136                 struct creg_cmd         *active_cmd;
 137                 struct workqueue_struct *creg_wq;
 138                 struct work_struct      done_work;
 139                 struct list_head        queue;
 140                 unsigned int            q_depth;
 141                 /* Cache the creg status to prevent ioreads */
 142                 struct {
 143                         u32             stat;
 144                         u32             failed_cancel_timer;
 145                         u32             creg_timeout;
 146                 } creg_stats;
 147                 struct timer_list       cmd_timer;
 148                 struct mutex            reset_lock;
 149                 int                     reset;
 150         } creg_ctrl;
 151
 152         struct {
 153                 char tmp[MAX_CREG_DATA8];
 154                 char buf[LOG_BUF_SIZE8]; /* terminated */
 155                 int buf_len;
 156         } log;
 157
 158         struct workqueue_struct *event_wq;
 159         struct work_struct      event_work;
 160         unsigned int            state;
 161         u64                     size8;
 162
 163         /* Lock the device attach/detach function */
 164         struct mutex            dev_lock;
 165
 166         /* Block Device Variables */
 167         bool                    bdev_attached;
 168         int                     disk_id;
 169         int                     major;
 170         struct request_queue    *queue;
 171         struct gendisk          *gendisk;
 172         struct {
 173                 /* Used to convert a byte address to a device address. */
 174                 u64 lower_mask;
 175                 u64 upper_shift;
 176                 u64 upper_mask;
 177                 u64 target_mask;
 178                 u64 target_shift;
 179         } _stripe;
 180         unsigned int            dma_fault;
 181
 182         int                     scrub_hard;
 183
 184         int                     n_targets;
 185         struct rsxx_dma_ctrl    *ctrl;
 186 };
 187
 188 enum rsxx_pci_regmap {
 189         HWID            = 0x00, /* Hardware Identification Register */
 190         SCRATCH         = 0x04, /* Scratch/Debug Register */
 191         RESET           = 0x08, /* Reset Register */
 192         ISR             = 0x10, /* Interrupt Status Register */
 193         IER             = 0x14, /* Interrupt Enable Register */
 194         IPR             = 0x18, /* Interrupt Poll Register */
 195         CB_ADD_LO       = 0x20, /* Command Host Buffer Address [31:0] */
 196         CB_ADD_HI       = 0x24, /* Command Host Buffer Address [63:32]*/
 197         HW_CMD_IDX      = 0x28, /* Hardware Processed Command Index */
 198         SW_CMD_IDX      = 0x2C, /* Software Processed Command Index */
 199         SB_ADD_LO       = 0x30, /* Status Host Buffer Address [31:0] */
 200         SB_ADD_HI       = 0x34, /* Status Host Buffer Address [63:32] */
 201         HW_STATUS_CNT   = 0x38, /* Hardware Status Counter */
 202         SW_STATUS_CNT   = 0x3C, /* Deprecated */
 203         CREG_CMD        = 0x40, /* CPU Command Register */
 204         CREG_ADD        = 0x44, /* CPU Address Register */
 205         CREG_CNT        = 0x48, /* CPU Count Register */
 206         CREG_STAT       = 0x4C, /* CPU Status Register */
 207         CREG_DATA0      = 0x50, /* CPU Data Registers */
 208         CREG_DATA1      = 0x54,
 209         CREG_DATA2      = 0x58,
 210         CREG_DATA3      = 0x5C,
 211         CREG_DATA4      = 0x60,
 212         CREG_DATA5      = 0x64,
 213         CREG_DATA6      = 0x68,
 214         CREG_DATA7      = 0x6c,
 215         INTR_COAL       = 0x70, /* Interrupt Coalescing Register */
 216         HW_ERROR        = 0x74, /* Card Error Register */
 217         PCI_DEBUG0      = 0x78, /* PCI Debug Registers */
 218         PCI_DEBUG1      = 0x7C,
 219         PCI_DEBUG2      = 0x80,
 220         PCI_DEBUG3      = 0x84,
 221         PCI_DEBUG4      = 0x88,
 222         PCI_DEBUG5      = 0x8C,
 223         PCI_DEBUG6      = 0x90,
 224         PCI_DEBUG7      = 0x94,
 225         PCI_POWER_THROTTLE = 0x98,
 226         PERF_CTRL       = 0x9c,
 227         PERF_TIMER_LO   = 0xa0,
 228         PERF_TIMER_HI   = 0xa4,
 229         PERF_RD512_LO   = 0xa8,
 230         PERF_RD512_HI   = 0xac,
 231         PERF_WR512_LO   = 0xb0,
 232         PERF_WR512_HI   = 0xb4,
 233         PCI_RECONFIG    = 0xb8,
 234 };
 235
 236 enum rsxx_intr {
 237         CR_INTR_DMA0    = 0x00000001,
 238         CR_INTR_CREG    = 0x00000002,
 239         CR_INTR_DMA1    = 0x00000004,
 240         CR_INTR_EVENT   = 0x00000008,
 241         CR_INTR_DMA2    = 0x00000010,
 242         CR_INTR_DMA3    = 0x00000020,
 243         CR_INTR_DMA4    = 0x00000040,
 244         CR_INTR_DMA5    = 0x00000080,
 245         CR_INTR_DMA6    = 0x00000100,
 246         CR_INTR_DMA7    = 0x00000200,
 247         CR_INTR_ALL_C   = 0x0000003f,
 248         CR_INTR_ALL_G   = 0x000003ff,
 249         CR_INTR_DMA_ALL = 0x000003f5,
 250         CR_INTR_ALL     = 0xffffffff,
 251 };
 252
 253 static inline int CR_INTR_DMA(int N)
 254 {
 255         static const unsigned int _CR_INTR_DMA[] = {
 256                 CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
 257                 CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
 258         };
 259         return _CR_INTR_DMA[N];
 260 }
 261 enum rsxx_pci_reset {
 262         DMA_QUEUE_RESET         = 0x00000001,
 263 };
 264
 265 enum rsxx_hw_fifo_flush {
 266         RSXX_FLUSH_BUSY         = 0x00000002,
 267         RSXX_FLUSH_TIMEOUT      = 0x00000004,
 268 };
 269
 270 enum rsxx_pci_revision {
 271         RSXX_DISCARD_SUPPORT = 2,
 272         RSXX_EEH_SUPPORT     = 3,
 273 };
 274
 275 enum rsxx_creg_cmd {
 276         CREG_CMD_TAG_MASK       = 0x0000FF00,
 277         CREG_OP_WRITE           = 0x000000C0,
 278         CREG_OP_READ            = 0x000000E0,
 279 };
 280
 281 enum rsxx_creg_addr {
 282         CREG_ADD_CARD_CMD               = 0x80001000,
 283         CREG_ADD_CARD_STATE             = 0x80001004,
 284         CREG_ADD_CARD_SIZE              = 0x8000100c,
 285         CREG_ADD_CAPABILITIES           = 0x80001050,
 286         CREG_ADD_LOG                    = 0x80002000,
 287         CREG_ADD_NUM_TARGETS            = 0x80003000,
 288         CREG_ADD_CONFIG                 = 0xB0000000,
 289 };
 290
 291 enum rsxx_creg_card_cmd {
 292         CARD_CMD_STARTUP                = 1,
 293         CARD_CMD_SHUTDOWN               = 2,
 294         CARD_CMD_LOW_LEVEL_FORMAT       = 3,
 295         CARD_CMD_FPGA_RECONFIG_BR       = 4,
 296         CARD_CMD_FPGA_RECONFIG_MAIN     = 5,
 297         CARD_CMD_BACKUP                 = 6,
 298         CARD_CMD_RESET                  = 7,
 299         CARD_CMD_deprecated             = 8,
 300         CARD_CMD_UNINITIALIZE           = 9,
 301         CARD_CMD_DSTROY_EMERGENCY       = 10,
 302         CARD_CMD_DSTROY_NORMAL          = 11,
 303         CARD_CMD_DSTROY_EXTENDED        = 12,
 304         CARD_CMD_DSTROY_ABORT           = 13,
 305 };
 306
 307 enum rsxx_card_state {
 308         CARD_STATE_SHUTDOWN             = 0x00000001,
 309         CARD_STATE_STARTING             = 0x00000002,
 310         CARD_STATE_FORMATTING           = 0x00000004,
 311         CARD_STATE_UNINITIALIZED        = 0x00000008,
 312         CARD_STATE_GOOD                 = 0x00000010,
 313         CARD_STATE_SHUTTING_DOWN        = 0x00000020,
 314         CARD_STATE_FAULT                = 0x00000040,
 315         CARD_STATE_RD_ONLY_FAULT        = 0x00000080,
 316         CARD_STATE_DSTROYING            = 0x00000100,
 317 };
 318
 319 enum rsxx_led {
 320         LED_DEFAULT     = 0x0,
 321         LED_IDENTIFY    = 0x1,
 322         LED_SOAK        = 0x2,
 323 };
 324
 325 enum rsxx_creg_flash_lock {
 326         CREG_FLASH_LOCK         = 1,
 327         CREG_FLASH_UNLOCK       = 2,
 328 };
 329
 330 enum rsxx_card_capabilities {
 331         CARD_CAP_SUBPAGE_WRITES = 0x00000080,
 332 };
 333
 334 enum rsxx_creg_stat {
 335         CREG_STAT_STATUS_MASK   = 0x00000003,
 336         CREG_STAT_SUCCESS       = 0x1,
 337         CREG_STAT_ERROR         = 0x2,
 338         CREG_STAT_CHAR_PENDING  = 0x00000004, /* Character I/O pending bit */
 339         CREG_STAT_LOG_PENDING   = 0x00000008, /* HW log message pending bit */
 340         CREG_STAT_TAG_MASK      = 0x0000ff00,
 341 };
 342
 343 static inline unsigned int CREG_DATA(int N)
 344 {
 345         return CREG_DATA0 + (N << 2);
 346 }
 347
 348 /*----------------- Convenient Log Wrappers -------------------*/
 349 #define CARD_TO_DEV(__CARD)     (&(__CARD)->dev->dev)
 350
 351 /***** config.c *****/
 352 int rsxx_load_config(struct rsxx_cardinfo *card);
 353
 354 /***** core.c *****/
 355 void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 356 void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 357 void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
 358                                  unsigned int intr);
 359 void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
 360                                   unsigned int intr);
 361
 362 /***** dev.c *****/
 363 int rsxx_attach_dev(struct rsxx_cardinfo *card);
 364 void rsxx_detach_dev(struct rsxx_cardinfo *card);
 365 int rsxx_setup_dev(struct rsxx_cardinfo *card);
 366 void rsxx_destroy_dev(struct rsxx_cardinfo *card);
 367 int rsxx_dev_init(void);
 368 void rsxx_dev_cleanup(void);
 369
 370 /***** dma.c ****/
 371 typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
 372                                 void *cb_data,
 373                                 unsigned int status);
 374 int rsxx_dma_setup(struct rsxx_cardinfo *card);
 375 void rsxx_dma_destroy(struct rsxx_cardinfo *card);
 376 int rsxx_dma_init(void);
 377 void rsxx_dma_cleanup(void);
 378 void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
 379 int rsxx_dma_configure(struct rsxx_cardinfo *card);
 380 int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
 381                            struct bio *bio,
 382                            atomic_t *n_dmas,
 383                            rsxx_dma_cb cb,
 384                            void *cb_data);
 385 int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
 386 int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
 387 void rsxx_eeh_cancel_dmas(struct rsxx_cardinfo *card);
 388 int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
 389
 390 /***** cregs.c *****/
 391 int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
 392                         unsigned int size8,
 393                         void *data,
 394                         int byte_stream);
 395 int rsxx_creg_read(struct rsxx_cardinfo *card,
 396                        u32 addr,
 397                        unsigned int size8,
 398                        void *data,
 399                        int byte_stream);
 400 int rsxx_read_hw_log(struct rsxx_cardinfo *card);
 401 int rsxx_get_card_state(struct rsxx_cardinfo *card,
 402                             unsigned int *state);
 403 int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
 404 int rsxx_get_num_targets(struct rsxx_cardinfo *card,
 405                              unsigned int *n_targets);
 406 int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
 407                                    u32 *capabilities);
 408 int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
 409 int rsxx_creg_setup(struct rsxx_cardinfo *card);
 410 void rsxx_creg_destroy(struct rsxx_cardinfo *card);
 411 int rsxx_creg_init(void);
 412 void rsxx_creg_cleanup(void);
 413 int rsxx_reg_access(struct rsxx_cardinfo *card,
 414                         struct rsxx_reg_access __user *ucmd,
 415                         int read);
 416 void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
 417 void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
 418
 419
 420
 421 #endif /* __DRIVERS_BLOCK_RSXX_H__ */