drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/fs.h>
  26 #include <linux/genhd.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kthread.h>
  33 #include <linux/kernel.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/version.h>
  43
  44 #define NVME_Q_DEPTH 1024
  45 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  46 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  47 #define NVME_MINORS 64
  48 #define IO_TIMEOUT      (5 * HZ)
  49 #define ADMIN_TIMEOUT   (60 * HZ)
  50
  51 static int nvme_major;
  52 module_param(nvme_major, int, 0);
  53
  54 static int use_threaded_interrupts;
  55 module_param(use_threaded_interrupts, int, 0);
  56
  57 static DEFINE_SPINLOCK(dev_list_lock);
  58 static LIST_HEAD(dev_list);
  59 static struct task_struct *nvme_thread;
  60
  61 /*
  62  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  63  */
  64 struct nvme_dev {
  65         struct list_head node;
  66         struct nvme_queue **queues;
  67         u32 __iomem *dbs;
  68         struct pci_dev *pci_dev;
  69         struct dma_pool *prp_page_pool;
  70         struct dma_pool *prp_small_pool;
  71         int instance;
  72         int queue_count;
  73         int db_stride;
  74         u32 ctrl_config;
  75         struct msix_entry *entry;
  76         struct nvme_bar __iomem *bar;
  77         struct list_head namespaces;
  78         char serial[20];
  79         char model[40];
  80         char firmware_rev[8];
  81 };
  82
  83 /*
  84  * An NVM Express namespace is equivalent to a SCSI LUN
  85  */
  86 struct nvme_ns {
  87         struct list_head list;
  88
  89         struct nvme_dev *dev;
  90         struct request_queue *queue;
  91         struct gendisk *disk;
  92
  93         int ns_id;
  94         int lba_shift;
  95 };
  96
  97 /*
  98  * An NVM Express queue.  Each device has at least two (one for admin
  99  * commands and one for I/O commands).
 100  */
 101 struct nvme_queue {
 102         struct device *q_dmadev;
 103         struct nvme_dev *dev;
 104         spinlock_t q_lock;
 105         struct nvme_command *sq_cmds;
 106         volatile struct nvme_completion *cqes;
 107         dma_addr_t sq_dma_addr;
 108         dma_addr_t cq_dma_addr;
 109         wait_queue_head_t sq_full;
 110         wait_queue_t sq_cong_wait;
 111         struct bio_list sq_cong;
 112         u32 __iomem *q_db;
 113         u16 q_depth;
 114         u16 cq_vector;
 115         u16 sq_head;
 116         u16 sq_tail;
 117         u16 cq_head;
 118         u16 cq_phase;
 119         unsigned long cmdid_data[];
 120 };
 121
 122 /*
 123  * Check we didin't inadvertently grow the command struct
 124  */
 125 static inline void _nvme_check_size(void)
 126 {
 127         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 133         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 134         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 135         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 136 }
 137
 138 struct nvme_cmd_info {
 139         unsigned long ctx;
 140         unsigned long timeout;
 141 };
 142
 143 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 144 {
 145         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 146 }
 147
 148 /**
 149  * alloc_cmdid() - Allocate a Command ID
 150  * @nvmeq: The queue that will be used for this command
 151  * @ctx: A pointer that will be passed to the handler
 152  * @handler: The ID of the handler to call
 153  *
 154  * Allocate a Command ID for a queue.  The data passed in will
 155  * be passed to the completion handler.  This is implemented by using
 156  * the bottom two bits of the ctx pointer to store the handler ID.
 157  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 158  * We can change this if it becomes a problem.
 159  *
 160  * May be called with local interrupts disabled and the q_lock held,
 161  * or with interrupts enabled and no locks held.
 162  */
 163 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 164                                                         unsigned timeout)
 165 {
 166         int depth = nvmeq->q_depth - 1;
 167         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 168         int cmdid;
 169
 170         BUG_ON((unsigned long)ctx & 3);
 171
 172         do {
 173                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 174                 if (cmdid >= depth)
 175                         return -EBUSY;
 176         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 177
 178         info[cmdid].ctx = (unsigned long)ctx | handler;
 179         info[cmdid].timeout = jiffies + timeout;
 180         return cmdid;
 181 }
 182
 183 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 184                                                 int handler, unsigned timeout)
 185 {
 186         int cmdid;
 187         wait_event_killable(nvmeq->sq_full,
 188                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 189         return (cmdid < 0) ? -EINTR : cmdid;
 190 }
 191
 192 /*
 193  * If you need more than four handlers, you'll need to change how
 194  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 195  * CMD_CTX value instead, if that works for your situation.
 196  */
 197 enum {
 198         sync_completion_id = 0,
 199         bio_completion_id,
 200 };
 201
 202 /* Special values must be a multiple of 4, and less than 0x1000 */
 203 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 204 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 205 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 206 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 207 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 208
 209 /*
 210  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 211  */
 212 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 213 {
 214         unsigned long data;
 215         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 216
 217         if (cmdid >= nvmeq->q_depth)
 218                 return CMD_CTX_INVALID;
 219         data = info[cmdid].ctx;
 220         info[cmdid].ctx = CMD_CTX_COMPLETED;
 221         clear_bit(cmdid, nvmeq->cmdid_data);
 222         wake_up(&nvmeq->sq_full);
 223         return data;
 224 }
 225
 226 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
 227 {
 228         unsigned long data;
 229         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 230         data = info[cmdid].ctx;
 231         info[cmdid].ctx = CMD_CTX_CANCELLED;
 232         return data;
 233 }
 234
 235 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 236 {
 237         return ns->dev->queues[get_cpu() + 1];
 238 }
 239
 240 static void put_nvmeq(struct nvme_queue *nvmeq)
 241 {
 242         put_cpu();
 243 }
 244
 245 /**
 246  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 247  * @nvmeq: The queue to use
 248  * @cmd: The command to send
 249  *
 250  * Safe to use from interrupt context
 251  */
 252 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 253 {
 254         unsigned long flags;
 255         u16 tail;
 256         spin_lock_irqsave(&nvmeq->q_lock, flags);
 257         tail = nvmeq->sq_tail;
 258         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 259         if (++tail == nvmeq->q_depth)
 260                 tail = 0;
 261         writel(tail, nvmeq->q_db);
 262         nvmeq->sq_tail = tail;
 263         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 264
 265         return 0;
 266 }
 267
 268 struct nvme_prps {
 269         int npages;             /* 0 means small pool in use */
 270         dma_addr_t first_dma;
 271         __le64 *list[0];
 272 };
 273
 274 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 275 {
 276         const int last_prp = PAGE_SIZE / 8 - 1;
 277         int i;
 278         dma_addr_t prp_dma;
 279
 280         if (!prps)
 281                 return;
 282
 283         prp_dma = prps->first_dma;
 284
 285         if (prps->npages == 0)
 286                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 287         for (i = 0; i < prps->npages; i++) {
 288                 __le64 *prp_list = prps->list[i];
 289                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 290                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 291                 prp_dma = next_prp_dma;
 292         }
 293         kfree(prps);
 294 }
 295
 296 struct nvme_bio {
 297         struct bio *bio;
 298         int nents;
 299         struct nvme_prps *prps;
 300         struct scatterlist sg[0];
 301 };
 302
 303 /* XXX: use a mempool */
 304 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 305 {
 306         return kzalloc(sizeof(struct nvme_bio) +
 307                         sizeof(struct scatterlist) * nseg, gfp);
 308 }
 309
 310 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 311 {
 312         nvme_free_prps(nvmeq->dev, nbio->prps);
 313         kfree(nbio);
 314 }
 315
 316 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 317                                                 struct nvme_completion *cqe)
 318 {
 319         struct nvme_bio *nbio = ctx;
 320         struct bio *bio = nbio->bio;
 321         u16 status = le16_to_cpup(&cqe->status) >> 1;
 322
 323         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 324                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 325         free_nbio(nvmeq, nbio);
 326         if (status) {
 327                 bio_endio(bio, -EIO);
 328         } else if (bio->bi_vcnt > bio->bi_idx) {
 329                 if (bio_list_empty(&nvmeq->sq_cong))
 330                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 331                 bio_list_add(&nvmeq->sq_cong, bio);
 332                 wake_up_process(nvme_thread);
 333         } else {
 334                 bio_endio(bio, 0);
 335         }
 336 }
 337
 338 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 339 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 340                                         struct nvme_common_command *cmd,
 341                                         struct scatterlist *sg, int *len,
 342                                         gfp_t gfp)
 343 {
 344         struct dma_pool *pool;
 345         int length = *len;
 346         int dma_len = sg_dma_len(sg);
 347         u64 dma_addr = sg_dma_address(sg);
 348         int offset = offset_in_page(dma_addr);
 349         __le64 *prp_list;
 350         dma_addr_t prp_dma;
 351         int nprps, npages, i;
 352         struct nvme_prps *prps = NULL;
 353
 354         cmd->prp1 = cpu_to_le64(dma_addr);
 355         length -= (PAGE_SIZE - offset);
 356         if (length <= 0)
 357                 return prps;
 358
 359         dma_len -= (PAGE_SIZE - offset);
 360         if (dma_len) {
 361                 dma_addr += (PAGE_SIZE - offset);
 362         } else {
 363                 sg = sg_next(sg);
 364                 dma_addr = sg_dma_address(sg);
 365                 dma_len = sg_dma_len(sg);
 366         }
 367
 368         if (length <= PAGE_SIZE) {
 369                 cmd->prp2 = cpu_to_le64(dma_addr);
 370                 return prps;
 371         }
 372
 373         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 374         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 375         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp);
 376         if (!prps) {
 377                 cmd->prp2 = cpu_to_le64(dma_addr);
 378                 *len = (*len - length) + PAGE_SIZE;
 379                 return prps;
 380         }
 381
 382         if (nprps <= (256 / 8)) {
 383                 pool = dev->prp_small_pool;
 384                 prps->npages = 0;
 385         } else {
 386                 pool = dev->prp_page_pool;
 387                 prps->npages = 1;
 388         }
 389
 390         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 391         if (!prp_list) {
 392                 cmd->prp2 = cpu_to_le64(dma_addr);
 393                 *len = (*len - length) + PAGE_SIZE;
 394                 kfree(prps);
 395                 return NULL;
 396         }
 397         prps->list[0] = prp_list;
 398         prps->first_dma = prp_dma;
 399         cmd->prp2 = cpu_to_le64(prp_dma);
 400         i = 0;
 401         for (;;) {
 402                 if (i == PAGE_SIZE / 8) {
 403                         __le64 *old_prp_list = prp_list;
 404                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 405                         if (!prp_list) {
 406                                 *len = (*len - length);
 407                                 return prps;
 408                         }
 409                         prps->list[prps->npages++] = prp_list;
 410                         prp_list[0] = old_prp_list[i - 1];
 411                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 412                         i = 1;
 413                 }
 414                 prp_list[i++] = cpu_to_le64(dma_addr);
 415                 dma_len -= PAGE_SIZE;
 416                 dma_addr += PAGE_SIZE;
 417                 length -= PAGE_SIZE;
 418                 if (length <= 0)
 419                         break;
 420                 if (dma_len > 0)
 421                         continue;
 422                 BUG_ON(dma_len < 0);
 423                 sg = sg_next(sg);
 424                 dma_addr = sg_dma_address(sg);
 425                 dma_len = sg_dma_len(sg);
 426         }
 427
 428         return prps;
 429 }
 430
 431 /* NVMe scatterlists require no holes in the virtual address */
 432 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 433                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 434
 435 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 436                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 437 {
 438         struct bio_vec *bvec, *bvprv = NULL;
 439         struct scatterlist *sg = NULL;
 440         int i, old_idx, length = 0, nsegs = 0;
 441
 442         sg_init_table(nbio->sg, psegs);
 443         old_idx = bio->bi_idx;
 444         bio_for_each_segment(bvec, bio, i) {
 445                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 446                         sg->length += bvec->bv_len;
 447                 } else {
 448                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 449                                 break;
 450                         sg = sg ? sg + 1 : nbio->sg;
 451                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 452                                                         bvec->bv_offset);
 453                         nsegs++;
 454                 }
 455                 length += bvec->bv_len;
 456                 bvprv = bvec;
 457         }
 458         bio->bi_idx = i;
 459         nbio->nents = nsegs;
 460         sg_mark_end(sg);
 461         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 462                 bio->bi_idx = old_idx;
 463                 return -ENOMEM;
 464         }
 465         return length;
 466 }
 467
 468 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 469                                                                 int cmdid)
 470 {
 471         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 472
 473         memset(cmnd, 0, sizeof(*cmnd));
 474         cmnd->common.opcode = nvme_cmd_flush;
 475         cmnd->common.command_id = cmdid;
 476         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 477
 478         if (++nvmeq->sq_tail == nvmeq->q_depth)
 479                 nvmeq->sq_tail = 0;
 480         writel(nvmeq->sq_tail, nvmeq->q_db);
 481
 482         return 0;
 483 }
 484
 485 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 486 {
 487         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 488                                                 sync_completion_id, IO_TIMEOUT);
 489         if (unlikely(cmdid < 0))
 490                 return cmdid;
 491
 492         return nvme_submit_flush(nvmeq, ns, cmdid);
 493 }
 494
 495 /*
 496  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 497  */
 498 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 499                                                                 struct bio *bio)
 500 {
 501         struct nvme_command *cmnd;
 502         struct nvme_bio *nbio;
 503         enum dma_data_direction dma_dir;
 504         int cmdid, length, result = -ENOMEM;
 505         u16 control;
 506         u32 dsmgmt;
 507         int psegs = bio_phys_segments(ns->queue, bio);
 508
 509         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 510                 result = nvme_submit_flush_data(nvmeq, ns);
 511                 if (result)
 512                         return result;
 513         }
 514
 515         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 516         if (!nbio)
 517                 goto nomem;
 518         nbio->bio = bio;
 519
 520         result = -EBUSY;
 521         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 522         if (unlikely(cmdid < 0))
 523                 goto free_nbio;
 524
 525         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 526                 return nvme_submit_flush(nvmeq, ns, cmdid);
 527
 528         control = 0;
 529         if (bio->bi_rw & REQ_FUA)
 530                 control |= NVME_RW_FUA;
 531         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 532                 control |= NVME_RW_LR;
 533
 534         dsmgmt = 0;
 535         if (bio->bi_rw & REQ_RAHEAD)
 536                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 537
 538         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 539
 540         memset(cmnd, 0, sizeof(*cmnd));
 541         if (bio_data_dir(bio)) {
 542                 cmnd->rw.opcode = nvme_cmd_write;
 543                 dma_dir = DMA_TO_DEVICE;
 544         } else {
 545                 cmnd->rw.opcode = nvme_cmd_read;
 546                 dma_dir = DMA_FROM_DEVICE;
 547         }
 548
 549         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 550         if (result < 0)
 551                 goto free_nbio;
 552         length = result;
 553
 554         cmnd->rw.command_id = cmdid;
 555         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 556         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 557                                                         &length, GFP_ATOMIC);
 558         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 559         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 560         cmnd->rw.control = cpu_to_le16(control);
 561         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 562
 563         bio->bi_sector += length >> 9;
 564
 565         if (++nvmeq->sq_tail == nvmeq->q_depth)
 566                 nvmeq->sq_tail = 0;
 567         writel(nvmeq->sq_tail, nvmeq->q_db);
 568
 569         return 0;
 570
 571  free_nbio:
 572         free_nbio(nvmeq, nbio);
 573  nomem:
 574         return result;
 575 }
 576
 577 /*
 578  * NB: return value of non-zero would mean that we were a stacking driver.
 579  * make_request must always succeed.
 580  */
 581 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 582 {
 583         struct nvme_ns *ns = q->queuedata;
 584         struct nvme_queue *nvmeq = get_nvmeq(ns);
 585         int result = -EBUSY;
 586
 587         spin_lock_irq(&nvmeq->q_lock);
 588         if (bio_list_empty(&nvmeq->sq_cong))
 589                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 590         if (unlikely(result)) {
 591                 if (bio_list_empty(&nvmeq->sq_cong))
 592                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 593                 bio_list_add(&nvmeq->sq_cong, bio);
 594         }
 595
 596         spin_unlock_irq(&nvmeq->q_lock);
 597         put_nvmeq(nvmeq);
 598
 599         return 0;
 600 }
 601
 602 struct sync_cmd_info {
 603         struct task_struct *task;
 604         u32 result;
 605         int status;
 606 };
 607
 608 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 609                                                 struct nvme_completion *cqe)
 610 {
 611         struct sync_cmd_info *cmdinfo = ctx;
 612         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 613                 return;
 614         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 615                 return;
 616         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 617                 dev_warn(nvmeq->q_dmadev,
 618                                 "completed id %d twice on queue %d\n",
 619                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 620                 return;
 621         }
 622         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 623                 dev_warn(nvmeq->q_dmadev,
 624                                 "invalid id %d completed on queue %d\n",
 625                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 626                 return;
 627         }
 628         cmdinfo->result = le32_to_cpup(&cqe->result);
 629         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 630         wake_up_process(cmdinfo->task);
 631 }
 632
 633 typedef void (*completion_fn)(struct nvme_queue *, void *,
 634                                                 struct nvme_completion *);
 635
 636 static const completion_fn nvme_completions[4] = {
 637         [sync_completion_id] = sync_completion,
 638         [bio_completion_id]  = bio_completion,
 639 };
 640
 641 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 642 {
 643         u16 head, phase;
 644
 645         head = nvmeq->cq_head;
 646         phase = nvmeq->cq_phase;
 647
 648         for (;;) {
 649                 unsigned long data;
 650                 void *ptr;
 651                 unsigned char handler;
 652                 struct nvme_completion cqe = nvmeq->cqes[head];
 653                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 654                         break;
 655                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 656                 if (++head == nvmeq->q_depth) {
 657                         head = 0;
 658                         phase = !phase;
 659                 }
 660
 661                 data = free_cmdid(nvmeq, cqe.command_id);
 662                 handler = data & 3;
 663                 ptr = (void *)(data & ~3UL);
 664                 nvme_completions[handler](nvmeq, ptr, &cqe);
 665         }
 666
 667         /* If the controller ignores the cq head doorbell and continuously
 668          * writes to the queue, it is theoretically possible to wrap around
 669          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 670          * requires that 0.1% of your interrupts are handled, so this isn't
 671          * a big problem.
 672          */
 673         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 674                 return IRQ_NONE;
 675
 676         writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
 677         nvmeq->cq_head = head;
 678         nvmeq->cq_phase = phase;
 679
 680         return IRQ_HANDLED;
 681 }
 682
 683 static irqreturn_t nvme_irq(int irq, void *data)
 684 {
 685         irqreturn_t result;
 686         struct nvme_queue *nvmeq = data;
 687         spin_lock(&nvmeq->q_lock);
 688         result = nvme_process_cq(nvmeq);
 689         spin_unlock(&nvmeq->q_lock);
 690         return result;
 691 }
 692
 693 static irqreturn_t nvme_irq_check(int irq, void *data)
 694 {
 695         struct nvme_queue *nvmeq = data;
 696         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 697         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 698                 return IRQ_NONE;
 699         return IRQ_WAKE_THREAD;
 700 }
 701
 702 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 703 {
 704         spin_lock_irq(&nvmeq->q_lock);
 705         cancel_cmdid(nvmeq, cmdid);
 706         spin_unlock_irq(&nvmeq->q_lock);
 707 }
 708
 709 /*
 710  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 711  * if the result is positive, it's an NVM Express status code
 712  */
 713 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 714                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 715 {
 716         int cmdid;
 717         struct sync_cmd_info cmdinfo;
 718
 719         cmdinfo.task = current;
 720         cmdinfo.status = -EINTR;
 721
 722         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 723                                                                 timeout);
 724         if (cmdid < 0)
 725                 return cmdid;
 726         cmd->common.command_id = cmdid;
 727
 728         set_current_state(TASK_KILLABLE);
 729         nvme_submit_cmd(nvmeq, cmd);
 730         schedule();
 731
 732         if (cmdinfo.status == -EINTR) {
 733                 nvme_abort_command(nvmeq, cmdid);
 734                 return -EINTR;
 735         }
 736
 737         if (result)
 738                 *result = cmdinfo.result;
 739
 740         return cmdinfo.status;
 741 }
 742
 743 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 744                                                                 u32 *result)
 745 {
 746         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 747 }
 748
 749 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 750 {
 751         int status;
 752         struct nvme_command c;
 753
 754         memset(&c, 0, sizeof(c));
 755         c.delete_queue.opcode = opcode;
 756         c.delete_queue.qid = cpu_to_le16(id);
 757
 758         status = nvme_submit_admin_cmd(dev, &c, NULL);
 759         if (status)
 760                 return -EIO;
 761         return 0;
 762 }
 763
 764 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 765                                                 struct nvme_queue *nvmeq)
 766 {
 767         int status;
 768         struct nvme_command c;
 769         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 770
 771         memset(&c, 0, sizeof(c));
 772         c.create_cq.opcode = nvme_admin_create_cq;
 773         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 774         c.create_cq.cqid = cpu_to_le16(qid);
 775         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 776         c.create_cq.cq_flags = cpu_to_le16(flags);
 777         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 778
 779         status = nvme_submit_admin_cmd(dev, &c, NULL);
 780         if (status)
 781                 return -EIO;
 782         return 0;
 783 }
 784
 785 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 786                                                 struct nvme_queue *nvmeq)
 787 {
 788         int status;
 789         struct nvme_command c;
 790         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 791
 792         memset(&c, 0, sizeof(c));
 793         c.create_sq.opcode = nvme_admin_create_sq;
 794         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 795         c.create_sq.sqid = cpu_to_le16(qid);
 796         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 797         c.create_sq.sq_flags = cpu_to_le16(flags);
 798         c.create_sq.cqid = cpu_to_le16(qid);
 799
 800         status = nvme_submit_admin_cmd(dev, &c, NULL);
 801         if (status)
 802                 return -EIO;
 803         return 0;
 804 }
 805
 806 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 807 {
 808         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 809 }
 810
 811 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 812 {
 813         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 814 }
 815
 816 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
 817                                                         dma_addr_t dma_addr)
 818 {
 819         struct nvme_command c;
 820
 821         memset(&c, 0, sizeof(c));
 822         c.identify.opcode = nvme_admin_identify;
 823         c.identify.nsid = cpu_to_le32(nsid);
 824         c.identify.prp1 = cpu_to_le64(dma_addr);
 825         c.identify.cns = cpu_to_le32(cns);
 826
 827         return nvme_submit_admin_cmd(dev, &c, NULL);
 828 }
 829
 830 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
 831                         unsigned dword11, dma_addr_t dma_addr, u32 *result)
 832 {
 833         struct nvme_command c;
 834
 835         memset(&c, 0, sizeof(c));
 836         c.features.opcode = nvme_admin_get_features;
 837         c.features.prp1 = cpu_to_le64(dma_addr);
 838         c.features.fid = cpu_to_le32(fid);
 839         c.features.dword11 = cpu_to_le32(dword11);
 840
 841         return nvme_submit_admin_cmd(dev, &c, result);
 842 }
 843
 844 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 845 {
 846         struct nvme_queue *nvmeq = dev->queues[qid];
 847         int vector = dev->entry[nvmeq->cq_vector].vector;
 848
 849         irq_set_affinity_hint(vector, NULL);
 850         free_irq(vector, nvmeq);
 851
 852         /* Don't tell the adapter to delete the admin queue */
 853         if (qid) {
 854                 adapter_delete_sq(dev, qid);
 855                 adapter_delete_cq(dev, qid);
 856         }
 857
 858         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 859                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 860         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 861                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 862         kfree(nvmeq);
 863 }
 864
 865 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 866                                                         int depth, int vector)
 867 {
 868         struct device *dmadev = &dev->pci_dev->dev;
 869         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 870         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 871         if (!nvmeq)
 872                 return NULL;
 873
 874         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 875                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 876         if (!nvmeq->cqes)
 877                 goto free_nvmeq;
 878         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 879
 880         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 881                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 882         if (!nvmeq->sq_cmds)
 883                 goto free_cqdma;
 884
 885         nvmeq->q_dmadev = dmadev;
 886         nvmeq->dev = dev;
 887         spin_lock_init(&nvmeq->q_lock);
 888         nvmeq->cq_head = 0;
 889         nvmeq->cq_phase = 1;
 890         init_waitqueue_head(&nvmeq->sq_full);
 891         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 892         bio_list_init(&nvmeq->sq_cong);
 893         nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
 894         nvmeq->q_depth = depth;
 895         nvmeq->cq_vector = vector;
 896
 897         return nvmeq;
 898
 899  free_cqdma:
 900         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 901                                                         nvmeq->cq_dma_addr);
 902  free_nvmeq:
 903         kfree(nvmeq);
 904         return NULL;
 905 }
 906
 907 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 908                                                         const char *name)
 909 {
 910         if (use_threaded_interrupts)
 911                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 912                                         nvme_irq_check, nvme_irq,
 913                                         IRQF_DISABLED | IRQF_SHARED,
 914                                         name, nvmeq);
 915         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 916                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 917 }
 918
 919 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 920                                         int qid, int cq_size, int vector)
 921 {
 922         int result;
 923         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 924
 925         if (!nvmeq)
 926                 return ERR_PTR(-ENOMEM);
 927
 928         result = adapter_alloc_cq(dev, qid, nvmeq);
 929         if (result < 0)
 930                 goto free_nvmeq;
 931
 932         result = adapter_alloc_sq(dev, qid, nvmeq);
 933         if (result < 0)
 934                 goto release_cq;
 935
 936         result = queue_request_irq(dev, nvmeq, "nvme");
 937         if (result < 0)
 938                 goto release_sq;
 939
 940         return nvmeq;
 941
 942  release_sq:
 943         adapter_delete_sq(dev, qid);
 944  release_cq:
 945         adapter_delete_cq(dev, qid);
 946  free_nvmeq:
 947         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 948                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 949         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 950                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 951         kfree(nvmeq);
 952         return ERR_PTR(result);
 953 }
 954
 955 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 956 {
 957         int result;
 958         u32 aqa;
 959         u64 cap;
 960         unsigned long timeout;
 961         struct nvme_queue *nvmeq;
 962
 963         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 964
 965         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 966         if (!nvmeq)
 967                 return -ENOMEM;
 968
 969         aqa = nvmeq->q_depth - 1;
 970         aqa |= aqa << 16;
 971
 972         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 973         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 974         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 975         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 976
 977         writel(0, &dev->bar->cc);
 978         writel(aqa, &dev->bar->aqa);
 979         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 980         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 981         writel(dev->ctrl_config, &dev->bar->cc);
 982
 983         cap = readq(&dev->bar->cap);
 984         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
 985         dev->db_stride = NVME_CAP_STRIDE(cap);
 986
 987         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 988                 msleep(100);
 989                 if (fatal_signal_pending(current))
 990                         return -EINTR;
 991                 if (time_after(jiffies, timeout)) {
 992                         dev_err(&dev->pci_dev->dev,
 993                                 "Device not ready; aborting initialisation\n");
 994                         return -ENODEV;
 995                 }
 996         }
 997
 998         result = queue_request_irq(dev, nvmeq, "nvme admin");
 999         dev->queues[0] = nvmeq;
1000         return result;
1001 }
1002
1003 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
1004                                 unsigned long addr, unsigned length,
1005                                 struct scatterlist **sgp)
1006 {
1007         int i, err, count, nents, offset;
1008         struct scatterlist *sg;
1009         struct page **pages;
1010
1011         if (addr & 3)
1012                 return -EINVAL;
1013         if (!length)
1014                 return -EINVAL;
1015
1016         offset = offset_in_page(addr);
1017         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1018         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1019
1020         err = get_user_pages_fast(addr, count, 1, pages);
1021         if (err < count) {
1022                 count = err;
1023                 err = -EFAULT;
1024                 goto put_pages;
1025         }
1026
1027         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
1028         sg_init_table(sg, count);
1029         for (i = 0; i < count; i++) {
1030                 sg_set_page(&sg[i], pages[i],
1031                                 min_t(int, length, PAGE_SIZE - offset), offset);
1032                 length -= (PAGE_SIZE - offset);
1033                 offset = 0;
1034         }
1035
1036         err = -ENOMEM;
1037         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1038                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1039         if (!nents)
1040                 goto put_pages;
1041
1042         kfree(pages);
1043         *sgp = sg;
1044         return nents;
1045
1046  put_pages:
1047         for (i = 0; i < count; i++)
1048                 put_page(pages[i]);
1049         kfree(pages);
1050         return err;
1051 }
1052
1053 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1054                         unsigned long addr, int length, struct scatterlist *sg)
1055 {
1056         int i, count;
1057
1058         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1059         dma_unmap_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE);
1060
1061         for (i = 0; i < count; i++)
1062                 put_page(sg_page(&sg[i]));
1063 }
1064
1065 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1066 {
1067         struct nvme_dev *dev = ns->dev;
1068         struct nvme_queue *nvmeq;
1069         struct nvme_user_io io;
1070         struct nvme_command c;
1071         unsigned length;
1072         int nents, status;
1073         struct scatterlist *sg;
1074         struct nvme_prps *prps;
1075
1076         if (copy_from_user(&io, uio, sizeof(io)))
1077                 return -EFAULT;
1078         length = (io.nblocks + 1) << ns->lba_shift;
1079
1080         switch (io.opcode) {
1081         case nvme_cmd_write:
1082         case nvme_cmd_read:
1083         case nvme_cmd_compare:
1084                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1085                                                                 length, &sg);
1086                 break;
1087         default:
1088                 return -EINVAL;
1089         }
1090
1091         if (nents < 0)
1092                 return nents;
1093
1094         memset(&c, 0, sizeof(c));
1095         c.rw.opcode = io.opcode;
1096         c.rw.flags = io.flags;
1097         c.rw.nsid = cpu_to_le32(ns->ns_id);
1098         c.rw.slba = cpu_to_le64(io.slba);
1099         c.rw.length = cpu_to_le16(io.nblocks);
1100         c.rw.control = cpu_to_le16(io.control);
1101         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1102         c.rw.reftag = io.reftag;
1103         c.rw.apptag = io.apptag;
1104         c.rw.appmask = io.appmask;
1105         /* XXX: metadata */
1106         prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1107
1108         nvmeq = get_nvmeq(ns);
1109         /*
1110          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1111          * disabled.  We may be preempted at any point, and be rescheduled
1112          * to a different CPU.  That will cause cacheline bouncing, but no
1113          * additional races since q_lock already protects against other CPUs.
1114          */
1115         put_nvmeq(nvmeq);
1116         if (length != (io.nblocks + 1) << ns->lba_shift)
1117                 status = -ENOMEM;
1118         else
1119                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1120
1121         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg);
1122         nvme_free_prps(dev, prps);
1123         return status;
1124 }
1125
1126 static int nvme_user_admin_cmd(struct nvme_ns *ns,
1127                                         struct nvme_admin_cmd __user *ucmd)
1128 {
1129         struct nvme_dev *dev = ns->dev;
1130         struct nvme_admin_cmd cmd;
1131         struct nvme_command c;
1132         int status, length, nents = 0;
1133         struct scatterlist *sg;
1134         struct nvme_prps *prps = NULL;
1135
1136         if (!capable(CAP_SYS_ADMIN))
1137                 return -EACCES;
1138         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1139                 return -EFAULT;
1140
1141         memset(&c, 0, sizeof(c));
1142         c.common.opcode = cmd.opcode;
1143         c.common.flags = cmd.flags;
1144         c.common.nsid = cpu_to_le32(cmd.nsid);
1145         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1146         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1147         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1148         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1149         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1150         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1151         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1152         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1153
1154         length = cmd.data_len;
1155         if (cmd.data_len) {
1156                 nents = nvme_map_user_pages(dev, 1, cmd.addr, length, &sg);
1157                 if (nents < 0)
1158                         return nents;
1159                 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1160         }
1161
1162         if (length != cmd.data_len)
1163                 status = -ENOMEM;
1164         else
1165                 status = nvme_submit_admin_cmd(dev, &c, NULL);
1166         if (cmd.data_len) {
1167                 nvme_unmap_user_pages(dev, 0, cmd.addr, cmd.data_len, sg);
1168                 nvme_free_prps(dev, prps);
1169         }
1170         return status;
1171 }
1172
1173 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1174                                                         unsigned long arg)
1175 {
1176         struct nvme_ns *ns = bdev->bd_disk->private_data;
1177
1178         switch (cmd) {
1179         case NVME_IOCTL_ID:
1180                 return ns->ns_id;
1181         case NVME_IOCTL_ADMIN_CMD:
1182                 return nvme_user_admin_cmd(ns, (void __user *)arg);
1183         case NVME_IOCTL_SUBMIT_IO:
1184                 return nvme_submit_io(ns, (void __user *)arg);
1185         default:
1186                 return -ENOTTY;
1187         }
1188 }
1189
1190 static const struct block_device_operations nvme_fops = {
1191         .owner          = THIS_MODULE,
1192         .ioctl          = nvme_ioctl,
1193         .compat_ioctl   = nvme_ioctl,
1194 };
1195
1196 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1197 {
1198         int depth = nvmeq->q_depth - 1;
1199         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1200         unsigned long now = jiffies;
1201         int cmdid;
1202
1203         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1204                 unsigned long data;
1205                 void *ptr;
1206                 unsigned char handler;
1207                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1208
1209                 if (!time_after(now, info[cmdid].timeout))
1210                         continue;
1211                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1212                 data = cancel_cmdid(nvmeq, cmdid);
1213                 handler = data & 3;
1214                 ptr = (void *)(data & ~3UL);
1215                 nvme_completions[handler](nvmeq, ptr, &cqe);
1216         }
1217 }
1218
1219 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1220 {
1221         while (bio_list_peek(&nvmeq->sq_cong)) {
1222                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1223                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1224                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1225                         bio_list_add_head(&nvmeq->sq_cong, bio);
1226                         break;
1227                 }
1228                 if (bio_list_empty(&nvmeq->sq_cong))
1229                         remove_wait_queue(&nvmeq->sq_full,
1230                                                         &nvmeq->sq_cong_wait);
1231         }
1232 }
1233
1234 static int nvme_kthread(void *data)
1235 {
1236         struct nvme_dev *dev;
1237
1238         while (!kthread_should_stop()) {
1239                 __set_current_state(TASK_RUNNING);
1240                 spin_lock(&dev_list_lock);
1241                 list_for_each_entry(dev, &dev_list, node) {
1242                         int i;
1243                         for (i = 0; i < dev->queue_count; i++) {
1244                                 struct nvme_queue *nvmeq = dev->queues[i];
1245                                 if (!nvmeq)
1246                                         continue;
1247                                 spin_lock_irq(&nvmeq->q_lock);
1248                                 if (nvme_process_cq(nvmeq))
1249                                         printk("process_cq did something\n");
1250                                 nvme_timeout_ios(nvmeq);
1251                                 nvme_resubmit_bios(nvmeq);
1252                                 spin_unlock_irq(&nvmeq->q_lock);
1253                         }
1254                 }
1255                 spin_unlock(&dev_list_lock);
1256                 set_current_state(TASK_INTERRUPTIBLE);
1257                 schedule_timeout(HZ);
1258         }
1259         return 0;
1260 }
1261
1262 static DEFINE_IDA(nvme_index_ida);
1263
1264 static int nvme_get_ns_idx(void)
1265 {
1266         int index, error;
1267
1268         do {
1269                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1270                         return -1;
1271
1272                 spin_lock(&dev_list_lock);
1273                 error = ida_get_new(&nvme_index_ida, &index);
1274                 spin_unlock(&dev_list_lock);
1275         } while (error == -EAGAIN);
1276
1277         if (error)
1278                 index = -1;
1279         return index;
1280 }
1281
1282 static void nvme_put_ns_idx(int index)
1283 {
1284         spin_lock(&dev_list_lock);
1285         ida_remove(&nvme_index_ida, index);
1286         spin_unlock(&dev_list_lock);
1287 }
1288
1289 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1290                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1291 {
1292         struct nvme_ns *ns;
1293         struct gendisk *disk;
1294         int lbaf;
1295
1296         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1297                 return NULL;
1298
1299         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1300         if (!ns)
1301                 return NULL;
1302         ns->queue = blk_alloc_queue(GFP_KERNEL);
1303         if (!ns->queue)
1304                 goto out_free_ns;
1305         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1306                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1307         blk_queue_make_request(ns->queue, nvme_make_request);
1308         ns->dev = dev;
1309         ns->queue->queuedata = ns;
1310
1311         disk = alloc_disk(NVME_MINORS);
1312         if (!disk)
1313                 goto out_free_queue;
1314         ns->ns_id = nsid;
1315         ns->disk = disk;
1316         lbaf = id->flbas & 0xf;
1317         ns->lba_shift = id->lbaf[lbaf].ds;
1318
1319         disk->major = nvme_major;
1320         disk->minors = NVME_MINORS;
1321         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1322         disk->fops = &nvme_fops;
1323         disk->private_data = ns;
1324         disk->queue = ns->queue;
1325         disk->driverfs_dev = &dev->pci_dev->dev;
1326         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1327         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1328
1329         return ns;
1330
1331  out_free_queue:
1332         blk_cleanup_queue(ns->queue);
1333  out_free_ns:
1334         kfree(ns);
1335         return NULL;
1336 }
1337
1338 static void nvme_ns_free(struct nvme_ns *ns)
1339 {
1340         int index = ns->disk->first_minor / NVME_MINORS;
1341         put_disk(ns->disk);
1342         nvme_put_ns_idx(index);
1343         blk_cleanup_queue(ns->queue);
1344         kfree(ns);
1345 }
1346
1347 static int set_queue_count(struct nvme_dev *dev, int count)
1348 {
1349         int status;
1350         u32 result;
1351         u32 q_count = (count - 1) | ((count - 1) << 16);
1352
1353         status = nvme_get_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1354                                                                 &result);
1355         if (status)
1356                 return -EIO;
1357         return min(result & 0xffff, result >> 16) + 1;
1358 }
1359
1360 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1361 {
1362         int result, cpu, i, nr_io_queues, db_bar_size;
1363
1364         nr_io_queues = num_online_cpus();
1365         result = set_queue_count(dev, nr_io_queues);
1366         if (result < 0)
1367                 return result;
1368         if (result < nr_io_queues)
1369                 nr_io_queues = result;
1370
1371         /* Deregister the admin queue's interrupt */
1372         free_irq(dev->entry[0].vector, dev->queues[0]);
1373
1374         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1375         if (db_bar_size > 8192) {
1376                 iounmap(dev->bar);
1377                 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1378                                                                 db_bar_size);
1379                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1380                 dev->queues[0]->q_db = dev->dbs;
1381         }
1382
1383         for (i = 0; i < nr_io_queues; i++)
1384                 dev->entry[i].entry = i;
1385         for (;;) {
1386                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1387                                                                 nr_io_queues);
1388                 if (result == 0) {
1389                         break;
1390                 } else if (result > 0) {
1391                         nr_io_queues = result;
1392                         continue;
1393                 } else {
1394                         nr_io_queues = 1;
1395                         break;
1396                 }
1397         }
1398
1399         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1400         /* XXX: handle failure here */
1401
1402         cpu = cpumask_first(cpu_online_mask);
1403         for (i = 0; i < nr_io_queues; i++) {
1404                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1405                 cpu = cpumask_next(cpu, cpu_online_mask);
1406         }
1407
1408         for (i = 0; i < nr_io_queues; i++) {
1409                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1410                                                         NVME_Q_DEPTH, i);
1411                 if (IS_ERR(dev->queues[i + 1]))
1412                         return PTR_ERR(dev->queues[i + 1]);
1413                 dev->queue_count++;
1414         }
1415
1416         for (; i < num_possible_cpus(); i++) {
1417                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1418                 dev->queues[i + 1] = dev->queues[target + 1];
1419         }
1420
1421         return 0;
1422 }
1423
1424 static void nvme_free_queues(struct nvme_dev *dev)
1425 {
1426         int i;
1427
1428         for (i = dev->queue_count - 1; i >= 0; i--)
1429                 nvme_free_queue(dev, i);
1430 }
1431
1432 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1433 {
1434         int res, nn, i;
1435         struct nvme_ns *ns, *next;
1436         struct nvme_id_ctrl *ctrl;
1437         struct nvme_id_ns *id_ns;
1438         void *mem;
1439         dma_addr_t dma_addr;
1440
1441         res = nvme_setup_io_queues(dev);
1442         if (res)
1443                 return res;
1444
1445         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1446                                                                 GFP_KERNEL);
1447
1448         res = nvme_identify(dev, 0, 1, dma_addr);
1449         if (res) {
1450                 res = -EIO;
1451                 goto out_free;
1452         }
1453
1454         ctrl = mem;
1455         nn = le32_to_cpup(&ctrl->nn);
1456         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1457         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1458         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1459
1460         id_ns = mem;
1461         for (i = 1; i <= nn; i++) {
1462                 res = nvme_identify(dev, i, 0, dma_addr);
1463                 if (res)
1464                         continue;
1465
1466                 if (id_ns->ncap == 0)
1467                         continue;
1468
1469                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1470                                                         dma_addr + 4096, NULL);
1471                 if (res)
1472                         continue;
1473
1474                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1475                 if (ns)
1476                         list_add_tail(&ns->list, &dev->namespaces);
1477         }
1478         list_for_each_entry(ns, &dev->namespaces, list)
1479                 add_disk(ns->disk);
1480
1481         goto out;
1482
1483  out_free:
1484         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1485                 list_del(&ns->list);
1486                 nvme_ns_free(ns);
1487         }
1488
1489  out:
1490         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1491         return res;
1492 }
1493
1494 static int nvme_dev_remove(struct nvme_dev *dev)
1495 {
1496         struct nvme_ns *ns, *next;
1497
1498         spin_lock(&dev_list_lock);
1499         list_del(&dev->node);
1500         spin_unlock(&dev_list_lock);
1501
1502         /* TODO: wait all I/O finished or cancel them */
1503
1504         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1505                 list_del(&ns->list);
1506                 del_gendisk(ns->disk);
1507                 nvme_ns_free(ns);
1508         }
1509
1510         nvme_free_queues(dev);
1511
1512         return 0;
1513 }
1514
1515 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1516 {
1517         struct device *dmadev = &dev->pci_dev->dev;
1518         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1519                                                 PAGE_SIZE, PAGE_SIZE, 0);
1520         if (!dev->prp_page_pool)
1521                 return -ENOMEM;
1522
1523         /* Optimisation for I/Os between 4k and 128k */
1524         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1525                                                 256, 256, 0);
1526         if (!dev->prp_small_pool) {
1527                 dma_pool_destroy(dev->prp_page_pool);
1528                 return -ENOMEM;
1529         }
1530         return 0;
1531 }
1532
1533 static void nvme_release_prp_pools(struct nvme_dev *dev)
1534 {
1535         dma_pool_destroy(dev->prp_page_pool);
1536         dma_pool_destroy(dev->prp_small_pool);
1537 }
1538
1539 /* XXX: Use an ida or something to let remove / add work correctly */
1540 static void nvme_set_instance(struct nvme_dev *dev)
1541 {
1542         static int instance;
1543         dev->instance = instance++;
1544 }
1545
1546 static void nvme_release_instance(struct nvme_dev *dev)
1547 {
1548 }
1549
1550 static int __devinit nvme_probe(struct pci_dev *pdev,
1551                                                 const struct pci_device_id *id)
1552 {
1553         int bars, result = -ENOMEM;
1554         struct nvme_dev *dev;
1555
1556         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1557         if (!dev)
1558                 return -ENOMEM;
1559         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1560                                                                 GFP_KERNEL);
1561         if (!dev->entry)
1562                 goto free;
1563         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1564                                                                 GFP_KERNEL);
1565         if (!dev->queues)
1566                 goto free;
1567
1568         if (pci_enable_device_mem(pdev))
1569                 goto free;
1570         pci_set_master(pdev);
1571         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1572         if (pci_request_selected_regions(pdev, bars, "nvme"))
1573                 goto disable;
1574
1575         INIT_LIST_HEAD(&dev->namespaces);
1576         dev->pci_dev = pdev;
1577         pci_set_drvdata(pdev, dev);
1578         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1579         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1580         nvme_set_instance(dev);
1581         dev->entry[0].vector = pdev->irq;
1582
1583         result = nvme_setup_prp_pools(dev);
1584         if (result)
1585                 goto disable_msix;
1586
1587         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1588         if (!dev->bar) {
1589                 result = -ENOMEM;
1590                 goto disable_msix;
1591         }
1592
1593         result = nvme_configure_admin_queue(dev);
1594         if (result)
1595                 goto unmap;
1596         dev->queue_count++;
1597
1598         spin_lock(&dev_list_lock);
1599         list_add(&dev->node, &dev_list);
1600         spin_unlock(&dev_list_lock);
1601
1602         result = nvme_dev_add(dev);
1603         if (result)
1604                 goto delete;
1605
1606         return 0;
1607
1608  delete:
1609         spin_lock(&dev_list_lock);
1610         list_del(&dev->node);
1611         spin_unlock(&dev_list_lock);
1612
1613         nvme_free_queues(dev);
1614  unmap:
1615         iounmap(dev->bar);
1616  disable_msix:
1617         pci_disable_msix(pdev);
1618         nvme_release_instance(dev);
1619         nvme_release_prp_pools(dev);
1620  disable:
1621         pci_disable_device(pdev);
1622         pci_release_regions(pdev);
1623  free:
1624         kfree(dev->queues);
1625         kfree(dev->entry);
1626         kfree(dev);
1627         return result;
1628 }
1629
1630 static void __devexit nvme_remove(struct pci_dev *pdev)
1631 {
1632         struct nvme_dev *dev = pci_get_drvdata(pdev);
1633         nvme_dev_remove(dev);
1634         pci_disable_msix(pdev);
1635         iounmap(dev->bar);
1636         nvme_release_instance(dev);
1637         nvme_release_prp_pools(dev);
1638         pci_disable_device(pdev);
1639         pci_release_regions(pdev);
1640         kfree(dev->queues);
1641         kfree(dev->entry);
1642         kfree(dev);
1643 }
1644
1645 /* These functions are yet to be implemented */
1646 #define nvme_error_detected NULL
1647 #define nvme_dump_registers NULL
1648 #define nvme_link_reset NULL
1649 #define nvme_slot_reset NULL
1650 #define nvme_error_resume NULL
1651 #define nvme_suspend NULL
1652 #define nvme_resume NULL
1653
1654 static struct pci_error_handlers nvme_err_handler = {
1655         .error_detected = nvme_error_detected,
1656         .mmio_enabled   = nvme_dump_registers,
1657         .link_reset     = nvme_link_reset,
1658         .slot_reset     = nvme_slot_reset,
1659         .resume         = nvme_error_resume,
1660 };
1661
1662 /* Move to pci_ids.h later */
1663 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1664
1665 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1666         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1667         { 0, }
1668 };
1669 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1670
1671 static struct pci_driver nvme_driver = {
1672         .name           = "nvme",
1673         .id_table       = nvme_id_table,
1674         .probe          = nvme_probe,
1675         .remove         = __devexit_p(nvme_remove),
1676         .suspend        = nvme_suspend,
1677         .resume         = nvme_resume,
1678         .err_handler    = &nvme_err_handler,
1679 };
1680
1681 static int __init nvme_init(void)
1682 {
1683         int result = -EBUSY;
1684
1685         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1686         if (IS_ERR(nvme_thread))
1687                 return PTR_ERR(nvme_thread);
1688
1689         nvme_major = register_blkdev(nvme_major, "nvme");
1690         if (nvme_major <= 0)
1691                 goto kill_kthread;
1692
1693         result = pci_register_driver(&nvme_driver);
1694         if (result)
1695                 goto unregister_blkdev;
1696         return 0;
1697
1698  unregister_blkdev:
1699         unregister_blkdev(nvme_major, "nvme");
1700  kill_kthread:
1701         kthread_stop(nvme_thread);
1702         return result;
1703 }
1704
1705 static void __exit nvme_exit(void)
1706 {
1707         pci_unregister_driver(&nvme_driver);
1708         unregister_blkdev(nvme_major, "nvme");
1709         kthread_stop(nvme_thread);
1710 }
1711
1712 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1713 MODULE_LICENSE("GPL");
1714 MODULE_VERSION("0.7");
1715 module_init(nvme_init);
1716 module_exit(nvme_exit);