drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44
  45 static int nvme_major;
  46 module_param(nvme_major, int, 0);
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0);
  50
  51 /*
  52  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  53  */
  54 struct nvme_dev {
  55         struct nvme_queue **queues;
  56         u32 __iomem *dbs;
  57         struct pci_dev *pci_dev;
  58         int instance;
  59         int queue_count;
  60         u32 ctrl_config;
  61         struct msix_entry *entry;
  62         struct nvme_bar __iomem *bar;
  63         struct list_head namespaces;
  64         char serial[20];
  65         char model[40];
  66         char firmware_rev[8];
  67 };
  68
  69 /*
  70  * An NVM Express namespace is equivalent to a SCSI LUN
  71  */
  72 struct nvme_ns {
  73         struct list_head list;
  74
  75         struct nvme_dev *dev;
  76         struct request_queue *queue;
  77         struct gendisk *disk;
  78
  79         int ns_id;
  80         int lba_shift;
  81 };
  82
  83 /*
  84  * An NVM Express queue.  Each device has at least two (one for admin
  85  * commands and one for I/O commands).
  86  */
  87 struct nvme_queue {
  88         struct device *q_dmadev;
  89         spinlock_t q_lock;
  90         struct nvme_command *sq_cmds;
  91         volatile struct nvme_completion *cqes;
  92         dma_addr_t sq_dma_addr;
  93         dma_addr_t cq_dma_addr;
  94         wait_queue_head_t sq_full;
  95         struct bio_list sq_cong;
  96         u32 __iomem *q_db;
  97         u16 q_depth;
  98         u16 cq_vector;
  99         u16 sq_head;
 100         u16 sq_tail;
 101         u16 cq_head;
 102         u16 cq_phase;
 103         unsigned long cmdid_data[];
 104 };
 105
 106 /*
 107  * Check we didin't inadvertently grow the command struct
 108  */
 109 static inline void _nvme_check_size(void)
 110 {
 111         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 112         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 113         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 114         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 115         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 118         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 119         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 120 }
 121
 122 /**
 123  * alloc_cmdid - Allocate a Command ID
 124  * @param nvmeq The queue that will be used for this command
 125  * @param ctx A pointer that will be passed to the handler
 126  * @param handler The ID of the handler to call
 127  *
 128  * Allocate a Command ID for a queue.  The data passed in will
 129  * be passed to the completion handler.  This is implemented by using
 130  * the bottom two bits of the ctx pointer to store the handler ID.
 131  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 132  * We can change this if it becomes a problem.
 133  */
 134 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler)
 135 {
 136         int depth = nvmeq->q_depth;
 137         unsigned long data = (unsigned long)ctx | handler;
 138         int cmdid;
 139
 140         BUG_ON((unsigned long)ctx & 3);
 141
 142         do {
 143                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 144                 if (cmdid >= depth)
 145                         return -EBUSY;
 146         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 147
 148         nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data;
 149         return cmdid;
 150 }
 151
 152 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 153                                                                 int handler)
 154 {
 155         int cmdid;
 156         wait_event_killable(nvmeq->sq_full,
 157                         (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0);
 158         return (cmdid < 0) ? -EINTR : cmdid;
 159 }
 160
 161 /* If you need more than four handlers, you'll need to change how
 162  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 163  * CMD_CTX value instead, if that works for your situation.
 164  */
 165 enum {
 166         sync_completion_id = 0,
 167         bio_completion_id,
 168 };
 169
 170 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 171 #define CMD_CTX_CANCELLED       (0x2008 + CMD_CTX_BASE)
 172 #define CMD_CTX_COMPLETED       (0x2010 + CMD_CTX_BASE)
 173 #define CMD_CTX_INVALID         (0x2014 + CMD_CTX_BASE)
 174
 175 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 176 {
 177         unsigned long data;
 178         unsigned offset = cmdid + BITS_TO_LONGS(nvmeq->q_depth);
 179
 180         if (cmdid > nvmeq->q_depth)
 181                 return CMD_CTX_INVALID;
 182         data = nvmeq->cmdid_data[offset];
 183         nvmeq->cmdid_data[offset] = CMD_CTX_COMPLETED;
 184         clear_bit(cmdid, nvmeq->cmdid_data);
 185         wake_up(&nvmeq->sq_full);
 186         return data;
 187 }
 188
 189 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 190 {
 191         unsigned offset = cmdid + BITS_TO_LONGS(nvmeq->q_depth);
 192         nvmeq->cmdid_data[offset] = CMD_CTX_CANCELLED;
 193 }
 194
 195 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 196 {
 197         int qid, cpu = get_cpu();
 198         if (cpu < ns->dev->queue_count)
 199                 qid = cpu + 1;
 200         else
 201                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 202         return ns->dev->queues[qid];
 203 }
 204
 205 static void put_nvmeq(struct nvme_queue *nvmeq)
 206 {
 207         put_cpu();
 208 }
 209
 210 /**
 211  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 212  * @nvmeq: The queue to use
 213  * @cmd: The command to send
 214  *
 215  * Safe to use from interrupt context
 216  */
 217 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 218 {
 219         unsigned long flags;
 220         u16 tail;
 221         /* XXX: Need to check tail isn't going to overrun head */
 222         spin_lock_irqsave(&nvmeq->q_lock, flags);
 223         tail = nvmeq->sq_tail;
 224         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 225         writel(tail, nvmeq->q_db);
 226         if (++tail == nvmeq->q_depth)
 227                 tail = 0;
 228         nvmeq->sq_tail = tail;
 229         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 230
 231         return 0;
 232 }
 233
 234 struct nvme_req_info {
 235         struct bio *bio;
 236         int nents;
 237         struct scatterlist sg[0];
 238 };
 239
 240 /* XXX: use a mempool */
 241 static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp)
 242 {
 243         return kmalloc(sizeof(struct nvme_req_info) +
 244                         sizeof(struct scatterlist) * nseg, gfp);
 245 }
 246
 247 static void free_info(struct nvme_req_info *info)
 248 {
 249         kfree(info);
 250 }
 251
 252 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 253                                                 struct nvme_completion *cqe)
 254 {
 255         struct nvme_req_info *info = ctx;
 256         struct bio *bio = info->bio;
 257         u16 status = le16_to_cpup(&cqe->status) >> 1;
 258
 259         dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents,
 260                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 261         free_info(info);
 262         bio_endio(bio, status ? -EIO : 0);
 263 }
 264
 265 /* length is in bytes */
 266 static void nvme_setup_prps(struct nvme_common_command *cmd,
 267                                         struct scatterlist *sg, int length)
 268 {
 269         int dma_len = sg_dma_len(sg);
 270         u64 dma_addr = sg_dma_address(sg);
 271         int offset = offset_in_page(dma_addr);
 272
 273         cmd->prp1 = cpu_to_le64(dma_addr);
 274         length -= (PAGE_SIZE - offset);
 275         if (length <= 0)
 276                 return;
 277
 278         dma_len -= (PAGE_SIZE - offset);
 279         if (dma_len) {
 280                 dma_addr += (PAGE_SIZE - offset);
 281         } else {
 282                 sg = sg_next(sg);
 283                 dma_addr = sg_dma_address(sg);
 284                 dma_len = sg_dma_len(sg);
 285         }
 286
 287         if (length <= PAGE_SIZE) {
 288                 cmd->prp2 = cpu_to_le64(dma_addr);
 289                 return;
 290         }
 291
 292         /* XXX: support PRP lists */
 293 }
 294
 295 static int nvme_map_bio(struct device *dev, struct nvme_req_info *info,
 296                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 297 {
 298         struct bio_vec *bvec;
 299         struct scatterlist *sg = info->sg;
 300         int i, nsegs;
 301
 302         sg_init_table(sg, psegs);
 303         bio_for_each_segment(bvec, bio, i) {
 304                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 305                 /* XXX: handle non-mergable here */
 306                 nsegs++;
 307         }
 308         info->nents = nsegs;
 309
 310         return dma_map_sg(dev, info->sg, info->nents, dma_dir);
 311 }
 312
 313 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 314                                                                 struct bio *bio)
 315 {
 316         struct nvme_command *cmnd;
 317         struct nvme_req_info *info;
 318         enum dma_data_direction dma_dir;
 319         int cmdid;
 320         u16 control;
 321         u32 dsmgmt;
 322         unsigned long flags;
 323         int psegs = bio_phys_segments(ns->queue, bio);
 324
 325         info = alloc_info(psegs, GFP_NOIO);
 326         if (!info)
 327                 goto congestion;
 328         info->bio = bio;
 329
 330         cmdid = alloc_cmdid(nvmeq, info, bio_completion_id);
 331         if (unlikely(cmdid < 0))
 332                 goto free_info;
 333
 334         control = 0;
 335         if (bio->bi_rw & REQ_FUA)
 336                 control |= NVME_RW_FUA;
 337         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 338                 control |= NVME_RW_LR;
 339
 340         dsmgmt = 0;
 341         if (bio->bi_rw & REQ_RAHEAD)
 342                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 343
 344         spin_lock_irqsave(&nvmeq->q_lock, flags);
 345         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 346
 347         memset(cmnd, 0, sizeof(*cmnd));
 348         if (bio_data_dir(bio)) {
 349                 cmnd->rw.opcode = nvme_cmd_write;
 350                 dma_dir = DMA_TO_DEVICE;
 351         } else {
 352                 cmnd->rw.opcode = nvme_cmd_read;
 353                 dma_dir = DMA_FROM_DEVICE;
 354         }
 355
 356         nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs);
 357
 358         cmnd->rw.flags = 1;
 359         cmnd->rw.command_id = cmdid;
 360         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 361         nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size);
 362         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 363         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 364         cmnd->rw.control = cpu_to_le16(control);
 365         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 366
 367         writel(nvmeq->sq_tail, nvmeq->q_db);
 368         if (++nvmeq->sq_tail == nvmeq->q_depth)
 369                 nvmeq->sq_tail = 0;
 370
 371         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 372
 373         return 0;
 374
 375  free_info:
 376         free_info(info);
 377  congestion:
 378         return -EBUSY;
 379 }
 380
 381 /*
 382  * NB: return value of non-zero would mean that we were a stacking driver.
 383  * make_request must always succeed.
 384  */
 385 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 386 {
 387         struct nvme_ns *ns = q->queuedata;
 388         struct nvme_queue *nvmeq = get_nvmeq(ns);
 389
 390         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 391                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 392                 bio_list_add(&nvmeq->sq_cong, bio);
 393         }
 394         put_nvmeq(nvmeq);
 395
 396         return 0;
 397 }
 398
 399 struct sync_cmd_info {
 400         struct task_struct *task;
 401         u32 result;
 402         int status;
 403 };
 404
 405 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 406                                                 struct nvme_completion *cqe)
 407 {
 408         struct sync_cmd_info *cmdinfo = ctx;
 409         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 410                 return;
 411         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 412                 dev_warn(nvmeq->q_dmadev,
 413                                 "completed id %d twice on queue %d\n",
 414                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 415                 return;
 416         }
 417         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 418                 dev_warn(nvmeq->q_dmadev,
 419                                 "invalid id %d completed on queue %d\n",
 420                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 421                 return;
 422         }
 423         cmdinfo->result = le32_to_cpup(&cqe->result);
 424         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 425         wake_up_process(cmdinfo->task);
 426 }
 427
 428 typedef void (*completion_fn)(struct nvme_queue *, void *,
 429                                                 struct nvme_completion *);
 430
 431 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 432 {
 433         u16 head, phase;
 434
 435         static const completion_fn completions[4] = {
 436                 [sync_completion_id] = sync_completion,
 437                 [bio_completion_id]  = bio_completion,
 438         };
 439
 440         head = nvmeq->cq_head;
 441         phase = nvmeq->cq_phase;
 442
 443         for (;;) {
 444                 unsigned long data;
 445                 void *ptr;
 446                 unsigned char handler;
 447                 struct nvme_completion cqe = nvmeq->cqes[head];
 448                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 449                         break;
 450                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 451                 if (++head == nvmeq->q_depth) {
 452                         head = 0;
 453                         phase = !phase;
 454                 }
 455
 456                 data = free_cmdid(nvmeq, cqe.command_id);
 457                 handler = data & 3;
 458                 ptr = (void *)(data & ~3UL);
 459                 completions[handler](nvmeq, ptr, &cqe);
 460         }
 461
 462         /* If the controller ignores the cq head doorbell and continuously
 463          * writes to the queue, it is theoretically possible to wrap around
 464          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 465          * requires that 0.1% of your interrupts are handled, so this isn't
 466          * a big problem.
 467          */
 468         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 469                 return IRQ_NONE;
 470
 471         writel(head, nvmeq->q_db + 1);
 472         nvmeq->cq_head = head;
 473         nvmeq->cq_phase = phase;
 474
 475         return IRQ_HANDLED;
 476 }
 477
 478 static irqreturn_t nvme_irq(int irq, void *data)
 479 {
 480         irqreturn_t result;
 481         struct nvme_queue *nvmeq = data;
 482         spin_lock(&nvmeq->q_lock);
 483         result = nvme_process_cq(nvmeq);
 484         spin_unlock(&nvmeq->q_lock);
 485         return result;
 486 }
 487
 488 static irqreturn_t nvme_irq_check(int irq, void *data)
 489 {
 490         struct nvme_queue *nvmeq = data;
 491         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 492         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 493                 return IRQ_NONE;
 494         return IRQ_WAKE_THREAD;
 495 }
 496
 497 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 498 {
 499         spin_lock_irq(&nvmeq->q_lock);
 500         cancel_cmdid_data(nvmeq, cmdid);
 501         spin_unlock_irq(&nvmeq->q_lock);
 502 }
 503
 504 /*
 505  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 506  * if the result is positive, it's an NVM Express status code
 507  */
 508 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 509                                         struct nvme_command *cmd, u32 *result)
 510 {
 511         int cmdid;
 512         struct sync_cmd_info cmdinfo;
 513
 514         cmdinfo.task = current;
 515         cmdinfo.status = -EINTR;
 516
 517         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id);
 518         if (cmdid < 0)
 519                 return cmdid;
 520         cmd->common.command_id = cmdid;
 521
 522         set_current_state(TASK_KILLABLE);
 523         nvme_submit_cmd(nvmeq, cmd);
 524         schedule();
 525
 526         if (cmdinfo.status == -EINTR) {
 527                 nvme_abort_command(nvmeq, cmdid);
 528                 return -EINTR;
 529         }
 530
 531         if (result)
 532                 *result = cmdinfo.result;
 533
 534         return cmdinfo.status;
 535 }
 536
 537 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 538                                                                 u32 *result)
 539 {
 540         return nvme_submit_sync_cmd(dev->queues[0], cmd, result);
 541 }
 542
 543 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 544 {
 545         int status;
 546         struct nvme_command c;
 547
 548         memset(&c, 0, sizeof(c));
 549         c.delete_queue.opcode = opcode;
 550         c.delete_queue.qid = cpu_to_le16(id);
 551
 552         status = nvme_submit_admin_cmd(dev, &c, NULL);
 553         if (status)
 554                 return -EIO;
 555         return 0;
 556 }
 557
 558 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 559                                                 struct nvme_queue *nvmeq)
 560 {
 561         int status;
 562         struct nvme_command c;
 563         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 564
 565         memset(&c, 0, sizeof(c));
 566         c.create_cq.opcode = nvme_admin_create_cq;
 567         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 568         c.create_cq.cqid = cpu_to_le16(qid);
 569         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 570         c.create_cq.cq_flags = cpu_to_le16(flags);
 571         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 572
 573         status = nvme_submit_admin_cmd(dev, &c, NULL);
 574         if (status)
 575                 return -EIO;
 576         return 0;
 577 }
 578
 579 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 580                                                 struct nvme_queue *nvmeq)
 581 {
 582         int status;
 583         struct nvme_command c;
 584         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 585
 586         memset(&c, 0, sizeof(c));
 587         c.create_sq.opcode = nvme_admin_create_sq;
 588         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 589         c.create_sq.sqid = cpu_to_le16(qid);
 590         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 591         c.create_sq.sq_flags = cpu_to_le16(flags);
 592         c.create_sq.cqid = cpu_to_le16(qid);
 593
 594         status = nvme_submit_admin_cmd(dev, &c, NULL);
 595         if (status)
 596                 return -EIO;
 597         return 0;
 598 }
 599
 600 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 601 {
 602         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 603 }
 604
 605 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 606 {
 607         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 608 }
 609
 610 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 611 {
 612         struct nvme_queue *nvmeq = dev->queues[qid];
 613
 614         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 615
 616         /* Don't tell the adapter to delete the admin queue */
 617         if (qid) {
 618                 adapter_delete_sq(dev, qid);
 619                 adapter_delete_cq(dev, qid);
 620         }
 621
 622         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 623                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 624         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 625                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 626         kfree(nvmeq);
 627 }
 628
 629 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 630                                                         int depth, int vector)
 631 {
 632         struct device *dmadev = &dev->pci_dev->dev;
 633         unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long);
 634         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 635         if (!nvmeq)
 636                 return NULL;
 637
 638         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 639                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 640         if (!nvmeq->cqes)
 641                 goto free_nvmeq;
 642         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 643
 644         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 645                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 646         if (!nvmeq->sq_cmds)
 647                 goto free_cqdma;
 648
 649         nvmeq->q_dmadev = dmadev;
 650         spin_lock_init(&nvmeq->q_lock);
 651         nvmeq->cq_head = 0;
 652         nvmeq->cq_phase = 1;
 653         init_waitqueue_head(&nvmeq->sq_full);
 654         bio_list_init(&nvmeq->sq_cong);
 655         nvmeq->q_db = &dev->dbs[qid * 2];
 656         nvmeq->q_depth = depth;
 657         nvmeq->cq_vector = vector;
 658
 659         return nvmeq;
 660
 661  free_cqdma:
 662         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 663                                                         nvmeq->cq_dma_addr);
 664  free_nvmeq:
 665         kfree(nvmeq);
 666         return NULL;
 667 }
 668
 669 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 670                                                         const char *name)
 671 {
 672         if (use_threaded_interrupts)
 673                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 674                                         nvme_irq_check, nvme_irq,
 675                                         IRQF_DISABLED | IRQF_SHARED,
 676                                         name, nvmeq);
 677         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 678                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 679 }
 680
 681 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 682                                         int qid, int cq_size, int vector)
 683 {
 684         int result;
 685         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 686
 687         if (!nvmeq)
 688                 return NULL;
 689
 690         result = adapter_alloc_cq(dev, qid, nvmeq);
 691         if (result < 0)
 692                 goto free_nvmeq;
 693
 694         result = adapter_alloc_sq(dev, qid, nvmeq);
 695         if (result < 0)
 696                 goto release_cq;
 697
 698         result = queue_request_irq(dev, nvmeq, "nvme");
 699         if (result < 0)
 700                 goto release_sq;
 701
 702         return nvmeq;
 703
 704  release_sq:
 705         adapter_delete_sq(dev, qid);
 706  release_cq:
 707         adapter_delete_cq(dev, qid);
 708  free_nvmeq:
 709         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 710                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 711         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 712                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 713         kfree(nvmeq);
 714         return NULL;
 715 }
 716
 717 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 718 {
 719         int result;
 720         u32 aqa;
 721         struct nvme_queue *nvmeq;
 722
 723         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 724
 725         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 726         if (!nvmeq)
 727                 return -ENOMEM;
 728
 729         aqa = nvmeq->q_depth - 1;
 730         aqa |= aqa << 16;
 731
 732         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 733         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 734         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 735
 736         writel(0, &dev->bar->cc);
 737         writel(aqa, &dev->bar->aqa);
 738         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 739         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 740         writel(dev->ctrl_config, &dev->bar->cc);
 741
 742         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 743                 msleep(100);
 744                 if (fatal_signal_pending(current))
 745                         return -EINTR;
 746         }
 747
 748         result = queue_request_irq(dev, nvmeq, "nvme admin");
 749         dev->queues[0] = nvmeq;
 750         return result;
 751 }
 752
 753 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 754                                 unsigned long addr, unsigned length,
 755                                 struct scatterlist **sgp)
 756 {
 757         int i, err, count, nents, offset;
 758         struct scatterlist *sg;
 759         struct page **pages;
 760
 761         if (addr & 3)
 762                 return -EINVAL;
 763         if (!length)
 764                 return -EINVAL;
 765
 766         offset = offset_in_page(addr);
 767         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 768         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 769
 770         err = get_user_pages_fast(addr, count, 1, pages);
 771         if (err < count) {
 772                 count = err;
 773                 err = -EFAULT;
 774                 goto put_pages;
 775         }
 776
 777         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 778         sg_init_table(sg, count);
 779         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 780         length -= (PAGE_SIZE - offset);
 781         for (i = 1; i < count; i++) {
 782                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 783                 length -= PAGE_SIZE;
 784         }
 785
 786         err = -ENOMEM;
 787         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 788                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 789         if (!nents)
 790                 goto put_pages;
 791
 792         kfree(pages);
 793         *sgp = sg;
 794         return nents;
 795
 796  put_pages:
 797         for (i = 0; i < count; i++)
 798                 put_page(pages[i]);
 799         kfree(pages);
 800         return err;
 801 }
 802
 803 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 804                                 unsigned long addr, int length,
 805                                 struct scatterlist *sg, int nents)
 806 {
 807         int i, count;
 808
 809         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 810         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 811
 812         for (i = 0; i < count; i++)
 813                 put_page(sg_page(&sg[i]));
 814 }
 815
 816 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 817                                         unsigned long addr, unsigned length,
 818                                         struct nvme_command *cmd)
 819 {
 820         int err, nents;
 821         struct scatterlist *sg;
 822
 823         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 824         if (nents < 0)
 825                 return nents;
 826         nvme_setup_prps(&cmd->common, sg, length);
 827         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 828         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 829         return err ? -EIO : 0;
 830 }
 831
 832 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 833 {
 834         struct nvme_command c;
 835
 836         memset(&c, 0, sizeof(c));
 837         c.identify.opcode = nvme_admin_identify;
 838         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 839         c.identify.cns = cpu_to_le32(cns);
 840
 841         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 842 }
 843
 844 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 845 {
 846         struct nvme_command c;
 847
 848         memset(&c, 0, sizeof(c));
 849         c.features.opcode = nvme_admin_get_features;
 850         c.features.nsid = cpu_to_le32(ns->ns_id);
 851         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 852
 853         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 854 }
 855
 856 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 857 {
 858         struct nvme_dev *dev = ns->dev;
 859         struct nvme_queue *nvmeq;
 860         struct nvme_user_io io;
 861         struct nvme_command c;
 862         unsigned length;
 863         u32 result;
 864         int nents, status;
 865         struct scatterlist *sg;
 866
 867         if (copy_from_user(&io, uio, sizeof(io)))
 868                 return -EFAULT;
 869         length = io.nblocks << io.block_shift;
 870         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 871         if (nents < 0)
 872                 return nents;
 873
 874         memset(&c, 0, sizeof(c));
 875         c.rw.opcode = io.opcode;
 876         c.rw.flags = io.flags;
 877         c.rw.nsid = cpu_to_le32(io.nsid);
 878         c.rw.slba = cpu_to_le64(io.slba);
 879         c.rw.length = cpu_to_le16(io.nblocks - 1);
 880         c.rw.control = cpu_to_le16(io.control);
 881         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 882         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 883         c.rw.apptag = cpu_to_le16(io.apptag);
 884         c.rw.appmask = cpu_to_le16(io.appmask);
 885         /* XXX: metadata */
 886         nvme_setup_prps(&c.common, sg, length);
 887
 888         nvmeq = get_nvmeq(ns);
 889         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 890          * disabled.  We may be preempted at any point, and be rescheduled
 891          * to a different CPU.  That will cause cacheline bouncing, but no
 892          * additional races since q_lock already protects against other CPUs.
 893          */
 894         put_nvmeq(nvmeq);
 895         status = nvme_submit_sync_cmd(nvmeq, &c, &result);
 896
 897         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
 898         put_user(result, &uio->result);
 899         return status;
 900 }
 901
 902 static int nvme_download_firmware(struct nvme_ns *ns,
 903                                                 struct nvme_dlfw __user *udlfw)
 904 {
 905         struct nvme_dev *dev = ns->dev;
 906         struct nvme_dlfw dlfw;
 907         struct nvme_command c;
 908         int nents, status;
 909         struct scatterlist *sg;
 910
 911         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
 912                 return -EFAULT;
 913         if (dlfw.length >= (1 << 30))
 914                 return -EINVAL;
 915
 916         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
 917         if (nents < 0)
 918                 return nents;
 919
 920         memset(&c, 0, sizeof(c));
 921         c.dlfw.opcode = nvme_admin_download_fw;
 922         c.dlfw.numd = cpu_to_le32(dlfw.length);
 923         c.dlfw.offset = cpu_to_le32(dlfw.offset);
 924         nvme_setup_prps(&c.common, sg, dlfw.length * 4);
 925
 926         status = nvme_submit_admin_cmd(dev, &c, NULL);
 927         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
 928         return status;
 929 }
 930
 931 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
 932 {
 933         struct nvme_dev *dev = ns->dev;
 934         struct nvme_command c;
 935
 936         memset(&c, 0, sizeof(c));
 937         c.common.opcode = nvme_admin_activate_fw;
 938         c.common.rsvd10[0] = cpu_to_le32(arg);
 939
 940         return nvme_submit_admin_cmd(dev, &c, NULL);
 941 }
 942
 943 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
 944                                                         unsigned long arg)
 945 {
 946         struct nvme_ns *ns = bdev->bd_disk->private_data;
 947
 948         switch (cmd) {
 949         case NVME_IOCTL_IDENTIFY_NS:
 950                 return nvme_identify(ns, arg, 0);
 951         case NVME_IOCTL_IDENTIFY_CTRL:
 952                 return nvme_identify(ns, arg, 1);
 953         case NVME_IOCTL_GET_RANGE_TYPE:
 954                 return nvme_get_range_type(ns, arg);
 955         case NVME_IOCTL_SUBMIT_IO:
 956                 return nvme_submit_io(ns, (void __user *)arg);
 957         case NVME_IOCTL_DOWNLOAD_FW:
 958                 return nvme_download_firmware(ns, (void __user *)arg);
 959         case NVME_IOCTL_ACTIVATE_FW:
 960                 return nvme_activate_firmware(ns, arg);
 961         default:
 962                 return -ENOTTY;
 963         }
 964 }
 965
 966 static const struct block_device_operations nvme_fops = {
 967         .owner          = THIS_MODULE,
 968         .ioctl          = nvme_ioctl,
 969 };
 970
 971 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
 972                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
 973 {
 974         struct nvme_ns *ns;
 975         struct gendisk *disk;
 976         int lbaf;
 977
 978         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
 979                 return NULL;
 980
 981         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
 982         if (!ns)
 983                 return NULL;
 984         ns->queue = blk_alloc_queue(GFP_KERNEL);
 985         if (!ns->queue)
 986                 goto out_free_ns;
 987         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
 988                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
 989         blk_queue_make_request(ns->queue, nvme_make_request);
 990         ns->dev = dev;
 991         ns->queue->queuedata = ns;
 992
 993         disk = alloc_disk(NVME_MINORS);
 994         if (!disk)
 995                 goto out_free_queue;
 996         ns->ns_id = index;
 997         ns->disk = disk;
 998         lbaf = id->flbas & 0xf;
 999         ns->lba_shift = id->lbaf[lbaf].ds;
1000
1001         disk->major = nvme_major;
1002         disk->minors = NVME_MINORS;
1003         disk->first_minor = NVME_MINORS * index;
1004         disk->fops = &nvme_fops;
1005         disk->private_data = ns;
1006         disk->queue = ns->queue;
1007         disk->driverfs_dev = &dev->pci_dev->dev;
1008         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1009         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1010
1011         return ns;
1012
1013  out_free_queue:
1014         blk_cleanup_queue(ns->queue);
1015  out_free_ns:
1016         kfree(ns);
1017         return NULL;
1018 }
1019
1020 static void nvme_ns_free(struct nvme_ns *ns)
1021 {
1022         put_disk(ns->disk);
1023         blk_cleanup_queue(ns->queue);
1024         kfree(ns);
1025 }
1026
1027 static int set_queue_count(struct nvme_dev *dev, int count)
1028 {
1029         int status;
1030         u32 result;
1031         struct nvme_command c;
1032         u32 q_count = (count - 1) | ((count - 1) << 16);
1033
1034         memset(&c, 0, sizeof(c));
1035         c.features.opcode = nvme_admin_get_features;
1036         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1037         c.features.dword11 = cpu_to_le32(q_count);
1038
1039         status = nvme_submit_admin_cmd(dev, &c, &result);
1040         if (status)
1041                 return -EIO;
1042         return min(result & 0xffff, result >> 16) + 1;
1043 }
1044
1045 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1046 {
1047         int result, cpu, i, nr_queues;
1048
1049         nr_queues = num_online_cpus();
1050         result = set_queue_count(dev, nr_queues);
1051         if (result < 0)
1052                 return result;
1053         if (result < nr_queues)
1054                 nr_queues = result;
1055
1056         /* Deregister the admin queue's interrupt */
1057         free_irq(dev->entry[0].vector, dev->queues[0]);
1058
1059         for (i = 0; i < nr_queues; i++)
1060                 dev->entry[i].entry = i;
1061         for (;;) {
1062                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1063                 if (result == 0) {
1064                         break;
1065                 } else if (result > 0) {
1066                         nr_queues = result;
1067                         continue;
1068                 } else {
1069                         nr_queues = 1;
1070                         break;
1071                 }
1072         }
1073
1074         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1075         /* XXX: handle failure here */
1076
1077         cpu = cpumask_first(cpu_online_mask);
1078         for (i = 0; i < nr_queues; i++) {
1079                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1080                 cpu = cpumask_next(cpu, cpu_online_mask);
1081         }
1082
1083         for (i = 0; i < nr_queues; i++) {
1084                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1085                                                         NVME_Q_DEPTH, i);
1086                 if (!dev->queues[i + 1])
1087                         return -ENOMEM;
1088                 dev->queue_count++;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static void nvme_free_queues(struct nvme_dev *dev)
1095 {
1096         int i;
1097
1098         for (i = dev->queue_count - 1; i >= 0; i--)
1099                 nvme_free_queue(dev, i);
1100 }
1101
1102 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1103 {
1104         int res, nn, i;
1105         struct nvme_ns *ns, *next;
1106         struct nvme_id_ctrl *ctrl;
1107         void *id;
1108         dma_addr_t dma_addr;
1109         struct nvme_command cid, crt;
1110
1111         res = nvme_setup_io_queues(dev);
1112         if (res)
1113                 return res;
1114
1115         /* XXX: Switch to a SG list once prp2 works */
1116         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1117                                                                 GFP_KERNEL);
1118
1119         memset(&cid, 0, sizeof(cid));
1120         cid.identify.opcode = nvme_admin_identify;
1121         cid.identify.nsid = 0;
1122         cid.identify.prp1 = cpu_to_le64(dma_addr);
1123         cid.identify.cns = cpu_to_le32(1);
1124
1125         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1126         if (res) {
1127                 res = -EIO;
1128                 goto out_free;
1129         }
1130
1131         ctrl = id;
1132         nn = le32_to_cpup(&ctrl->nn);
1133         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1134         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1135         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1136
1137         cid.identify.cns = 0;
1138         memset(&crt, 0, sizeof(crt));
1139         crt.features.opcode = nvme_admin_get_features;
1140         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1141         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1142
1143         for (i = 0; i < nn; i++) {
1144                 cid.identify.nsid = cpu_to_le32(i);
1145                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1146                 if (res)
1147                         continue;
1148
1149                 if (((struct nvme_id_ns *)id)->ncap == 0)
1150                         continue;
1151
1152                 crt.features.nsid = cpu_to_le32(i);
1153                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1154                 if (res)
1155                         continue;
1156
1157                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1158                 if (ns)
1159                         list_add_tail(&ns->list, &dev->namespaces);
1160         }
1161         list_for_each_entry(ns, &dev->namespaces, list)
1162                 add_disk(ns->disk);
1163
1164         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1165         return 0;
1166
1167  out_free:
1168         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1169                 list_del(&ns->list);
1170                 nvme_ns_free(ns);
1171         }
1172
1173         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1174         return res;
1175 }
1176
1177 static int nvme_dev_remove(struct nvme_dev *dev)
1178 {
1179         struct nvme_ns *ns, *next;
1180
1181         /* TODO: wait all I/O finished or cancel them */
1182
1183         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1184                 list_del(&ns->list);
1185                 del_gendisk(ns->disk);
1186                 nvme_ns_free(ns);
1187         }
1188
1189         nvme_free_queues(dev);
1190
1191         return 0;
1192 }
1193
1194 /* XXX: Use an ida or something to let remove / add work correctly */
1195 static void nvme_set_instance(struct nvme_dev *dev)
1196 {
1197         static int instance;
1198         dev->instance = instance++;
1199 }
1200
1201 static void nvme_release_instance(struct nvme_dev *dev)
1202 {
1203 }
1204
1205 static int __devinit nvme_probe(struct pci_dev *pdev,
1206                                                 const struct pci_device_id *id)
1207 {
1208         int bars, result = -ENOMEM;
1209         struct nvme_dev *dev;
1210
1211         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1212         if (!dev)
1213                 return -ENOMEM;
1214         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1215                                                                 GFP_KERNEL);
1216         if (!dev->entry)
1217                 goto free;
1218         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1219                                                                 GFP_KERNEL);
1220         if (!dev->queues)
1221                 goto free;
1222
1223         if (pci_enable_device_mem(pdev))
1224                 goto free;
1225         pci_set_master(pdev);
1226         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1227         if (pci_request_selected_regions(pdev, bars, "nvme"))
1228                 goto disable;
1229
1230         INIT_LIST_HEAD(&dev->namespaces);
1231         dev->pci_dev = pdev;
1232         pci_set_drvdata(pdev, dev);
1233         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1234         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1235         nvme_set_instance(dev);
1236         dev->entry[0].vector = pdev->irq;
1237
1238         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1239         if (!dev->bar) {
1240                 result = -ENOMEM;
1241                 goto disable_msix;
1242         }
1243
1244         result = nvme_configure_admin_queue(dev);
1245         if (result)
1246                 goto unmap;
1247         dev->queue_count++;
1248
1249         result = nvme_dev_add(dev);
1250         if (result)
1251                 goto delete;
1252         return 0;
1253
1254  delete:
1255         nvme_free_queues(dev);
1256  unmap:
1257         iounmap(dev->bar);
1258  disable_msix:
1259         pci_disable_msix(pdev);
1260         nvme_release_instance(dev);
1261  disable:
1262         pci_disable_device(pdev);
1263         pci_release_regions(pdev);
1264  free:
1265         kfree(dev->queues);
1266         kfree(dev->entry);
1267         kfree(dev);
1268         return result;
1269 }
1270
1271 static void __devexit nvme_remove(struct pci_dev *pdev)
1272 {
1273         struct nvme_dev *dev = pci_get_drvdata(pdev);
1274         nvme_dev_remove(dev);
1275         pci_disable_msix(pdev);
1276         iounmap(dev->bar);
1277         nvme_release_instance(dev);
1278         pci_disable_device(pdev);
1279         pci_release_regions(pdev);
1280         kfree(dev->queues);
1281         kfree(dev->entry);
1282         kfree(dev);
1283 }
1284
1285 /* These functions are yet to be implemented */
1286 #define nvme_error_detected NULL
1287 #define nvme_dump_registers NULL
1288 #define nvme_link_reset NULL
1289 #define nvme_slot_reset NULL
1290 #define nvme_error_resume NULL
1291 #define nvme_suspend NULL
1292 #define nvme_resume NULL
1293
1294 static struct pci_error_handlers nvme_err_handler = {
1295         .error_detected = nvme_error_detected,
1296         .mmio_enabled   = nvme_dump_registers,
1297         .link_reset     = nvme_link_reset,
1298         .slot_reset     = nvme_slot_reset,
1299         .resume         = nvme_error_resume,
1300 };
1301
1302 /* Move to pci_ids.h later */
1303 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1304
1305 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1306         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1307         { 0, }
1308 };
1309 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1310
1311 static struct pci_driver nvme_driver = {
1312         .name           = "nvme",
1313         .id_table       = nvme_id_table,
1314         .probe          = nvme_probe,
1315         .remove         = __devexit_p(nvme_remove),
1316         .suspend        = nvme_suspend,
1317         .resume         = nvme_resume,
1318         .err_handler    = &nvme_err_handler,
1319 };
1320
1321 static int __init nvme_init(void)
1322 {
1323         int result;
1324
1325         nvme_major = register_blkdev(nvme_major, "nvme");
1326         if (nvme_major <= 0)
1327                 return -EBUSY;
1328
1329         result = pci_register_driver(&nvme_driver);
1330         if (!result)
1331                 return 0;
1332
1333         unregister_blkdev(nvme_major, "nvme");
1334         return result;
1335 }
1336
1337 static void __exit nvme_exit(void)
1338 {
1339         pci_unregister_driver(&nvme_driver);
1340         unregister_blkdev(nvme_major, "nvme");
1341 }
1342
1343 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1344 MODULE_LICENSE("GPL");
1345 MODULE_VERSION("0.2");
1346 module_init(nvme_init);
1347 module_exit(nvme_exit);