drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         int instance;
  61         int queue_count;
  62         u32 ctrl_config;
  63         struct msix_entry *entry;
  64         struct nvme_bar __iomem *bar;
  65         struct list_head namespaces;
  66         char serial[20];
  67         char model[40];
  68         char firmware_rev[8];
  69 };
  70
  71 /*
  72  * An NVM Express namespace is equivalent to a SCSI LUN
  73  */
  74 struct nvme_ns {
  75         struct list_head list;
  76
  77         struct nvme_dev *dev;
  78         struct request_queue *queue;
  79         struct gendisk *disk;
  80
  81         int ns_id;
  82         int lba_shift;
  83 };
  84
  85 /*
  86  * An NVM Express queue.  Each device has at least two (one for admin
  87  * commands and one for I/O commands).
  88  */
  89 struct nvme_queue {
  90         struct device *q_dmadev;
  91         spinlock_t q_lock;
  92         struct nvme_command *sq_cmds;
  93         volatile struct nvme_completion *cqes;
  94         dma_addr_t sq_dma_addr;
  95         dma_addr_t cq_dma_addr;
  96         wait_queue_head_t sq_full;
  97         struct bio_list sq_cong;
  98         u32 __iomem *q_db;
  99         u16 q_depth;
 100         u16 cq_vector;
 101         u16 sq_head;
 102         u16 sq_tail;
 103         u16 cq_head;
 104         u16 cq_phase;
 105         unsigned long cmdid_data[];
 106 };
 107
 108 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 109
 110 /*
 111  * Check we didin't inadvertently grow the command struct
 112  */
 113 static inline void _nvme_check_size(void)
 114 {
 115         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 116         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 117         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 118         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 122         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 123         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 124 }
 125
 126 struct nvme_cmd_info {
 127         unsigned long ctx;
 128         unsigned long timeout;
 129 };
 130
 131 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 132 {
 133         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 134 }
 135
 136 /**
 137  * alloc_cmdid - Allocate a Command ID
 138  * @param nvmeq The queue that will be used for this command
 139  * @param ctx A pointer that will be passed to the handler
 140  * @param handler The ID of the handler to call
 141  *
 142  * Allocate a Command ID for a queue.  The data passed in will
 143  * be passed to the completion handler.  This is implemented by using
 144  * the bottom two bits of the ctx pointer to store the handler ID.
 145  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 146  * We can change this if it becomes a problem.
 147  */
 148 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 149                                                         unsigned timeout)
 150 {
 151         int depth = nvmeq->q_depth;
 152         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 153         int cmdid;
 154
 155         BUG_ON((unsigned long)ctx & 3);
 156
 157         do {
 158                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 159                 if (cmdid >= depth)
 160                         return -EBUSY;
 161         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 162
 163         info[cmdid].ctx = (unsigned long)ctx | handler;
 164         info[cmdid].timeout = jiffies + timeout;
 165         return cmdid;
 166 }
 167
 168 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 169                                                 int handler, unsigned timeout)
 170 {
 171         int cmdid;
 172         wait_event_killable(nvmeq->sq_full,
 173                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 174         return (cmdid < 0) ? -EINTR : cmdid;
 175 }
 176
 177 /* If you need more than four handlers, you'll need to change how
 178  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 179  * CMD_CTX value instead, if that works for your situation.
 180  */
 181 enum {
 182         sync_completion_id = 0,
 183         bio_completion_id,
 184 };
 185
 186 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 187 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 188 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 189 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 190
 191 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 192 {
 193         unsigned long data;
 194         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 195
 196         if (cmdid >= nvmeq->q_depth)
 197                 return CMD_CTX_INVALID;
 198         data = info[cmdid].ctx;
 199         info[cmdid].ctx = CMD_CTX_COMPLETED;
 200         clear_bit(cmdid, nvmeq->cmdid_data);
 201         wake_up(&nvmeq->sq_full);
 202         return data;
 203 }
 204
 205 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 206 {
 207         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 208         info[cmdid].ctx = CMD_CTX_CANCELLED;
 209 }
 210
 211 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 212 {
 213         int qid, cpu = get_cpu();
 214         if (cpu < ns->dev->queue_count)
 215                 qid = cpu + 1;
 216         else
 217                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 218         return ns->dev->queues[qid];
 219 }
 220
 221 static void put_nvmeq(struct nvme_queue *nvmeq)
 222 {
 223         put_cpu();
 224 }
 225
 226 /**
 227  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 228  * @nvmeq: The queue to use
 229  * @cmd: The command to send
 230  *
 231  * Safe to use from interrupt context
 232  */
 233 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 234 {
 235         unsigned long flags;
 236         u16 tail;
 237         /* XXX: Need to check tail isn't going to overrun head */
 238         spin_lock_irqsave(&nvmeq->q_lock, flags);
 239         tail = nvmeq->sq_tail;
 240         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 241         writel(tail, nvmeq->q_db);
 242         if (++tail == nvmeq->q_depth)
 243                 tail = 0;
 244         nvmeq->sq_tail = tail;
 245         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 246
 247         return 0;
 248 }
 249
 250 static __le64 *alloc_prp_list(struct nvme_queue *nvmeq, int length,
 251                                  dma_addr_t *addr)
 252 {
 253         return dma_alloc_coherent(nvmeq->q_dmadev, PAGE_SIZE, addr, GFP_ATOMIC);
 254 }
 255
 256 struct nvme_prps {
 257         int npages;
 258         dma_addr_t first_dma;
 259         __le64 *list[0];
 260 };
 261
 262 static void nvme_free_prps(struct nvme_queue *nvmeq, struct nvme_prps *prps)
 263 {
 264         const int last_prp = PAGE_SIZE / 8 - 1;
 265         int i;
 266         dma_addr_t prp_dma;
 267
 268         if (!prps)
 269                 return;
 270
 271         prp_dma = prps->first_dma;
 272         for (i = 0; i < prps->npages; i++) {
 273                 __le64 *prp_list = prps->list[i];
 274                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 275                 dma_free_coherent(nvmeq->q_dmadev, PAGE_SIZE, prp_list,
 276                                                                 prp_dma);
 277                 prp_dma = next_prp_dma;
 278         }
 279         kfree(prps);
 280 }
 281
 282 struct nvme_bio {
 283         struct bio *bio;
 284         int nents;
 285         struct nvme_prps *prps;
 286         struct scatterlist sg[0];
 287 };
 288
 289 /* XXX: use a mempool */
 290 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 291 {
 292         return kzalloc(sizeof(struct nvme_bio) +
 293                         sizeof(struct scatterlist) * nseg, gfp);
 294 }
 295
 296 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 297 {
 298         nvme_free_prps(nvmeq, nbio->prps);
 299         kfree(nbio);
 300 }
 301
 302 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 303                                                 struct nvme_completion *cqe)
 304 {
 305         struct nvme_bio *nbio = ctx;
 306         struct bio *bio = nbio->bio;
 307         u16 status = le16_to_cpup(&cqe->status) >> 1;
 308
 309         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 310                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 311         free_nbio(nvmeq, nbio);
 312         bio_endio(bio, status ? -EIO : 0);
 313         bio = bio_list_pop(&nvmeq->sq_cong);
 314         if (bio)
 315                 nvme_resubmit_bio(nvmeq, bio);
 316 }
 317
 318 /* length is in bytes */
 319 static struct nvme_prps *nvme_setup_prps(struct nvme_queue *nvmeq,
 320                                         struct nvme_common_command *cmd,
 321                                         struct scatterlist *sg, int length)
 322 {
 323         int dma_len = sg_dma_len(sg);
 324         u64 dma_addr = sg_dma_address(sg);
 325         int offset = offset_in_page(dma_addr);
 326         __le64 *prp_list;
 327         dma_addr_t prp_dma;
 328         int nprps, npages, i, prp_page;
 329         struct nvme_prps *prps = NULL;
 330
 331         cmd->prp1 = cpu_to_le64(dma_addr);
 332         length -= (PAGE_SIZE - offset);
 333         if (length <= 0)
 334                 return prps;
 335
 336         dma_len -= (PAGE_SIZE - offset);
 337         if (dma_len) {
 338                 dma_addr += (PAGE_SIZE - offset);
 339         } else {
 340                 sg = sg_next(sg);
 341                 dma_addr = sg_dma_address(sg);
 342                 dma_len = sg_dma_len(sg);
 343         }
 344
 345         if (length <= PAGE_SIZE) {
 346                 cmd->prp2 = cpu_to_le64(dma_addr);
 347                 return prps;
 348         }
 349
 350         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 351         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 352         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 353         prps->npages = npages;
 354         prp_page = 0;
 355         prp_list = alloc_prp_list(nvmeq, length, &prp_dma);
 356         prps->list[prp_page++] = prp_list;
 357         prps->first_dma = prp_dma;
 358         cmd->prp2 = cpu_to_le64(prp_dma);
 359         i = 0;
 360         for (;;) {
 361                 if (i == PAGE_SIZE / 8 - 1) {
 362                         __le64 *old_prp_list = prp_list;
 363                         prp_list = alloc_prp_list(nvmeq, length, &prp_dma);
 364                         prps->list[prp_page++] = prp_list;
 365                         old_prp_list[i] = cpu_to_le64(prp_dma);
 366                         i = 0;
 367                 }
 368                 prp_list[i++] = cpu_to_le64(dma_addr);
 369                 dma_len -= PAGE_SIZE;
 370                 dma_addr += PAGE_SIZE;
 371                 length -= PAGE_SIZE;
 372                 if (length <= 0)
 373                         break;
 374                 if (dma_len > 0)
 375                         continue;
 376                 BUG_ON(dma_len < 0);
 377                 sg = sg_next(sg);
 378                 dma_addr = sg_dma_address(sg);
 379                 dma_len = sg_dma_len(sg);
 380         }
 381
 382         return prps;
 383 }
 384
 385 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 386                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 387 {
 388         struct bio_vec *bvec;
 389         struct scatterlist *sg = nbio->sg;
 390         int i, nsegs;
 391
 392         sg_init_table(sg, psegs);
 393         bio_for_each_segment(bvec, bio, i) {
 394                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 395                 sg++;
 396                 /* XXX: handle non-mergable here */
 397                 nsegs++;
 398         }
 399         nbio->nents = nsegs;
 400
 401         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 402 }
 403
 404 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 405                                                                 struct bio *bio)
 406 {
 407         struct nvme_command *cmnd;
 408         struct nvme_bio *nbio;
 409         enum dma_data_direction dma_dir;
 410         int cmdid;
 411         u16 control;
 412         u32 dsmgmt;
 413         unsigned long flags;
 414         int psegs = bio_phys_segments(ns->queue, bio);
 415
 416         nbio = alloc_nbio(psegs, GFP_NOIO);
 417         if (!nbio)
 418                 goto congestion;
 419         nbio->bio = bio;
 420
 421         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 422         if (unlikely(cmdid < 0))
 423                 goto free_nbio;
 424
 425         control = 0;
 426         if (bio->bi_rw & REQ_FUA)
 427                 control |= NVME_RW_FUA;
 428         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 429                 control |= NVME_RW_LR;
 430
 431         dsmgmt = 0;
 432         if (bio->bi_rw & REQ_RAHEAD)
 433                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 434
 435         spin_lock_irqsave(&nvmeq->q_lock, flags);
 436         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 437
 438         memset(cmnd, 0, sizeof(*cmnd));
 439         if (bio_data_dir(bio)) {
 440                 cmnd->rw.opcode = nvme_cmd_write;
 441                 dma_dir = DMA_TO_DEVICE;
 442         } else {
 443                 cmnd->rw.opcode = nvme_cmd_read;
 444                 dma_dir = DMA_FROM_DEVICE;
 445         }
 446
 447         nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 448
 449         cmnd->rw.flags = 1;
 450         cmnd->rw.command_id = cmdid;
 451         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 452         nbio->prps = nvme_setup_prps(nvmeq, &cmnd->common, nbio->sg,
 453                                                                 bio->bi_size);
 454         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 455         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 456         cmnd->rw.control = cpu_to_le16(control);
 457         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 458
 459         writel(nvmeq->sq_tail, nvmeq->q_db);
 460         if (++nvmeq->sq_tail == nvmeq->q_depth)
 461                 nvmeq->sq_tail = 0;
 462
 463         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 464
 465         return 0;
 466
 467  free_nbio:
 468         free_nbio(nvmeq, nbio);
 469  congestion:
 470         return -EBUSY;
 471 }
 472
 473 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 474 {
 475         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 476         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 477                 bio_list_add_head(&nvmeq->sq_cong, bio);
 478         else if (bio_list_empty(&nvmeq->sq_cong))
 479                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 480         /* XXX: Need to duplicate the logic from __freed_request here */
 481 }
 482
 483 /*
 484  * NB: return value of non-zero would mean that we were a stacking driver.
 485  * make_request must always succeed.
 486  */
 487 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 488 {
 489         struct nvme_ns *ns = q->queuedata;
 490         struct nvme_queue *nvmeq = get_nvmeq(ns);
 491
 492         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 493                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 494                 spin_lock_irq(&nvmeq->q_lock);
 495                 bio_list_add(&nvmeq->sq_cong, bio);
 496                 spin_unlock_irq(&nvmeq->q_lock);
 497         }
 498         put_nvmeq(nvmeq);
 499
 500         return 0;
 501 }
 502
 503 struct sync_cmd_info {
 504         struct task_struct *task;
 505         u32 result;
 506         int status;
 507 };
 508
 509 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 510                                                 struct nvme_completion *cqe)
 511 {
 512         struct sync_cmd_info *cmdinfo = ctx;
 513         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 514                 return;
 515         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 516                 dev_warn(nvmeq->q_dmadev,
 517                                 "completed id %d twice on queue %d\n",
 518                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 519                 return;
 520         }
 521         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 522                 dev_warn(nvmeq->q_dmadev,
 523                                 "invalid id %d completed on queue %d\n",
 524                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 525                 return;
 526         }
 527         cmdinfo->result = le32_to_cpup(&cqe->result);
 528         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 529         wake_up_process(cmdinfo->task);
 530 }
 531
 532 typedef void (*completion_fn)(struct nvme_queue *, void *,
 533                                                 struct nvme_completion *);
 534
 535 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 536 {
 537         u16 head, phase;
 538
 539         static const completion_fn completions[4] = {
 540                 [sync_completion_id] = sync_completion,
 541                 [bio_completion_id]  = bio_completion,
 542         };
 543
 544         head = nvmeq->cq_head;
 545         phase = nvmeq->cq_phase;
 546
 547         for (;;) {
 548                 unsigned long data;
 549                 void *ptr;
 550                 unsigned char handler;
 551                 struct nvme_completion cqe = nvmeq->cqes[head];
 552                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 553                         break;
 554                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 555                 if (++head == nvmeq->q_depth) {
 556                         head = 0;
 557                         phase = !phase;
 558                 }
 559
 560                 data = free_cmdid(nvmeq, cqe.command_id);
 561                 handler = data & 3;
 562                 ptr = (void *)(data & ~3UL);
 563                 completions[handler](nvmeq, ptr, &cqe);
 564         }
 565
 566         /* If the controller ignores the cq head doorbell and continuously
 567          * writes to the queue, it is theoretically possible to wrap around
 568          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 569          * requires that 0.1% of your interrupts are handled, so this isn't
 570          * a big problem.
 571          */
 572         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 573                 return IRQ_NONE;
 574
 575         writel(head, nvmeq->q_db + 1);
 576         nvmeq->cq_head = head;
 577         nvmeq->cq_phase = phase;
 578
 579         return IRQ_HANDLED;
 580 }
 581
 582 static irqreturn_t nvme_irq(int irq, void *data)
 583 {
 584         irqreturn_t result;
 585         struct nvme_queue *nvmeq = data;
 586         spin_lock(&nvmeq->q_lock);
 587         result = nvme_process_cq(nvmeq);
 588         spin_unlock(&nvmeq->q_lock);
 589         return result;
 590 }
 591
 592 static irqreturn_t nvme_irq_check(int irq, void *data)
 593 {
 594         struct nvme_queue *nvmeq = data;
 595         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 596         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 597                 return IRQ_NONE;
 598         return IRQ_WAKE_THREAD;
 599 }
 600
 601 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 602 {
 603         spin_lock_irq(&nvmeq->q_lock);
 604         cancel_cmdid_data(nvmeq, cmdid);
 605         spin_unlock_irq(&nvmeq->q_lock);
 606 }
 607
 608 /*
 609  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 610  * if the result is positive, it's an NVM Express status code
 611  */
 612 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 613                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 614 {
 615         int cmdid;
 616         struct sync_cmd_info cmdinfo;
 617
 618         cmdinfo.task = current;
 619         cmdinfo.status = -EINTR;
 620
 621         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 622                                                                 timeout);
 623         if (cmdid < 0)
 624                 return cmdid;
 625         cmd->common.command_id = cmdid;
 626
 627         set_current_state(TASK_KILLABLE);
 628         nvme_submit_cmd(nvmeq, cmd);
 629         schedule();
 630
 631         if (cmdinfo.status == -EINTR) {
 632                 nvme_abort_command(nvmeq, cmdid);
 633                 return -EINTR;
 634         }
 635
 636         if (result)
 637                 *result = cmdinfo.result;
 638
 639         return cmdinfo.status;
 640 }
 641
 642 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 643                                                                 u32 *result)
 644 {
 645         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 646 }
 647
 648 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 649 {
 650         int status;
 651         struct nvme_command c;
 652
 653         memset(&c, 0, sizeof(c));
 654         c.delete_queue.opcode = opcode;
 655         c.delete_queue.qid = cpu_to_le16(id);
 656
 657         status = nvme_submit_admin_cmd(dev, &c, NULL);
 658         if (status)
 659                 return -EIO;
 660         return 0;
 661 }
 662
 663 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 664                                                 struct nvme_queue *nvmeq)
 665 {
 666         int status;
 667         struct nvme_command c;
 668         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 669
 670         memset(&c, 0, sizeof(c));
 671         c.create_cq.opcode = nvme_admin_create_cq;
 672         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 673         c.create_cq.cqid = cpu_to_le16(qid);
 674         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 675         c.create_cq.cq_flags = cpu_to_le16(flags);
 676         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 677
 678         status = nvme_submit_admin_cmd(dev, &c, NULL);
 679         if (status)
 680                 return -EIO;
 681         return 0;
 682 }
 683
 684 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 685                                                 struct nvme_queue *nvmeq)
 686 {
 687         int status;
 688         struct nvme_command c;
 689         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 690
 691         memset(&c, 0, sizeof(c));
 692         c.create_sq.opcode = nvme_admin_create_sq;
 693         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 694         c.create_sq.sqid = cpu_to_le16(qid);
 695         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 696         c.create_sq.sq_flags = cpu_to_le16(flags);
 697         c.create_sq.cqid = cpu_to_le16(qid);
 698
 699         status = nvme_submit_admin_cmd(dev, &c, NULL);
 700         if (status)
 701                 return -EIO;
 702         return 0;
 703 }
 704
 705 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 706 {
 707         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 708 }
 709
 710 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 711 {
 712         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 713 }
 714
 715 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 716 {
 717         struct nvme_queue *nvmeq = dev->queues[qid];
 718
 719         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 720
 721         /* Don't tell the adapter to delete the admin queue */
 722         if (qid) {
 723                 adapter_delete_sq(dev, qid);
 724                 adapter_delete_cq(dev, qid);
 725         }
 726
 727         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 728                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 729         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 730                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 731         kfree(nvmeq);
 732 }
 733
 734 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 735                                                         int depth, int vector)
 736 {
 737         struct device *dmadev = &dev->pci_dev->dev;
 738         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 739         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 740         if (!nvmeq)
 741                 return NULL;
 742
 743         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 744                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 745         if (!nvmeq->cqes)
 746                 goto free_nvmeq;
 747         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 748
 749         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 750                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 751         if (!nvmeq->sq_cmds)
 752                 goto free_cqdma;
 753
 754         nvmeq->q_dmadev = dmadev;
 755         spin_lock_init(&nvmeq->q_lock);
 756         nvmeq->cq_head = 0;
 757         nvmeq->cq_phase = 1;
 758         init_waitqueue_head(&nvmeq->sq_full);
 759         bio_list_init(&nvmeq->sq_cong);
 760         nvmeq->q_db = &dev->dbs[qid * 2];
 761         nvmeq->q_depth = depth;
 762         nvmeq->cq_vector = vector;
 763
 764         return nvmeq;
 765
 766  free_cqdma:
 767         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 768                                                         nvmeq->cq_dma_addr);
 769  free_nvmeq:
 770         kfree(nvmeq);
 771         return NULL;
 772 }
 773
 774 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 775                                                         const char *name)
 776 {
 777         if (use_threaded_interrupts)
 778                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 779                                         nvme_irq_check, nvme_irq,
 780                                         IRQF_DISABLED | IRQF_SHARED,
 781                                         name, nvmeq);
 782         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 783                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 784 }
 785
 786 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 787                                         int qid, int cq_size, int vector)
 788 {
 789         int result;
 790         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 791
 792         if (!nvmeq)
 793                 return NULL;
 794
 795         result = adapter_alloc_cq(dev, qid, nvmeq);
 796         if (result < 0)
 797                 goto free_nvmeq;
 798
 799         result = adapter_alloc_sq(dev, qid, nvmeq);
 800         if (result < 0)
 801                 goto release_cq;
 802
 803         result = queue_request_irq(dev, nvmeq, "nvme");
 804         if (result < 0)
 805                 goto release_sq;
 806
 807         return nvmeq;
 808
 809  release_sq:
 810         adapter_delete_sq(dev, qid);
 811  release_cq:
 812         adapter_delete_cq(dev, qid);
 813  free_nvmeq:
 814         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 815                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 816         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 817                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 818         kfree(nvmeq);
 819         return NULL;
 820 }
 821
 822 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 823 {
 824         int result;
 825         u32 aqa;
 826         struct nvme_queue *nvmeq;
 827
 828         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 829
 830         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 831         if (!nvmeq)
 832                 return -ENOMEM;
 833
 834         aqa = nvmeq->q_depth - 1;
 835         aqa |= aqa << 16;
 836
 837         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 838         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 839         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 840
 841         writel(0, &dev->bar->cc);
 842         writel(aqa, &dev->bar->aqa);
 843         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 844         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 845         writel(dev->ctrl_config, &dev->bar->cc);
 846
 847         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 848                 msleep(100);
 849                 if (fatal_signal_pending(current))
 850                         return -EINTR;
 851         }
 852
 853         result = queue_request_irq(dev, nvmeq, "nvme admin");
 854         dev->queues[0] = nvmeq;
 855         return result;
 856 }
 857
 858 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 859                                 unsigned long addr, unsigned length,
 860                                 struct scatterlist **sgp)
 861 {
 862         int i, err, count, nents, offset;
 863         struct scatterlist *sg;
 864         struct page **pages;
 865
 866         if (addr & 3)
 867                 return -EINVAL;
 868         if (!length)
 869                 return -EINVAL;
 870
 871         offset = offset_in_page(addr);
 872         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 873         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 874
 875         err = get_user_pages_fast(addr, count, 1, pages);
 876         if (err < count) {
 877                 count = err;
 878                 err = -EFAULT;
 879                 goto put_pages;
 880         }
 881
 882         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 883         sg_init_table(sg, count);
 884         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 885         length -= (PAGE_SIZE - offset);
 886         for (i = 1; i < count; i++) {
 887                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 888                 length -= PAGE_SIZE;
 889         }
 890
 891         err = -ENOMEM;
 892         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 893                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 894         if (!nents)
 895                 goto put_pages;
 896
 897         kfree(pages);
 898         *sgp = sg;
 899         return nents;
 900
 901  put_pages:
 902         for (i = 0; i < count; i++)
 903                 put_page(pages[i]);
 904         kfree(pages);
 905         return err;
 906 }
 907
 908 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 909                                 unsigned long addr, int length,
 910                                 struct scatterlist *sg, int nents)
 911 {
 912         int i, count;
 913
 914         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 915         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 916
 917         for (i = 0; i < count; i++)
 918                 put_page(sg_page(&sg[i]));
 919 }
 920
 921 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 922                                         unsigned long addr, unsigned length,
 923                                         struct nvme_command *cmd)
 924 {
 925         int err, nents;
 926         struct scatterlist *sg;
 927         struct nvme_prps *prps;
 928
 929         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 930         if (nents < 0)
 931                 return nents;
 932         prps = nvme_setup_prps(dev->queues[0], &cmd->common, sg, length);
 933         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 934         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 935         nvme_free_prps(dev->queues[0], prps);
 936         return err ? -EIO : 0;
 937 }
 938
 939 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 940 {
 941         struct nvme_command c;
 942
 943         memset(&c, 0, sizeof(c));
 944         c.identify.opcode = nvme_admin_identify;
 945         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 946         c.identify.cns = cpu_to_le32(cns);
 947
 948         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 949 }
 950
 951 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 952 {
 953         struct nvme_command c;
 954
 955         memset(&c, 0, sizeof(c));
 956         c.features.opcode = nvme_admin_get_features;
 957         c.features.nsid = cpu_to_le32(ns->ns_id);
 958         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 959
 960         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 961 }
 962
 963 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 964 {
 965         struct nvme_dev *dev = ns->dev;
 966         struct nvme_queue *nvmeq;
 967         struct nvme_user_io io;
 968         struct nvme_command c;
 969         unsigned length;
 970         u32 result;
 971         int nents, status;
 972         struct scatterlist *sg;
 973         struct nvme_prps *prps;
 974
 975         if (copy_from_user(&io, uio, sizeof(io)))
 976                 return -EFAULT;
 977         length = io.nblocks << io.block_shift;
 978         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 979         if (nents < 0)
 980                 return nents;
 981
 982         memset(&c, 0, sizeof(c));
 983         c.rw.opcode = io.opcode;
 984         c.rw.flags = io.flags;
 985         c.rw.nsid = cpu_to_le32(io.nsid);
 986         c.rw.slba = cpu_to_le64(io.slba);
 987         c.rw.length = cpu_to_le16(io.nblocks - 1);
 988         c.rw.control = cpu_to_le16(io.control);
 989         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
 990         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
 991         c.rw.apptag = cpu_to_le16(io.apptag);
 992         c.rw.appmask = cpu_to_le16(io.appmask);
 993         nvmeq = get_nvmeq(ns);
 994         /* XXX: metadata */
 995         prps = nvme_setup_prps(nvmeq, &c.common, sg, length);
 996
 997         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
 998          * disabled.  We may be preempted at any point, and be rescheduled
 999          * to a different CPU.  That will cause cacheline bouncing, but no
1000          * additional races since q_lock already protects against other CPUs.
1001          */
1002         put_nvmeq(nvmeq);
1003         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1004
1005         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1006         nvme_free_prps(nvmeq, prps);
1007         put_user(result, &uio->result);
1008         return status;
1009 }
1010
1011 static int nvme_download_firmware(struct nvme_ns *ns,
1012                                                 struct nvme_dlfw __user *udlfw)
1013 {
1014         struct nvme_dev *dev = ns->dev;
1015         struct nvme_dlfw dlfw;
1016         struct nvme_command c;
1017         int nents, status;
1018         struct scatterlist *sg;
1019         struct nvme_prps *prps;
1020
1021         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1022                 return -EFAULT;
1023         if (dlfw.length >= (1 << 30))
1024                 return -EINVAL;
1025
1026         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1027         if (nents < 0)
1028                 return nents;
1029
1030         memset(&c, 0, sizeof(c));
1031         c.dlfw.opcode = nvme_admin_download_fw;
1032         c.dlfw.numd = cpu_to_le32(dlfw.length);
1033         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1034         prps = nvme_setup_prps(dev->queues[0], &c.common, sg, dlfw.length * 4);
1035
1036         status = nvme_submit_admin_cmd(dev, &c, NULL);
1037         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1038         nvme_free_prps(dev->queues[0], prps);
1039         return status;
1040 }
1041
1042 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1043 {
1044         struct nvme_dev *dev = ns->dev;
1045         struct nvme_command c;
1046
1047         memset(&c, 0, sizeof(c));
1048         c.common.opcode = nvme_admin_activate_fw;
1049         c.common.rsvd10[0] = cpu_to_le32(arg);
1050
1051         return nvme_submit_admin_cmd(dev, &c, NULL);
1052 }
1053
1054 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1055                                                         unsigned long arg)
1056 {
1057         struct nvme_ns *ns = bdev->bd_disk->private_data;
1058
1059         switch (cmd) {
1060         case NVME_IOCTL_IDENTIFY_NS:
1061                 return nvme_identify(ns, arg, 0);
1062         case NVME_IOCTL_IDENTIFY_CTRL:
1063                 return nvme_identify(ns, arg, 1);
1064         case NVME_IOCTL_GET_RANGE_TYPE:
1065                 return nvme_get_range_type(ns, arg);
1066         case NVME_IOCTL_SUBMIT_IO:
1067                 return nvme_submit_io(ns, (void __user *)arg);
1068         case NVME_IOCTL_DOWNLOAD_FW:
1069                 return nvme_download_firmware(ns, (void __user *)arg);
1070         case NVME_IOCTL_ACTIVATE_FW:
1071                 return nvme_activate_firmware(ns, arg);
1072         default:
1073                 return -ENOTTY;
1074         }
1075 }
1076
1077 static const struct block_device_operations nvme_fops = {
1078         .owner          = THIS_MODULE,
1079         .ioctl          = nvme_ioctl,
1080 };
1081
1082 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1083                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1084 {
1085         struct nvme_ns *ns;
1086         struct gendisk *disk;
1087         int lbaf;
1088
1089         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1090                 return NULL;
1091
1092         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1093         if (!ns)
1094                 return NULL;
1095         ns->queue = blk_alloc_queue(GFP_KERNEL);
1096         if (!ns->queue)
1097                 goto out_free_ns;
1098         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1099                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1100         blk_queue_make_request(ns->queue, nvme_make_request);
1101         ns->dev = dev;
1102         ns->queue->queuedata = ns;
1103
1104         disk = alloc_disk(NVME_MINORS);
1105         if (!disk)
1106                 goto out_free_queue;
1107         ns->ns_id = index;
1108         ns->disk = disk;
1109         lbaf = id->flbas & 0xf;
1110         ns->lba_shift = id->lbaf[lbaf].ds;
1111
1112         disk->major = nvme_major;
1113         disk->minors = NVME_MINORS;
1114         disk->first_minor = NVME_MINORS * index;
1115         disk->fops = &nvme_fops;
1116         disk->private_data = ns;
1117         disk->queue = ns->queue;
1118         disk->driverfs_dev = &dev->pci_dev->dev;
1119         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1120         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1121
1122         return ns;
1123
1124  out_free_queue:
1125         blk_cleanup_queue(ns->queue);
1126  out_free_ns:
1127         kfree(ns);
1128         return NULL;
1129 }
1130
1131 static void nvme_ns_free(struct nvme_ns *ns)
1132 {
1133         put_disk(ns->disk);
1134         blk_cleanup_queue(ns->queue);
1135         kfree(ns);
1136 }
1137
1138 static int set_queue_count(struct nvme_dev *dev, int count)
1139 {
1140         int status;
1141         u32 result;
1142         struct nvme_command c;
1143         u32 q_count = (count - 1) | ((count - 1) << 16);
1144
1145         memset(&c, 0, sizeof(c));
1146         c.features.opcode = nvme_admin_get_features;
1147         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1148         c.features.dword11 = cpu_to_le32(q_count);
1149
1150         status = nvme_submit_admin_cmd(dev, &c, &result);
1151         if (status)
1152                 return -EIO;
1153         return min(result & 0xffff, result >> 16) + 1;
1154 }
1155
1156 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1157 {
1158         int result, cpu, i, nr_queues;
1159
1160         nr_queues = num_online_cpus();
1161         result = set_queue_count(dev, nr_queues);
1162         if (result < 0)
1163                 return result;
1164         if (result < nr_queues)
1165                 nr_queues = result;
1166
1167         /* Deregister the admin queue's interrupt */
1168         free_irq(dev->entry[0].vector, dev->queues[0]);
1169
1170         for (i = 0; i < nr_queues; i++)
1171                 dev->entry[i].entry = i;
1172         for (;;) {
1173                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1174                 if (result == 0) {
1175                         break;
1176                 } else if (result > 0) {
1177                         nr_queues = result;
1178                         continue;
1179                 } else {
1180                         nr_queues = 1;
1181                         break;
1182                 }
1183         }
1184
1185         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1186         /* XXX: handle failure here */
1187
1188         cpu = cpumask_first(cpu_online_mask);
1189         for (i = 0; i < nr_queues; i++) {
1190                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1191                 cpu = cpumask_next(cpu, cpu_online_mask);
1192         }
1193
1194         for (i = 0; i < nr_queues; i++) {
1195                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1196                                                         NVME_Q_DEPTH, i);
1197                 if (!dev->queues[i + 1])
1198                         return -ENOMEM;
1199                 dev->queue_count++;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static void nvme_free_queues(struct nvme_dev *dev)
1206 {
1207         int i;
1208
1209         for (i = dev->queue_count - 1; i >= 0; i--)
1210                 nvme_free_queue(dev, i);
1211 }
1212
1213 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1214 {
1215         int res, nn, i;
1216         struct nvme_ns *ns, *next;
1217         struct nvme_id_ctrl *ctrl;
1218         void *id;
1219         dma_addr_t dma_addr;
1220         struct nvme_command cid, crt;
1221
1222         res = nvme_setup_io_queues(dev);
1223         if (res)
1224                 return res;
1225
1226         /* XXX: Switch to a SG list once prp2 works */
1227         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1228                                                                 GFP_KERNEL);
1229
1230         memset(&cid, 0, sizeof(cid));
1231         cid.identify.opcode = nvme_admin_identify;
1232         cid.identify.nsid = 0;
1233         cid.identify.prp1 = cpu_to_le64(dma_addr);
1234         cid.identify.cns = cpu_to_le32(1);
1235
1236         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1237         if (res) {
1238                 res = -EIO;
1239                 goto out_free;
1240         }
1241
1242         ctrl = id;
1243         nn = le32_to_cpup(&ctrl->nn);
1244         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1245         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1246         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1247
1248         cid.identify.cns = 0;
1249         memset(&crt, 0, sizeof(crt));
1250         crt.features.opcode = nvme_admin_get_features;
1251         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1252         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1253
1254         for (i = 0; i < nn; i++) {
1255                 cid.identify.nsid = cpu_to_le32(i);
1256                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1257                 if (res)
1258                         continue;
1259
1260                 if (((struct nvme_id_ns *)id)->ncap == 0)
1261                         continue;
1262
1263                 crt.features.nsid = cpu_to_le32(i);
1264                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1265                 if (res)
1266                         continue;
1267
1268                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1269                 if (ns)
1270                         list_add_tail(&ns->list, &dev->namespaces);
1271         }
1272         list_for_each_entry(ns, &dev->namespaces, list)
1273                 add_disk(ns->disk);
1274
1275         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1276         return 0;
1277
1278  out_free:
1279         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1280                 list_del(&ns->list);
1281                 nvme_ns_free(ns);
1282         }
1283
1284         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1285         return res;
1286 }
1287
1288 static int nvme_dev_remove(struct nvme_dev *dev)
1289 {
1290         struct nvme_ns *ns, *next;
1291
1292         /* TODO: wait all I/O finished or cancel them */
1293
1294         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1295                 list_del(&ns->list);
1296                 del_gendisk(ns->disk);
1297                 nvme_ns_free(ns);
1298         }
1299
1300         nvme_free_queues(dev);
1301
1302         return 0;
1303 }
1304
1305 /* XXX: Use an ida or something to let remove / add work correctly */
1306 static void nvme_set_instance(struct nvme_dev *dev)
1307 {
1308         static int instance;
1309         dev->instance = instance++;
1310 }
1311
1312 static void nvme_release_instance(struct nvme_dev *dev)
1313 {
1314 }
1315
1316 static int __devinit nvme_probe(struct pci_dev *pdev,
1317                                                 const struct pci_device_id *id)
1318 {
1319         int bars, result = -ENOMEM;
1320         struct nvme_dev *dev;
1321
1322         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1323         if (!dev)
1324                 return -ENOMEM;
1325         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1326                                                                 GFP_KERNEL);
1327         if (!dev->entry)
1328                 goto free;
1329         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1330                                                                 GFP_KERNEL);
1331         if (!dev->queues)
1332                 goto free;
1333
1334         if (pci_enable_device_mem(pdev))
1335                 goto free;
1336         pci_set_master(pdev);
1337         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1338         if (pci_request_selected_regions(pdev, bars, "nvme"))
1339                 goto disable;
1340
1341         INIT_LIST_HEAD(&dev->namespaces);
1342         dev->pci_dev = pdev;
1343         pci_set_drvdata(pdev, dev);
1344         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1345         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1346         nvme_set_instance(dev);
1347         dev->entry[0].vector = pdev->irq;
1348
1349         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1350         if (!dev->bar) {
1351                 result = -ENOMEM;
1352                 goto disable_msix;
1353         }
1354
1355         result = nvme_configure_admin_queue(dev);
1356         if (result)
1357                 goto unmap;
1358         dev->queue_count++;
1359
1360         result = nvme_dev_add(dev);
1361         if (result)
1362                 goto delete;
1363         return 0;
1364
1365  delete:
1366         nvme_free_queues(dev);
1367  unmap:
1368         iounmap(dev->bar);
1369  disable_msix:
1370         pci_disable_msix(pdev);
1371         nvme_release_instance(dev);
1372  disable:
1373         pci_disable_device(pdev);
1374         pci_release_regions(pdev);
1375  free:
1376         kfree(dev->queues);
1377         kfree(dev->entry);
1378         kfree(dev);
1379         return result;
1380 }
1381
1382 static void __devexit nvme_remove(struct pci_dev *pdev)
1383 {
1384         struct nvme_dev *dev = pci_get_drvdata(pdev);
1385         nvme_dev_remove(dev);
1386         pci_disable_msix(pdev);
1387         iounmap(dev->bar);
1388         nvme_release_instance(dev);
1389         pci_disable_device(pdev);
1390         pci_release_regions(pdev);
1391         kfree(dev->queues);
1392         kfree(dev->entry);
1393         kfree(dev);
1394 }
1395
1396 /* These functions are yet to be implemented */
1397 #define nvme_error_detected NULL
1398 #define nvme_dump_registers NULL
1399 #define nvme_link_reset NULL
1400 #define nvme_slot_reset NULL
1401 #define nvme_error_resume NULL
1402 #define nvme_suspend NULL
1403 #define nvme_resume NULL
1404
1405 static struct pci_error_handlers nvme_err_handler = {
1406         .error_detected = nvme_error_detected,
1407         .mmio_enabled   = nvme_dump_registers,
1408         .link_reset     = nvme_link_reset,
1409         .slot_reset     = nvme_slot_reset,
1410         .resume         = nvme_error_resume,
1411 };
1412
1413 /* Move to pci_ids.h later */
1414 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1415
1416 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1417         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1418         { 0, }
1419 };
1420 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1421
1422 static struct pci_driver nvme_driver = {
1423         .name           = "nvme",
1424         .id_table       = nvme_id_table,
1425         .probe          = nvme_probe,
1426         .remove         = __devexit_p(nvme_remove),
1427         .suspend        = nvme_suspend,
1428         .resume         = nvme_resume,
1429         .err_handler    = &nvme_err_handler,
1430 };
1431
1432 static int __init nvme_init(void)
1433 {
1434         int result;
1435
1436         nvme_major = register_blkdev(nvme_major, "nvme");
1437         if (nvme_major <= 0)
1438                 return -EBUSY;
1439
1440         result = pci_register_driver(&nvme_driver);
1441         if (!result)
1442                 return 0;
1443
1444         unregister_blkdev(nvme_major, "nvme");
1445         return result;
1446 }
1447
1448 static void __exit nvme_exit(void)
1449 {
1450         pci_unregister_driver(&nvme_driver);
1451         unregister_blkdev(nvme_major, "nvme");
1452 }
1453
1454 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1455 MODULE_LICENSE("GPL");
1456 MODULE_VERSION("0.2");
1457 module_init(nvme_init);
1458 module_exit(nvme_exit);