drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/poison.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/version.h>
  40
  41 #define NVME_Q_DEPTH 1024
  42 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  43 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  44 #define NVME_MINORS 64
  45 #define IO_TIMEOUT      (5 * HZ)
  46 #define ADMIN_TIMEOUT   (60 * HZ)
  47
  48 static int nvme_major;
  49 module_param(nvme_major, int, 0);
  50
  51 static int use_threaded_interrupts;
  52 module_param(use_threaded_interrupts, int, 0);
  53
  54 static DEFINE_SPINLOCK(dev_list_lock);
  55 static LIST_HEAD(dev_list);
  56 static struct task_struct *nvme_thread;
  57
  58 /*
  59  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  60  */
  61 struct nvme_dev {
  62         struct list_head node;
  63         struct nvme_queue **queues;
  64         u32 __iomem *dbs;
  65         struct pci_dev *pci_dev;
  66         struct dma_pool *prp_page_pool;
  67         struct dma_pool *prp_small_pool;
  68         int instance;
  69         int queue_count;
  70         u32 ctrl_config;
  71         struct msix_entry *entry;
  72         struct nvme_bar __iomem *bar;
  73         struct list_head namespaces;
  74         char serial[20];
  75         char model[40];
  76         char firmware_rev[8];
  77 };
  78
  79 /*
  80  * An NVM Express namespace is equivalent to a SCSI LUN
  81  */
  82 struct nvme_ns {
  83         struct list_head list;
  84
  85         struct nvme_dev *dev;
  86         struct request_queue *queue;
  87         struct gendisk *disk;
  88
  89         int ns_id;
  90         int lba_shift;
  91 };
  92
  93 /*
  94  * An NVM Express queue.  Each device has at least two (one for admin
  95  * commands and one for I/O commands).
  96  */
  97 struct nvme_queue {
  98         struct device *q_dmadev;
  99         struct nvme_dev *dev;
 100         spinlock_t q_lock;
 101         struct nvme_command *sq_cmds;
 102         volatile struct nvme_completion *cqes;
 103         dma_addr_t sq_dma_addr;
 104         dma_addr_t cq_dma_addr;
 105         wait_queue_head_t sq_full;
 106         wait_queue_t sq_cong_wait;
 107         struct bio_list sq_cong;
 108         u32 __iomem *q_db;
 109         u16 q_depth;
 110         u16 cq_vector;
 111         u16 sq_head;
 112         u16 sq_tail;
 113         u16 cq_head;
 114         u16 cq_phase;
 115         unsigned long cmdid_data[];
 116 };
 117
 118 /*
 119  * Check we didin't inadvertently grow the command struct
 120  */
 121 static inline void _nvme_check_size(void)
 122 {
 123         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 132 }
 133
 134 struct nvme_cmd_info {
 135         unsigned long ctx;
 136         unsigned long timeout;
 137 };
 138
 139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 140 {
 141         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 142 }
 143
 144 /**
 145  * alloc_cmdid() - Allocate a Command ID
 146  * @nvmeq: The queue that will be used for this command
 147  * @ctx: A pointer that will be passed to the handler
 148  * @handler: The ID of the handler to call
 149  *
 150  * Allocate a Command ID for a queue.  The data passed in will
 151  * be passed to the completion handler.  This is implemented by using
 152  * the bottom two bits of the ctx pointer to store the handler ID.
 153  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 154  * We can change this if it becomes a problem.
 155  */
 156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 157                                                         unsigned timeout)
 158 {
 159         int depth = nvmeq->q_depth - 1;
 160         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 161         int cmdid;
 162
 163         BUG_ON((unsigned long)ctx & 3);
 164
 165         do {
 166                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 167                 if (cmdid >= depth)
 168                         return -EBUSY;
 169         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 170
 171         info[cmdid].ctx = (unsigned long)ctx | handler;
 172         info[cmdid].timeout = jiffies + timeout;
 173         return cmdid;
 174 }
 175
 176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 177                                                 int handler, unsigned timeout)
 178 {
 179         int cmdid;
 180         wait_event_killable(nvmeq->sq_full,
 181                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 182         return (cmdid < 0) ? -EINTR : cmdid;
 183 }
 184
 185 /*
 186  * If you need more than four handlers, you'll need to change how
 187  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 188  * CMD_CTX value instead, if that works for your situation.
 189  */
 190 enum {
 191         sync_completion_id = 0,
 192         bio_completion_id,
 193 };
 194
 195 /* Special values must be a multiple of 4, and less than 0x1000 */
 196 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 197 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 198 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 199 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 200 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 201
 202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 203 {
 204         unsigned long data;
 205         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 206
 207         if (cmdid >= nvmeq->q_depth)
 208                 return CMD_CTX_INVALID;
 209         data = info[cmdid].ctx;
 210         info[cmdid].ctx = CMD_CTX_COMPLETED;
 211         clear_bit(cmdid, nvmeq->cmdid_data);
 212         wake_up(&nvmeq->sq_full);
 213         return data;
 214 }
 215
 216 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 217 {
 218         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 219         info[cmdid].ctx = CMD_CTX_CANCELLED;
 220 }
 221
 222 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 223 {
 224         int qid, cpu = get_cpu();
 225         if (cpu < ns->dev->queue_count)
 226                 qid = cpu + 1;
 227         else
 228                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 229         return ns->dev->queues[qid];
 230 }
 231
 232 static void put_nvmeq(struct nvme_queue *nvmeq)
 233 {
 234         put_cpu();
 235 }
 236
 237 /**
 238  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 239  * @nvmeq: The queue to use
 240  * @cmd: The command to send
 241  *
 242  * Safe to use from interrupt context
 243  */
 244 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 245 {
 246         unsigned long flags;
 247         u16 tail;
 248         spin_lock_irqsave(&nvmeq->q_lock, flags);
 249         tail = nvmeq->sq_tail;
 250         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 251         if (++tail == nvmeq->q_depth)
 252                 tail = 0;
 253         writel(tail, nvmeq->q_db);
 254         nvmeq->sq_tail = tail;
 255         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 256
 257         return 0;
 258 }
 259
 260 struct nvme_prps {
 261         int npages;
 262         dma_addr_t first_dma;
 263         __le64 *list[0];
 264 };
 265
 266 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 267 {
 268         const int last_prp = PAGE_SIZE / 8 - 1;
 269         int i;
 270         dma_addr_t prp_dma;
 271
 272         if (!prps)
 273                 return;
 274
 275         prp_dma = prps->first_dma;
 276
 277         if (prps->npages == 0)
 278                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 279         for (i = 0; i < prps->npages; i++) {
 280                 __le64 *prp_list = prps->list[i];
 281                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 282                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 283                 prp_dma = next_prp_dma;
 284         }
 285         kfree(prps);
 286 }
 287
 288 struct nvme_bio {
 289         struct bio *bio;
 290         int nents;
 291         struct nvme_prps *prps;
 292         struct scatterlist sg[0];
 293 };
 294
 295 /* XXX: use a mempool */
 296 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 297 {
 298         return kzalloc(sizeof(struct nvme_bio) +
 299                         sizeof(struct scatterlist) * nseg, gfp);
 300 }
 301
 302 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 303 {
 304         nvme_free_prps(nvmeq->dev, nbio->prps);
 305         kfree(nbio);
 306 }
 307
 308 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 309                                                 struct nvme_completion *cqe)
 310 {
 311         struct nvme_bio *nbio = ctx;
 312         struct bio *bio = nbio->bio;
 313         u16 status = le16_to_cpup(&cqe->status) >> 1;
 314
 315         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 316                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 317         free_nbio(nvmeq, nbio);
 318         if (status)
 319                 bio_endio(bio, -EIO);
 320         if (bio->bi_vcnt > bio->bi_idx) {
 321                 bio_list_add(&nvmeq->sq_cong, bio);
 322                 wake_up_process(nvme_thread);
 323         } else {
 324                 bio_endio(bio, 0);
 325         }
 326 }
 327
 328 /* length is in bytes */
 329 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 330                                         struct nvme_common_command *cmd,
 331                                         struct scatterlist *sg, int length)
 332 {
 333         struct dma_pool *pool;
 334         int dma_len = sg_dma_len(sg);
 335         u64 dma_addr = sg_dma_address(sg);
 336         int offset = offset_in_page(dma_addr);
 337         __le64 *prp_list;
 338         dma_addr_t prp_dma;
 339         int nprps, npages, i, prp_page;
 340         struct nvme_prps *prps = NULL;
 341
 342         cmd->prp1 = cpu_to_le64(dma_addr);
 343         length -= (PAGE_SIZE - offset);
 344         if (length <= 0)
 345                 return prps;
 346
 347         dma_len -= (PAGE_SIZE - offset);
 348         if (dma_len) {
 349                 dma_addr += (PAGE_SIZE - offset);
 350         } else {
 351                 sg = sg_next(sg);
 352                 dma_addr = sg_dma_address(sg);
 353                 dma_len = sg_dma_len(sg);
 354         }
 355
 356         if (length <= PAGE_SIZE) {
 357                 cmd->prp2 = cpu_to_le64(dma_addr);
 358                 return prps;
 359         }
 360
 361         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 362         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 363         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 364         prp_page = 0;
 365         if (nprps <= (256 / 8)) {
 366                 pool = dev->prp_small_pool;
 367                 prps->npages = 0;
 368         } else {
 369                 pool = dev->prp_page_pool;
 370                 prps->npages = npages;
 371         }
 372
 373         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 374         prps->list[prp_page++] = prp_list;
 375         prps->first_dma = prp_dma;
 376         cmd->prp2 = cpu_to_le64(prp_dma);
 377         i = 0;
 378         for (;;) {
 379                 if (i == PAGE_SIZE / 8 - 1) {
 380                         __le64 *old_prp_list = prp_list;
 381                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 382                         prps->list[prp_page++] = prp_list;
 383                         old_prp_list[i] = cpu_to_le64(prp_dma);
 384                         i = 0;
 385                 }
 386                 prp_list[i++] = cpu_to_le64(dma_addr);
 387                 dma_len -= PAGE_SIZE;
 388                 dma_addr += PAGE_SIZE;
 389                 length -= PAGE_SIZE;
 390                 if (length <= 0)
 391                         break;
 392                 if (dma_len > 0)
 393                         continue;
 394                 BUG_ON(dma_len < 0);
 395                 sg = sg_next(sg);
 396                 dma_addr = sg_dma_address(sg);
 397                 dma_len = sg_dma_len(sg);
 398         }
 399
 400         return prps;
 401 }
 402
 403 /* NVMe scatterlists require no holes in the virtual address */
 404 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 405                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 406
 407 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 408                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 409 {
 410         struct bio_vec *bvec, *bvprv = NULL;
 411         struct scatterlist *sg = NULL;
 412         int i, old_idx, length = 0, nsegs = 0;
 413
 414         sg_init_table(nbio->sg, psegs);
 415         old_idx = bio->bi_idx;
 416         bio_for_each_segment(bvec, bio, i) {
 417                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 418                         sg->length += bvec->bv_len;
 419                 } else {
 420                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 421                                 break;
 422                         sg = sg ? sg + 1 : nbio->sg;
 423                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 424                                                         bvec->bv_offset);
 425                         nsegs++;
 426                 }
 427                 length += bvec->bv_len;
 428                 bvprv = bvec;
 429         }
 430         bio->bi_idx = i;
 431         nbio->nents = nsegs;
 432         sg_mark_end(sg);
 433         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 434                 bio->bi_idx = old_idx;
 435                 return -ENOMEM;
 436         }
 437         return length;
 438 }
 439
 440 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 441                                                                 int cmdid)
 442 {
 443         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 444
 445         memset(cmnd, 0, sizeof(*cmnd));
 446         cmnd->common.opcode = nvme_cmd_flush;
 447         cmnd->common.command_id = cmdid;
 448         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 449
 450         if (++nvmeq->sq_tail == nvmeq->q_depth)
 451                 nvmeq->sq_tail = 0;
 452         writel(nvmeq->sq_tail, nvmeq->q_db);
 453
 454         return 0;
 455 }
 456
 457 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 458 {
 459         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 460                                                 sync_completion_id, IO_TIMEOUT);
 461         if (unlikely(cmdid < 0))
 462                 return cmdid;
 463
 464         return nvme_submit_flush(nvmeq, ns, cmdid);
 465 }
 466
 467 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 468                                                                 struct bio *bio)
 469 {
 470         struct nvme_command *cmnd;
 471         struct nvme_bio *nbio;
 472         enum dma_data_direction dma_dir;
 473         int cmdid, length, result = -ENOMEM;
 474         u16 control;
 475         u32 dsmgmt;
 476         int psegs = bio_phys_segments(ns->queue, bio);
 477
 478         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 479                 result = nvme_submit_flush_data(nvmeq, ns);
 480                 if (result)
 481                         return result;
 482         }
 483
 484         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 485         if (!nbio)
 486                 goto nomem;
 487         nbio->bio = bio;
 488
 489         result = -EBUSY;
 490         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 491         if (unlikely(cmdid < 0))
 492                 goto free_nbio;
 493
 494         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 495                 return nvme_submit_flush(nvmeq, ns, cmdid);
 496
 497         control = 0;
 498         if (bio->bi_rw & REQ_FUA)
 499                 control |= NVME_RW_FUA;
 500         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 501                 control |= NVME_RW_LR;
 502
 503         dsmgmt = 0;
 504         if (bio->bi_rw & REQ_RAHEAD)
 505                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 506
 507         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 508
 509         memset(cmnd, 0, sizeof(*cmnd));
 510         if (bio_data_dir(bio)) {
 511                 cmnd->rw.opcode = nvme_cmd_write;
 512                 dma_dir = DMA_TO_DEVICE;
 513         } else {
 514                 cmnd->rw.opcode = nvme_cmd_read;
 515                 dma_dir = DMA_FROM_DEVICE;
 516         }
 517
 518         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 519         if (result < 0)
 520                 goto free_nbio;
 521         length = result;
 522
 523         cmnd->rw.command_id = cmdid;
 524         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 525         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 526                                                                 length);
 527         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 528         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 529         cmnd->rw.control = cpu_to_le16(control);
 530         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 531
 532         bio->bi_sector += length >> 9;
 533
 534         if (++nvmeq->sq_tail == nvmeq->q_depth)
 535                 nvmeq->sq_tail = 0;
 536         writel(nvmeq->sq_tail, nvmeq->q_db);
 537
 538         return 0;
 539
 540  free_nbio:
 541         free_nbio(nvmeq, nbio);
 542  nomem:
 543         return result;
 544 }
 545
 546 /*
 547  * NB: return value of non-zero would mean that we were a stacking driver.
 548  * make_request must always succeed.
 549  */
 550 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 551 {
 552         struct nvme_ns *ns = q->queuedata;
 553         struct nvme_queue *nvmeq = get_nvmeq(ns);
 554         int result = -EBUSY;
 555
 556         spin_lock_irq(&nvmeq->q_lock);
 557         if (bio_list_empty(&nvmeq->sq_cong))
 558                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 559         if (unlikely(result)) {
 560                 if (bio_list_empty(&nvmeq->sq_cong))
 561                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 562                 bio_list_add(&nvmeq->sq_cong, bio);
 563         }
 564
 565         spin_unlock_irq(&nvmeq->q_lock);
 566         put_nvmeq(nvmeq);
 567
 568         return 0;
 569 }
 570
 571 struct sync_cmd_info {
 572         struct task_struct *task;
 573         u32 result;
 574         int status;
 575 };
 576
 577 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 578                                                 struct nvme_completion *cqe)
 579 {
 580         struct sync_cmd_info *cmdinfo = ctx;
 581         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 582                 return;
 583         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 584                 return;
 585         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 586                 dev_warn(nvmeq->q_dmadev,
 587                                 "completed id %d twice on queue %d\n",
 588                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 589                 return;
 590         }
 591         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 592                 dev_warn(nvmeq->q_dmadev,
 593                                 "invalid id %d completed on queue %d\n",
 594                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 595                 return;
 596         }
 597         cmdinfo->result = le32_to_cpup(&cqe->result);
 598         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 599         wake_up_process(cmdinfo->task);
 600 }
 601
 602 typedef void (*completion_fn)(struct nvme_queue *, void *,
 603                                                 struct nvme_completion *);
 604
 605 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 606 {
 607         u16 head, phase;
 608
 609         static const completion_fn completions[4] = {
 610                 [sync_completion_id] = sync_completion,
 611                 [bio_completion_id]  = bio_completion,
 612         };
 613
 614         head = nvmeq->cq_head;
 615         phase = nvmeq->cq_phase;
 616
 617         for (;;) {
 618                 unsigned long data;
 619                 void *ptr;
 620                 unsigned char handler;
 621                 struct nvme_completion cqe = nvmeq->cqes[head];
 622                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 623                         break;
 624                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 625                 if (++head == nvmeq->q_depth) {
 626                         head = 0;
 627                         phase = !phase;
 628                 }
 629
 630                 data = free_cmdid(nvmeq, cqe.command_id);
 631                 handler = data & 3;
 632                 ptr = (void *)(data & ~3UL);
 633                 completions[handler](nvmeq, ptr, &cqe);
 634         }
 635
 636         /* If the controller ignores the cq head doorbell and continuously
 637          * writes to the queue, it is theoretically possible to wrap around
 638          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 639          * requires that 0.1% of your interrupts are handled, so this isn't
 640          * a big problem.
 641          */
 642         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 643                 return IRQ_NONE;
 644
 645         writel(head, nvmeq->q_db + 1);
 646         nvmeq->cq_head = head;
 647         nvmeq->cq_phase = phase;
 648
 649         return IRQ_HANDLED;
 650 }
 651
 652 static irqreturn_t nvme_irq(int irq, void *data)
 653 {
 654         irqreturn_t result;
 655         struct nvme_queue *nvmeq = data;
 656         spin_lock(&nvmeq->q_lock);
 657         result = nvme_process_cq(nvmeq);
 658         spin_unlock(&nvmeq->q_lock);
 659         return result;
 660 }
 661
 662 static irqreturn_t nvme_irq_check(int irq, void *data)
 663 {
 664         struct nvme_queue *nvmeq = data;
 665         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 666         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 667                 return IRQ_NONE;
 668         return IRQ_WAKE_THREAD;
 669 }
 670
 671 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 672 {
 673         spin_lock_irq(&nvmeq->q_lock);
 674         cancel_cmdid_data(nvmeq, cmdid);
 675         spin_unlock_irq(&nvmeq->q_lock);
 676 }
 677
 678 /*
 679  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 680  * if the result is positive, it's an NVM Express status code
 681  */
 682 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 683                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 684 {
 685         int cmdid;
 686         struct sync_cmd_info cmdinfo;
 687
 688         cmdinfo.task = current;
 689         cmdinfo.status = -EINTR;
 690
 691         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 692                                                                 timeout);
 693         if (cmdid < 0)
 694                 return cmdid;
 695         cmd->common.command_id = cmdid;
 696
 697         set_current_state(TASK_KILLABLE);
 698         nvme_submit_cmd(nvmeq, cmd);
 699         schedule();
 700
 701         if (cmdinfo.status == -EINTR) {
 702                 nvme_abort_command(nvmeq, cmdid);
 703                 return -EINTR;
 704         }
 705
 706         if (result)
 707                 *result = cmdinfo.result;
 708
 709         return cmdinfo.status;
 710 }
 711
 712 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 713                                                                 u32 *result)
 714 {
 715         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 716 }
 717
 718 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 719 {
 720         int status;
 721         struct nvme_command c;
 722
 723         memset(&c, 0, sizeof(c));
 724         c.delete_queue.opcode = opcode;
 725         c.delete_queue.qid = cpu_to_le16(id);
 726
 727         status = nvme_submit_admin_cmd(dev, &c, NULL);
 728         if (status)
 729                 return -EIO;
 730         return 0;
 731 }
 732
 733 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 734                                                 struct nvme_queue *nvmeq)
 735 {
 736         int status;
 737         struct nvme_command c;
 738         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 739
 740         memset(&c, 0, sizeof(c));
 741         c.create_cq.opcode = nvme_admin_create_cq;
 742         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 743         c.create_cq.cqid = cpu_to_le16(qid);
 744         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 745         c.create_cq.cq_flags = cpu_to_le16(flags);
 746         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 747
 748         status = nvme_submit_admin_cmd(dev, &c, NULL);
 749         if (status)
 750                 return -EIO;
 751         return 0;
 752 }
 753
 754 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 755                                                 struct nvme_queue *nvmeq)
 756 {
 757         int status;
 758         struct nvme_command c;
 759         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 760
 761         memset(&c, 0, sizeof(c));
 762         c.create_sq.opcode = nvme_admin_create_sq;
 763         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 764         c.create_sq.sqid = cpu_to_le16(qid);
 765         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 766         c.create_sq.sq_flags = cpu_to_le16(flags);
 767         c.create_sq.cqid = cpu_to_le16(qid);
 768
 769         status = nvme_submit_admin_cmd(dev, &c, NULL);
 770         if (status)
 771                 return -EIO;
 772         return 0;
 773 }
 774
 775 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 776 {
 777         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 778 }
 779
 780 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 781 {
 782         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 783 }
 784
 785 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 786 {
 787         struct nvme_queue *nvmeq = dev->queues[qid];
 788
 789         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 790
 791         /* Don't tell the adapter to delete the admin queue */
 792         if (qid) {
 793                 adapter_delete_sq(dev, qid);
 794                 adapter_delete_cq(dev, qid);
 795         }
 796
 797         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 798                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 799         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 800                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 801         kfree(nvmeq);
 802 }
 803
 804 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 805                                                         int depth, int vector)
 806 {
 807         struct device *dmadev = &dev->pci_dev->dev;
 808         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 809         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 810         if (!nvmeq)
 811                 return NULL;
 812
 813         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 814                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 815         if (!nvmeq->cqes)
 816                 goto free_nvmeq;
 817         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 818
 819         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 820                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 821         if (!nvmeq->sq_cmds)
 822                 goto free_cqdma;
 823
 824         nvmeq->q_dmadev = dmadev;
 825         nvmeq->dev = dev;
 826         spin_lock_init(&nvmeq->q_lock);
 827         nvmeq->cq_head = 0;
 828         nvmeq->cq_phase = 1;
 829         init_waitqueue_head(&nvmeq->sq_full);
 830         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 831         bio_list_init(&nvmeq->sq_cong);
 832         nvmeq->q_db = &dev->dbs[qid * 2];
 833         nvmeq->q_depth = depth;
 834         nvmeq->cq_vector = vector;
 835
 836         return nvmeq;
 837
 838  free_cqdma:
 839         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 840                                                         nvmeq->cq_dma_addr);
 841  free_nvmeq:
 842         kfree(nvmeq);
 843         return NULL;
 844 }
 845
 846 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 847                                                         const char *name)
 848 {
 849         if (use_threaded_interrupts)
 850                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 851                                         nvme_irq_check, nvme_irq,
 852                                         IRQF_DISABLED | IRQF_SHARED,
 853                                         name, nvmeq);
 854         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 855                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 856 }
 857
 858 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 859                                         int qid, int cq_size, int vector)
 860 {
 861         int result;
 862         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 863
 864         if (!nvmeq)
 865                 return NULL;
 866
 867         result = adapter_alloc_cq(dev, qid, nvmeq);
 868         if (result < 0)
 869                 goto free_nvmeq;
 870
 871         result = adapter_alloc_sq(dev, qid, nvmeq);
 872         if (result < 0)
 873                 goto release_cq;
 874
 875         result = queue_request_irq(dev, nvmeq, "nvme");
 876         if (result < 0)
 877                 goto release_sq;
 878
 879         return nvmeq;
 880
 881  release_sq:
 882         adapter_delete_sq(dev, qid);
 883  release_cq:
 884         adapter_delete_cq(dev, qid);
 885  free_nvmeq:
 886         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 887                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 888         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 889                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 890         kfree(nvmeq);
 891         return NULL;
 892 }
 893
 894 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 895 {
 896         int result;
 897         u32 aqa;
 898         struct nvme_queue *nvmeq;
 899
 900         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 901
 902         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 903         if (!nvmeq)
 904                 return -ENOMEM;
 905
 906         aqa = nvmeq->q_depth - 1;
 907         aqa |= aqa << 16;
 908
 909         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 910         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 911         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 912
 913         writel(0, &dev->bar->cc);
 914         writel(aqa, &dev->bar->aqa);
 915         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 916         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 917         writel(dev->ctrl_config, &dev->bar->cc);
 918
 919         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 920                 msleep(100);
 921                 if (fatal_signal_pending(current))
 922                         return -EINTR;
 923         }
 924
 925         result = queue_request_irq(dev, nvmeq, "nvme admin");
 926         dev->queues[0] = nvmeq;
 927         return result;
 928 }
 929
 930 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 931                                 unsigned long addr, unsigned length,
 932                                 struct scatterlist **sgp)
 933 {
 934         int i, err, count, nents, offset;
 935         struct scatterlist *sg;
 936         struct page **pages;
 937
 938         if (addr & 3)
 939                 return -EINVAL;
 940         if (!length)
 941                 return -EINVAL;
 942
 943         offset = offset_in_page(addr);
 944         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 945         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 946
 947         err = get_user_pages_fast(addr, count, 1, pages);
 948         if (err < count) {
 949                 count = err;
 950                 err = -EFAULT;
 951                 goto put_pages;
 952         }
 953
 954         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 955         sg_init_table(sg, count);
 956         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 957         length -= (PAGE_SIZE - offset);
 958         for (i = 1; i < count; i++) {
 959                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 960                 length -= PAGE_SIZE;
 961         }
 962
 963         err = -ENOMEM;
 964         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 965                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 966         if (!nents)
 967                 goto put_pages;
 968
 969         kfree(pages);
 970         *sgp = sg;
 971         return nents;
 972
 973  put_pages:
 974         for (i = 0; i < count; i++)
 975                 put_page(pages[i]);
 976         kfree(pages);
 977         return err;
 978 }
 979
 980 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 981                                 unsigned long addr, int length,
 982                                 struct scatterlist *sg, int nents)
 983 {
 984         int i, count;
 985
 986         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 987         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 988
 989         for (i = 0; i < count; i++)
 990                 put_page(sg_page(&sg[i]));
 991 }
 992
 993 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 994                                         unsigned long addr, unsigned length,
 995                                         struct nvme_command *cmd)
 996 {
 997         int err, nents;
 998         struct scatterlist *sg;
 999         struct nvme_prps *prps;
1000
1001         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1002         if (nents < 0)
1003                 return nents;
1004         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1005         err = nvme_submit_admin_cmd(dev, cmd, NULL);
1006         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1007         nvme_free_prps(dev, prps);
1008         return err ? -EIO : 0;
1009 }
1010
1011 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1012 {
1013         struct nvme_command c;
1014
1015         memset(&c, 0, sizeof(c));
1016         c.identify.opcode = nvme_admin_identify;
1017         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1018         c.identify.cns = cpu_to_le32(cns);
1019
1020         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1021 }
1022
1023 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1024 {
1025         struct nvme_command c;
1026
1027         memset(&c, 0, sizeof(c));
1028         c.features.opcode = nvme_admin_get_features;
1029         c.features.nsid = cpu_to_le32(ns->ns_id);
1030         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1031
1032         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1033 }
1034
1035 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1036 {
1037         struct nvme_dev *dev = ns->dev;
1038         struct nvme_queue *nvmeq;
1039         struct nvme_user_io io;
1040         struct nvme_command c;
1041         unsigned length;
1042         u32 result;
1043         int nents, status;
1044         struct scatterlist *sg;
1045         struct nvme_prps *prps;
1046
1047         if (copy_from_user(&io, uio, sizeof(io)))
1048                 return -EFAULT;
1049         length = io.nblocks << io.block_shift;
1050         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
1051         if (nents < 0)
1052                 return nents;
1053
1054         memset(&c, 0, sizeof(c));
1055         c.rw.opcode = io.opcode;
1056         c.rw.flags = io.flags;
1057         c.rw.nsid = cpu_to_le32(io.nsid);
1058         c.rw.slba = cpu_to_le64(io.slba);
1059         c.rw.length = cpu_to_le16(io.nblocks - 1);
1060         c.rw.control = cpu_to_le16(io.control);
1061         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1062         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1063         c.rw.apptag = cpu_to_le16(io.apptag);
1064         c.rw.appmask = cpu_to_le16(io.appmask);
1065         /* XXX: metadata */
1066         prps = nvme_setup_prps(dev, &c.common, sg, length);
1067
1068         nvmeq = get_nvmeq(ns);
1069         /*
1070          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1071          * disabled.  We may be preempted at any point, and be rescheduled
1072          * to a different CPU.  That will cause cacheline bouncing, but no
1073          * additional races since q_lock already protects against other CPUs.
1074          */
1075         put_nvmeq(nvmeq);
1076         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1077
1078         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1079         nvme_free_prps(dev, prps);
1080         put_user(result, &uio->result);
1081         return status;
1082 }
1083
1084 static int nvme_download_firmware(struct nvme_ns *ns,
1085                                                 struct nvme_dlfw __user *udlfw)
1086 {
1087         struct nvme_dev *dev = ns->dev;
1088         struct nvme_dlfw dlfw;
1089         struct nvme_command c;
1090         int nents, status;
1091         struct scatterlist *sg;
1092         struct nvme_prps *prps;
1093
1094         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1095                 return -EFAULT;
1096         if (dlfw.length >= (1 << 30))
1097                 return -EINVAL;
1098
1099         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1100         if (nents < 0)
1101                 return nents;
1102
1103         memset(&c, 0, sizeof(c));
1104         c.dlfw.opcode = nvme_admin_download_fw;
1105         c.dlfw.numd = cpu_to_le32(dlfw.length);
1106         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1107         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1108
1109         status = nvme_submit_admin_cmd(dev, &c, NULL);
1110         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1111         nvme_free_prps(dev, prps);
1112         return status;
1113 }
1114
1115 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1116 {
1117         struct nvme_dev *dev = ns->dev;
1118         struct nvme_command c;
1119
1120         memset(&c, 0, sizeof(c));
1121         c.common.opcode = nvme_admin_activate_fw;
1122         c.common.rsvd10[0] = cpu_to_le32(arg);
1123
1124         return nvme_submit_admin_cmd(dev, &c, NULL);
1125 }
1126
1127 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1128                                                         unsigned long arg)
1129 {
1130         struct nvme_ns *ns = bdev->bd_disk->private_data;
1131
1132         switch (cmd) {
1133         case NVME_IOCTL_IDENTIFY_NS:
1134                 return nvme_identify(ns, arg, 0);
1135         case NVME_IOCTL_IDENTIFY_CTRL:
1136                 return nvme_identify(ns, arg, 1);
1137         case NVME_IOCTL_GET_RANGE_TYPE:
1138                 return nvme_get_range_type(ns, arg);
1139         case NVME_IOCTL_SUBMIT_IO:
1140                 return nvme_submit_io(ns, (void __user *)arg);
1141         case NVME_IOCTL_DOWNLOAD_FW:
1142                 return nvme_download_firmware(ns, (void __user *)arg);
1143         case NVME_IOCTL_ACTIVATE_FW:
1144                 return nvme_activate_firmware(ns, arg);
1145         default:
1146                 return -ENOTTY;
1147         }
1148 }
1149
1150 static const struct block_device_operations nvme_fops = {
1151         .owner          = THIS_MODULE,
1152         .ioctl          = nvme_ioctl,
1153 };
1154
1155 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1156 {
1157         while (bio_list_peek(&nvmeq->sq_cong)) {
1158                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1159                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1160                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1161                         bio_list_add_head(&nvmeq->sq_cong, bio);
1162                         break;
1163                 }
1164         }
1165 }
1166
1167 static int nvme_kthread(void *data)
1168 {
1169         struct nvme_dev *dev;
1170
1171         while (!kthread_should_stop()) {
1172                 __set_current_state(TASK_RUNNING);
1173                 spin_lock(&dev_list_lock);
1174                 list_for_each_entry(dev, &dev_list, node) {
1175                         int i;
1176                         for (i = 0; i < dev->queue_count; i++) {
1177                                 struct nvme_queue *nvmeq = dev->queues[i];
1178                                 if (!nvmeq)
1179                                         continue;
1180                                 spin_lock_irq(&nvmeq->q_lock);
1181                                 if (nvme_process_cq(nvmeq))
1182                                         printk("process_cq did something\n");
1183                                 nvme_resubmit_bios(nvmeq);
1184                                 spin_unlock_irq(&nvmeq->q_lock);
1185                         }
1186                 }
1187                 spin_unlock(&dev_list_lock);
1188                 set_current_state(TASK_INTERRUPTIBLE);
1189                 schedule_timeout(HZ);
1190         }
1191         return 0;
1192 }
1193
1194 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1195                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1196 {
1197         struct nvme_ns *ns;
1198         struct gendisk *disk;
1199         int lbaf;
1200
1201         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1202                 return NULL;
1203
1204         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1205         if (!ns)
1206                 return NULL;
1207         ns->queue = blk_alloc_queue(GFP_KERNEL);
1208         if (!ns->queue)
1209                 goto out_free_ns;
1210         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1211                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1212         blk_queue_make_request(ns->queue, nvme_make_request);
1213         ns->dev = dev;
1214         ns->queue->queuedata = ns;
1215
1216         disk = alloc_disk(NVME_MINORS);
1217         if (!disk)
1218                 goto out_free_queue;
1219         ns->ns_id = index;
1220         ns->disk = disk;
1221         lbaf = id->flbas & 0xf;
1222         ns->lba_shift = id->lbaf[lbaf].ds;
1223
1224         disk->major = nvme_major;
1225         disk->minors = NVME_MINORS;
1226         disk->first_minor = NVME_MINORS * index;
1227         disk->fops = &nvme_fops;
1228         disk->private_data = ns;
1229         disk->queue = ns->queue;
1230         disk->driverfs_dev = &dev->pci_dev->dev;
1231         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1232         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1233
1234         return ns;
1235
1236  out_free_queue:
1237         blk_cleanup_queue(ns->queue);
1238  out_free_ns:
1239         kfree(ns);
1240         return NULL;
1241 }
1242
1243 static void nvme_ns_free(struct nvme_ns *ns)
1244 {
1245         put_disk(ns->disk);
1246         blk_cleanup_queue(ns->queue);
1247         kfree(ns);
1248 }
1249
1250 static int set_queue_count(struct nvme_dev *dev, int count)
1251 {
1252         int status;
1253         u32 result;
1254         struct nvme_command c;
1255         u32 q_count = (count - 1) | ((count - 1) << 16);
1256
1257         memset(&c, 0, sizeof(c));
1258         c.features.opcode = nvme_admin_get_features;
1259         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1260         c.features.dword11 = cpu_to_le32(q_count);
1261
1262         status = nvme_submit_admin_cmd(dev, &c, &result);
1263         if (status)
1264                 return -EIO;
1265         return min(result & 0xffff, result >> 16) + 1;
1266 }
1267
1268 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1269 {
1270         int result, cpu, i, nr_io_queues;
1271
1272         nr_io_queues = num_online_cpus();
1273         result = set_queue_count(dev, nr_io_queues);
1274         if (result < 0)
1275                 return result;
1276         if (result < nr_io_queues)
1277                 nr_io_queues = result;
1278
1279         /* Deregister the admin queue's interrupt */
1280         free_irq(dev->entry[0].vector, dev->queues[0]);
1281
1282         for (i = 0; i < nr_io_queues; i++)
1283                 dev->entry[i].entry = i;
1284         for (;;) {
1285                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1286                                                                 nr_io_queues);
1287                 if (result == 0) {
1288                         break;
1289                 } else if (result > 0) {
1290                         nr_io_queues = result;
1291                         continue;
1292                 } else {
1293                         nr_io_queues = 1;
1294                         break;
1295                 }
1296         }
1297
1298         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1299         /* XXX: handle failure here */
1300
1301         cpu = cpumask_first(cpu_online_mask);
1302         for (i = 0; i < nr_io_queues; i++) {
1303                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1304                 cpu = cpumask_next(cpu, cpu_online_mask);
1305         }
1306
1307         for (i = 0; i < nr_io_queues; i++) {
1308                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1309                                                         NVME_Q_DEPTH, i);
1310                 if (!dev->queues[i + 1])
1311                         return -ENOMEM;
1312                 dev->queue_count++;
1313         }
1314
1315         return 0;
1316 }
1317
1318 static void nvme_free_queues(struct nvme_dev *dev)
1319 {
1320         int i;
1321
1322         for (i = dev->queue_count - 1; i >= 0; i--)
1323                 nvme_free_queue(dev, i);
1324 }
1325
1326 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1327 {
1328         int res, nn, i;
1329         struct nvme_ns *ns, *next;
1330         struct nvme_id_ctrl *ctrl;
1331         void *id;
1332         dma_addr_t dma_addr;
1333         struct nvme_command cid, crt;
1334
1335         res = nvme_setup_io_queues(dev);
1336         if (res)
1337                 return res;
1338
1339         /* XXX: Switch to a SG list once prp2 works */
1340         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1341                                                                 GFP_KERNEL);
1342
1343         memset(&cid, 0, sizeof(cid));
1344         cid.identify.opcode = nvme_admin_identify;
1345         cid.identify.nsid = 0;
1346         cid.identify.prp1 = cpu_to_le64(dma_addr);
1347         cid.identify.cns = cpu_to_le32(1);
1348
1349         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1350         if (res) {
1351                 res = -EIO;
1352                 goto out_free;
1353         }
1354
1355         ctrl = id;
1356         nn = le32_to_cpup(&ctrl->nn);
1357         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1358         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1359         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1360
1361         cid.identify.cns = 0;
1362         memset(&crt, 0, sizeof(crt));
1363         crt.features.opcode = nvme_admin_get_features;
1364         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1365         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1366
1367         for (i = 0; i <= nn; i++) {
1368                 cid.identify.nsid = cpu_to_le32(i);
1369                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1370                 if (res)
1371                         continue;
1372
1373                 if (((struct nvme_id_ns *)id)->ncap == 0)
1374                         continue;
1375
1376                 crt.features.nsid = cpu_to_le32(i);
1377                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1378                 if (res)
1379                         continue;
1380
1381                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1382                 if (ns)
1383                         list_add_tail(&ns->list, &dev->namespaces);
1384         }
1385         list_for_each_entry(ns, &dev->namespaces, list)
1386                 add_disk(ns->disk);
1387
1388         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1389         return 0;
1390
1391  out_free:
1392         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1393                 list_del(&ns->list);
1394                 nvme_ns_free(ns);
1395         }
1396
1397         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1398         return res;
1399 }
1400
1401 static int nvme_dev_remove(struct nvme_dev *dev)
1402 {
1403         struct nvme_ns *ns, *next;
1404
1405         spin_lock(&dev_list_lock);
1406         list_del(&dev->node);
1407         spin_unlock(&dev_list_lock);
1408
1409         /* TODO: wait all I/O finished or cancel them */
1410
1411         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1412                 list_del(&ns->list);
1413                 del_gendisk(ns->disk);
1414                 nvme_ns_free(ns);
1415         }
1416
1417         nvme_free_queues(dev);
1418
1419         return 0;
1420 }
1421
1422 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1423 {
1424         struct device *dmadev = &dev->pci_dev->dev;
1425         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1426                                                 PAGE_SIZE, PAGE_SIZE, 0);
1427         if (!dev->prp_page_pool)
1428                 return -ENOMEM;
1429
1430         /* Optimisation for I/Os between 4k and 128k */
1431         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1432                                                 256, 256, 0);
1433         if (!dev->prp_small_pool) {
1434                 dma_pool_destroy(dev->prp_page_pool);
1435                 return -ENOMEM;
1436         }
1437         return 0;
1438 }
1439
1440 static void nvme_release_prp_pools(struct nvme_dev *dev)
1441 {
1442         dma_pool_destroy(dev->prp_page_pool);
1443         dma_pool_destroy(dev->prp_small_pool);
1444 }
1445
1446 /* XXX: Use an ida or something to let remove / add work correctly */
1447 static void nvme_set_instance(struct nvme_dev *dev)
1448 {
1449         static int instance;
1450         dev->instance = instance++;
1451 }
1452
1453 static void nvme_release_instance(struct nvme_dev *dev)
1454 {
1455 }
1456
1457 static int __devinit nvme_probe(struct pci_dev *pdev,
1458                                                 const struct pci_device_id *id)
1459 {
1460         int bars, result = -ENOMEM;
1461         struct nvme_dev *dev;
1462
1463         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1464         if (!dev)
1465                 return -ENOMEM;
1466         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1467                                                                 GFP_KERNEL);
1468         if (!dev->entry)
1469                 goto free;
1470         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1471                                                                 GFP_KERNEL);
1472         if (!dev->queues)
1473                 goto free;
1474
1475         if (pci_enable_device_mem(pdev))
1476                 goto free;
1477         pci_set_master(pdev);
1478         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1479         if (pci_request_selected_regions(pdev, bars, "nvme"))
1480                 goto disable;
1481
1482         INIT_LIST_HEAD(&dev->namespaces);
1483         dev->pci_dev = pdev;
1484         pci_set_drvdata(pdev, dev);
1485         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1486         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1487         nvme_set_instance(dev);
1488         dev->entry[0].vector = pdev->irq;
1489
1490         result = nvme_setup_prp_pools(dev);
1491         if (result)
1492                 goto disable_msix;
1493
1494         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1495         if (!dev->bar) {
1496                 result = -ENOMEM;
1497                 goto disable_msix;
1498         }
1499
1500         result = nvme_configure_admin_queue(dev);
1501         if (result)
1502                 goto unmap;
1503         dev->queue_count++;
1504
1505         spin_lock(&dev_list_lock);
1506         list_add(&dev->node, &dev_list);
1507         spin_unlock(&dev_list_lock);
1508
1509         result = nvme_dev_add(dev);
1510         if (result)
1511                 goto delete;
1512
1513         return 0;
1514
1515  delete:
1516         spin_lock(&dev_list_lock);
1517         list_del(&dev->node);
1518         spin_unlock(&dev_list_lock);
1519
1520         nvme_free_queues(dev);
1521  unmap:
1522         iounmap(dev->bar);
1523  disable_msix:
1524         pci_disable_msix(pdev);
1525         nvme_release_instance(dev);
1526         nvme_release_prp_pools(dev);
1527  disable:
1528         pci_disable_device(pdev);
1529         pci_release_regions(pdev);
1530  free:
1531         kfree(dev->queues);
1532         kfree(dev->entry);
1533         kfree(dev);
1534         return result;
1535 }
1536
1537 static void __devexit nvme_remove(struct pci_dev *pdev)
1538 {
1539         struct nvme_dev *dev = pci_get_drvdata(pdev);
1540         nvme_dev_remove(dev);
1541         pci_disable_msix(pdev);
1542         iounmap(dev->bar);
1543         nvme_release_instance(dev);
1544         nvme_release_prp_pools(dev);
1545         pci_disable_device(pdev);
1546         pci_release_regions(pdev);
1547         kfree(dev->queues);
1548         kfree(dev->entry);
1549         kfree(dev);
1550 }
1551
1552 /* These functions are yet to be implemented */
1553 #define nvme_error_detected NULL
1554 #define nvme_dump_registers NULL
1555 #define nvme_link_reset NULL
1556 #define nvme_slot_reset NULL
1557 #define nvme_error_resume NULL
1558 #define nvme_suspend NULL
1559 #define nvme_resume NULL
1560
1561 static struct pci_error_handlers nvme_err_handler = {
1562         .error_detected = nvme_error_detected,
1563         .mmio_enabled   = nvme_dump_registers,
1564         .link_reset     = nvme_link_reset,
1565         .slot_reset     = nvme_slot_reset,
1566         .resume         = nvme_error_resume,
1567 };
1568
1569 /* Move to pci_ids.h later */
1570 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1571
1572 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1573         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1574         { 0, }
1575 };
1576 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1577
1578 static struct pci_driver nvme_driver = {
1579         .name           = "nvme",
1580         .id_table       = nvme_id_table,
1581         .probe          = nvme_probe,
1582         .remove         = __devexit_p(nvme_remove),
1583         .suspend        = nvme_suspend,
1584         .resume         = nvme_resume,
1585         .err_handler    = &nvme_err_handler,
1586 };
1587
1588 static int __init nvme_init(void)
1589 {
1590         int result = -EBUSY;
1591
1592         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1593         if (IS_ERR(nvme_thread))
1594                 return PTR_ERR(nvme_thread);
1595
1596         nvme_major = register_blkdev(nvme_major, "nvme");
1597         if (nvme_major <= 0)
1598                 goto kill_kthread;
1599
1600         result = pci_register_driver(&nvme_driver);
1601         if (result)
1602                 goto unregister_blkdev;
1603         return 0;
1604
1605  unregister_blkdev:
1606         unregister_blkdev(nvme_major, "nvme");
1607  kill_kthread:
1608         kthread_stop(nvme_thread);
1609         return result;
1610 }
1611
1612 static void __exit nvme_exit(void)
1613 {
1614         pci_unregister_driver(&nvme_driver);
1615         unregister_blkdev(nvme_major, "nvme");
1616         kthread_stop(nvme_thread);
1617 }
1618
1619 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1620 MODULE_LICENSE("GPL");
1621 MODULE_VERSION("0.4");
1622 module_init(nvme_init);
1623 module_exit(nvme_exit);