drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kernel.h>
  30 #include <linux/mm.h>
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/poison.h>
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/types.h>
  38 #include <linux/version.h>
  39
  40 #define NVME_Q_DEPTH 1024
  41 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  42 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  43 #define NVME_MINORS 64
  44 #define IO_TIMEOUT      (5 * HZ)
  45 #define ADMIN_TIMEOUT   (60 * HZ)
  46
  47 static int nvme_major;
  48 module_param(nvme_major, int, 0);
  49
  50 static int use_threaded_interrupts;
  51 module_param(use_threaded_interrupts, int, 0);
  52
  53 /*
  54  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  55  */
  56 struct nvme_dev {
  57         struct nvme_queue **queues;
  58         u32 __iomem *dbs;
  59         struct pci_dev *pci_dev;
  60         struct dma_pool *prp_page_pool;
  61         struct dma_pool *prp_small_pool;
  62         int instance;
  63         int queue_count;
  64         u32 ctrl_config;
  65         struct msix_entry *entry;
  66         struct nvme_bar __iomem *bar;
  67         struct list_head namespaces;
  68         char serial[20];
  69         char model[40];
  70         char firmware_rev[8];
  71 };
  72
  73 /*
  74  * An NVM Express namespace is equivalent to a SCSI LUN
  75  */
  76 struct nvme_ns {
  77         struct list_head list;
  78
  79         struct nvme_dev *dev;
  80         struct request_queue *queue;
  81         struct gendisk *disk;
  82
  83         int ns_id;
  84         int lba_shift;
  85 };
  86
  87 /*
  88  * An NVM Express queue.  Each device has at least two (one for admin
  89  * commands and one for I/O commands).
  90  */
  91 struct nvme_queue {
  92         struct device *q_dmadev;
  93         struct nvme_dev *dev;
  94         spinlock_t q_lock;
  95         struct nvme_command *sq_cmds;
  96         volatile struct nvme_completion *cqes;
  97         dma_addr_t sq_dma_addr;
  98         dma_addr_t cq_dma_addr;
  99         wait_queue_head_t sq_full;
 100         struct bio_list sq_cong;
 101         u32 __iomem *q_db;
 102         u16 q_depth;
 103         u16 cq_vector;
 104         u16 sq_head;
 105         u16 sq_tail;
 106         u16 cq_head;
 107         u16 cq_phase;
 108         unsigned long cmdid_data[];
 109 };
 110
 111 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio);
 112
 113 /*
 114  * Check we didin't inadvertently grow the command struct
 115  */
 116 static inline void _nvme_check_size(void)
 117 {
 118         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 119         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 120         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 121         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 122         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 123         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 125         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 126         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 127 }
 128
 129 struct nvme_cmd_info {
 130         unsigned long ctx;
 131         unsigned long timeout;
 132 };
 133
 134 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 135 {
 136         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 137 }
 138
 139 /**
 140  * alloc_cmdid - Allocate a Command ID
 141  * @param nvmeq The queue that will be used for this command
 142  * @param ctx A pointer that will be passed to the handler
 143  * @param handler The ID of the handler to call
 144  *
 145  * Allocate a Command ID for a queue.  The data passed in will
 146  * be passed to the completion handler.  This is implemented by using
 147  * the bottom two bits of the ctx pointer to store the handler ID.
 148  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 149  * We can change this if it becomes a problem.
 150  */
 151 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 152                                                         unsigned timeout)
 153 {
 154         int depth = nvmeq->q_depth;
 155         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 156         int cmdid;
 157
 158         BUG_ON((unsigned long)ctx & 3);
 159
 160         do {
 161                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 162                 if (cmdid >= depth)
 163                         return -EBUSY;
 164         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 165
 166         info[cmdid].ctx = (unsigned long)ctx | handler;
 167         info[cmdid].timeout = jiffies + timeout;
 168         return cmdid;
 169 }
 170
 171 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 172                                                 int handler, unsigned timeout)
 173 {
 174         int cmdid;
 175         wait_event_killable(nvmeq->sq_full,
 176                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 177         return (cmdid < 0) ? -EINTR : cmdid;
 178 }
 179
 180 /* If you need more than four handlers, you'll need to change how
 181  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 182  * CMD_CTX value instead, if that works for your situation.
 183  */
 184 enum {
 185         sync_completion_id = 0,
 186         bio_completion_id,
 187 };
 188
 189 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 190 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 191 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 192 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 193
 194 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 195 {
 196         unsigned long data;
 197         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 198
 199         if (cmdid >= nvmeq->q_depth)
 200                 return CMD_CTX_INVALID;
 201         data = info[cmdid].ctx;
 202         info[cmdid].ctx = CMD_CTX_COMPLETED;
 203         clear_bit(cmdid, nvmeq->cmdid_data);
 204         wake_up(&nvmeq->sq_full);
 205         return data;
 206 }
 207
 208 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 209 {
 210         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 211         info[cmdid].ctx = CMD_CTX_CANCELLED;
 212 }
 213
 214 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 215 {
 216         int qid, cpu = get_cpu();
 217         if (cpu < ns->dev->queue_count)
 218                 qid = cpu + 1;
 219         else
 220                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 221         return ns->dev->queues[qid];
 222 }
 223
 224 static void put_nvmeq(struct nvme_queue *nvmeq)
 225 {
 226         put_cpu();
 227 }
 228
 229 /**
 230  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 231  * @nvmeq: The queue to use
 232  * @cmd: The command to send
 233  *
 234  * Safe to use from interrupt context
 235  */
 236 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 237 {
 238         unsigned long flags;
 239         u16 tail;
 240         /* XXX: Need to check tail isn't going to overrun head */
 241         spin_lock_irqsave(&nvmeq->q_lock, flags);
 242         tail = nvmeq->sq_tail;
 243         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 244         writel(tail, nvmeq->q_db);
 245         if (++tail == nvmeq->q_depth)
 246                 tail = 0;
 247         nvmeq->sq_tail = tail;
 248         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 249
 250         return 0;
 251 }
 252
 253 struct nvme_prps {
 254         int npages;
 255         dma_addr_t first_dma;
 256         __le64 *list[0];
 257 };
 258
 259 static void nvme_free_prps(struct nvme_queue *nvmeq, struct nvme_prps *prps)
 260 {
 261         const int last_prp = PAGE_SIZE / 8 - 1;
 262         struct nvme_dev *dev = nvmeq->dev;
 263         int i;
 264         dma_addr_t prp_dma;
 265
 266         if (!prps)
 267                 return;
 268
 269         prp_dma = prps->first_dma;
 270
 271         if (prps->npages == 0)
 272                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 273         for (i = 0; i < prps->npages; i++) {
 274                 __le64 *prp_list = prps->list[i];
 275                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 276                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 277                 prp_dma = next_prp_dma;
 278         }
 279         kfree(prps);
 280 }
 281
 282 struct nvme_bio {
 283         struct bio *bio;
 284         int nents;
 285         struct nvme_prps *prps;
 286         struct scatterlist sg[0];
 287 };
 288
 289 /* XXX: use a mempool */
 290 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 291 {
 292         return kzalloc(sizeof(struct nvme_bio) +
 293                         sizeof(struct scatterlist) * nseg, gfp);
 294 }
 295
 296 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 297 {
 298         nvme_free_prps(nvmeq, nbio->prps);
 299         kfree(nbio);
 300 }
 301
 302 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 303                                                 struct nvme_completion *cqe)
 304 {
 305         struct nvme_bio *nbio = ctx;
 306         struct bio *bio = nbio->bio;
 307         u16 status = le16_to_cpup(&cqe->status) >> 1;
 308
 309         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 310                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 311         free_nbio(nvmeq, nbio);
 312         bio_endio(bio, status ? -EIO : 0);
 313         bio = bio_list_pop(&nvmeq->sq_cong);
 314         if (bio)
 315                 nvme_resubmit_bio(nvmeq, bio);
 316 }
 317
 318 /* length is in bytes */
 319 static struct nvme_prps *nvme_setup_prps(struct nvme_queue *nvmeq,
 320                                         struct nvme_common_command *cmd,
 321                                         struct scatterlist *sg, int length)
 322 {
 323         struct nvme_dev *dev = nvmeq->dev;
 324         struct dma_pool *pool;
 325         int dma_len = sg_dma_len(sg);
 326         u64 dma_addr = sg_dma_address(sg);
 327         int offset = offset_in_page(dma_addr);
 328         __le64 *prp_list;
 329         dma_addr_t prp_dma;
 330         int nprps, npages, i, prp_page;
 331         struct nvme_prps *prps = NULL;
 332
 333         cmd->prp1 = cpu_to_le64(dma_addr);
 334         length -= (PAGE_SIZE - offset);
 335         if (length <= 0)
 336                 return prps;
 337
 338         dma_len -= (PAGE_SIZE - offset);
 339         if (dma_len) {
 340                 dma_addr += (PAGE_SIZE - offset);
 341         } else {
 342                 sg = sg_next(sg);
 343                 dma_addr = sg_dma_address(sg);
 344                 dma_len = sg_dma_len(sg);
 345         }
 346
 347         if (length <= PAGE_SIZE) {
 348                 cmd->prp2 = cpu_to_le64(dma_addr);
 349                 return prps;
 350         }
 351
 352         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 353         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 354         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 355         prp_page = 0;
 356         if (nprps <= (256 / 8)) {
 357                 pool = dev->prp_small_pool;
 358                 prps->npages = 0;
 359         } else {
 360                 pool = dev->prp_page_pool;
 361                 prps->npages = npages;
 362         }
 363
 364         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 365         prps->list[prp_page++] = prp_list;
 366         prps->first_dma = prp_dma;
 367         cmd->prp2 = cpu_to_le64(prp_dma);
 368         i = 0;
 369         for (;;) {
 370                 if (i == PAGE_SIZE / 8 - 1) {
 371                         __le64 *old_prp_list = prp_list;
 372                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 373                         prps->list[prp_page++] = prp_list;
 374                         old_prp_list[i] = cpu_to_le64(prp_dma);
 375                         i = 0;
 376                 }
 377                 prp_list[i++] = cpu_to_le64(dma_addr);
 378                 dma_len -= PAGE_SIZE;
 379                 dma_addr += PAGE_SIZE;
 380                 length -= PAGE_SIZE;
 381                 if (length <= 0)
 382                         break;
 383                 if (dma_len > 0)
 384                         continue;
 385                 BUG_ON(dma_len < 0);
 386                 sg = sg_next(sg);
 387                 dma_addr = sg_dma_address(sg);
 388                 dma_len = sg_dma_len(sg);
 389         }
 390
 391         return prps;
 392 }
 393
 394 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 395                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 396 {
 397         struct bio_vec *bvec;
 398         struct scatterlist *sg = nbio->sg;
 399         int i, nsegs;
 400
 401         sg_init_table(sg, psegs);
 402         bio_for_each_segment(bvec, bio, i) {
 403                 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
 404                 sg++;
 405                 /* XXX: handle non-mergable here */
 406                 nsegs++;
 407         }
 408         nbio->nents = nsegs;
 409
 410         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 411 }
 412
 413 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 414                                                                 struct bio *bio)
 415 {
 416         struct nvme_command *cmnd;
 417         struct nvme_bio *nbio;
 418         enum dma_data_direction dma_dir;
 419         int cmdid;
 420         u16 control;
 421         u32 dsmgmt;
 422         unsigned long flags;
 423         int psegs = bio_phys_segments(ns->queue, bio);
 424
 425         nbio = alloc_nbio(psegs, GFP_NOIO);
 426         if (!nbio)
 427                 goto congestion;
 428         nbio->bio = bio;
 429
 430         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 431         if (unlikely(cmdid < 0))
 432                 goto free_nbio;
 433
 434         control = 0;
 435         if (bio->bi_rw & REQ_FUA)
 436                 control |= NVME_RW_FUA;
 437         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 438                 control |= NVME_RW_LR;
 439
 440         dsmgmt = 0;
 441         if (bio->bi_rw & REQ_RAHEAD)
 442                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 443
 444         spin_lock_irqsave(&nvmeq->q_lock, flags);
 445         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 446
 447         memset(cmnd, 0, sizeof(*cmnd));
 448         if (bio_data_dir(bio)) {
 449                 cmnd->rw.opcode = nvme_cmd_write;
 450                 dma_dir = DMA_TO_DEVICE;
 451         } else {
 452                 cmnd->rw.opcode = nvme_cmd_read;
 453                 dma_dir = DMA_FROM_DEVICE;
 454         }
 455
 456         nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 457
 458         cmnd->rw.flags = 1;
 459         cmnd->rw.command_id = cmdid;
 460         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 461         nbio->prps = nvme_setup_prps(nvmeq, &cmnd->common, nbio->sg,
 462                                                                 bio->bi_size);
 463         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 464         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 465         cmnd->rw.control = cpu_to_le16(control);
 466         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 467
 468         writel(nvmeq->sq_tail, nvmeq->q_db);
 469         if (++nvmeq->sq_tail == nvmeq->q_depth)
 470                 nvmeq->sq_tail = 0;
 471
 472         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 473
 474         return 0;
 475
 476  free_nbio:
 477         free_nbio(nvmeq, nbio);
 478  congestion:
 479         return -EBUSY;
 480 }
 481
 482 static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio)
 483 {
 484         struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
 485         if (nvme_submit_bio_queue(nvmeq, ns, bio))
 486                 bio_list_add_head(&nvmeq->sq_cong, bio);
 487         else if (bio_list_empty(&nvmeq->sq_cong))
 488                 blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw));
 489         /* XXX: Need to duplicate the logic from __freed_request here */
 490 }
 491
 492 /*
 493  * NB: return value of non-zero would mean that we were a stacking driver.
 494  * make_request must always succeed.
 495  */
 496 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 497 {
 498         struct nvme_ns *ns = q->queuedata;
 499         struct nvme_queue *nvmeq = get_nvmeq(ns);
 500
 501         if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
 502                 blk_set_queue_congested(q, rw_is_sync(bio->bi_rw));
 503                 spin_lock_irq(&nvmeq->q_lock);
 504                 bio_list_add(&nvmeq->sq_cong, bio);
 505                 spin_unlock_irq(&nvmeq->q_lock);
 506         }
 507         put_nvmeq(nvmeq);
 508
 509         return 0;
 510 }
 511
 512 struct sync_cmd_info {
 513         struct task_struct *task;
 514         u32 result;
 515         int status;
 516 };
 517
 518 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 519                                                 struct nvme_completion *cqe)
 520 {
 521         struct sync_cmd_info *cmdinfo = ctx;
 522         if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED)
 523                 return;
 524         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 525                 dev_warn(nvmeq->q_dmadev,
 526                                 "completed id %d twice on queue %d\n",
 527                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 528                 return;
 529         }
 530         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 531                 dev_warn(nvmeq->q_dmadev,
 532                                 "invalid id %d completed on queue %d\n",
 533                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 534                 return;
 535         }
 536         cmdinfo->result = le32_to_cpup(&cqe->result);
 537         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 538         wake_up_process(cmdinfo->task);
 539 }
 540
 541 typedef void (*completion_fn)(struct nvme_queue *, void *,
 542                                                 struct nvme_completion *);
 543
 544 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 545 {
 546         u16 head, phase;
 547
 548         static const completion_fn completions[4] = {
 549                 [sync_completion_id] = sync_completion,
 550                 [bio_completion_id]  = bio_completion,
 551         };
 552
 553         head = nvmeq->cq_head;
 554         phase = nvmeq->cq_phase;
 555
 556         for (;;) {
 557                 unsigned long data;
 558                 void *ptr;
 559                 unsigned char handler;
 560                 struct nvme_completion cqe = nvmeq->cqes[head];
 561                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 562                         break;
 563                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 564                 if (++head == nvmeq->q_depth) {
 565                         head = 0;
 566                         phase = !phase;
 567                 }
 568
 569                 data = free_cmdid(nvmeq, cqe.command_id);
 570                 handler = data & 3;
 571                 ptr = (void *)(data & ~3UL);
 572                 completions[handler](nvmeq, ptr, &cqe);
 573         }
 574
 575         /* If the controller ignores the cq head doorbell and continuously
 576          * writes to the queue, it is theoretically possible to wrap around
 577          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 578          * requires that 0.1% of your interrupts are handled, so this isn't
 579          * a big problem.
 580          */
 581         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 582                 return IRQ_NONE;
 583
 584         writel(head, nvmeq->q_db + 1);
 585         nvmeq->cq_head = head;
 586         nvmeq->cq_phase = phase;
 587
 588         return IRQ_HANDLED;
 589 }
 590
 591 static irqreturn_t nvme_irq(int irq, void *data)
 592 {
 593         irqreturn_t result;
 594         struct nvme_queue *nvmeq = data;
 595         spin_lock(&nvmeq->q_lock);
 596         result = nvme_process_cq(nvmeq);
 597         spin_unlock(&nvmeq->q_lock);
 598         return result;
 599 }
 600
 601 static irqreturn_t nvme_irq_check(int irq, void *data)
 602 {
 603         struct nvme_queue *nvmeq = data;
 604         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 605         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 606                 return IRQ_NONE;
 607         return IRQ_WAKE_THREAD;
 608 }
 609
 610 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 611 {
 612         spin_lock_irq(&nvmeq->q_lock);
 613         cancel_cmdid_data(nvmeq, cmdid);
 614         spin_unlock_irq(&nvmeq->q_lock);
 615 }
 616
 617 /*
 618  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 619  * if the result is positive, it's an NVM Express status code
 620  */
 621 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 622                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 623 {
 624         int cmdid;
 625         struct sync_cmd_info cmdinfo;
 626
 627         cmdinfo.task = current;
 628         cmdinfo.status = -EINTR;
 629
 630         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 631                                                                 timeout);
 632         if (cmdid < 0)
 633                 return cmdid;
 634         cmd->common.command_id = cmdid;
 635
 636         set_current_state(TASK_KILLABLE);
 637         nvme_submit_cmd(nvmeq, cmd);
 638         schedule();
 639
 640         if (cmdinfo.status == -EINTR) {
 641                 nvme_abort_command(nvmeq, cmdid);
 642                 return -EINTR;
 643         }
 644
 645         if (result)
 646                 *result = cmdinfo.result;
 647
 648         return cmdinfo.status;
 649 }
 650
 651 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 652                                                                 u32 *result)
 653 {
 654         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 655 }
 656
 657 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 658 {
 659         int status;
 660         struct nvme_command c;
 661
 662         memset(&c, 0, sizeof(c));
 663         c.delete_queue.opcode = opcode;
 664         c.delete_queue.qid = cpu_to_le16(id);
 665
 666         status = nvme_submit_admin_cmd(dev, &c, NULL);
 667         if (status)
 668                 return -EIO;
 669         return 0;
 670 }
 671
 672 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 673                                                 struct nvme_queue *nvmeq)
 674 {
 675         int status;
 676         struct nvme_command c;
 677         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 678
 679         memset(&c, 0, sizeof(c));
 680         c.create_cq.opcode = nvme_admin_create_cq;
 681         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 682         c.create_cq.cqid = cpu_to_le16(qid);
 683         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 684         c.create_cq.cq_flags = cpu_to_le16(flags);
 685         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 686
 687         status = nvme_submit_admin_cmd(dev, &c, NULL);
 688         if (status)
 689                 return -EIO;
 690         return 0;
 691 }
 692
 693 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 694                                                 struct nvme_queue *nvmeq)
 695 {
 696         int status;
 697         struct nvme_command c;
 698         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 699
 700         memset(&c, 0, sizeof(c));
 701         c.create_sq.opcode = nvme_admin_create_sq;
 702         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 703         c.create_sq.sqid = cpu_to_le16(qid);
 704         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 705         c.create_sq.sq_flags = cpu_to_le16(flags);
 706         c.create_sq.cqid = cpu_to_le16(qid);
 707
 708         status = nvme_submit_admin_cmd(dev, &c, NULL);
 709         if (status)
 710                 return -EIO;
 711         return 0;
 712 }
 713
 714 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 715 {
 716         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 717 }
 718
 719 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 720 {
 721         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 722 }
 723
 724 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 725 {
 726         struct nvme_queue *nvmeq = dev->queues[qid];
 727
 728         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 729
 730         /* Don't tell the adapter to delete the admin queue */
 731         if (qid) {
 732                 adapter_delete_sq(dev, qid);
 733                 adapter_delete_cq(dev, qid);
 734         }
 735
 736         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 737                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 738         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 739                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 740         kfree(nvmeq);
 741 }
 742
 743 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 744                                                         int depth, int vector)
 745 {
 746         struct device *dmadev = &dev->pci_dev->dev;
 747         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 748         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 749         if (!nvmeq)
 750                 return NULL;
 751
 752         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 753                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 754         if (!nvmeq->cqes)
 755                 goto free_nvmeq;
 756         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 757
 758         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 759                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 760         if (!nvmeq->sq_cmds)
 761                 goto free_cqdma;
 762
 763         nvmeq->q_dmadev = dmadev;
 764         nvmeq->dev = dev;
 765         spin_lock_init(&nvmeq->q_lock);
 766         nvmeq->cq_head = 0;
 767         nvmeq->cq_phase = 1;
 768         init_waitqueue_head(&nvmeq->sq_full);
 769         bio_list_init(&nvmeq->sq_cong);
 770         nvmeq->q_db = &dev->dbs[qid * 2];
 771         nvmeq->q_depth = depth;
 772         nvmeq->cq_vector = vector;
 773
 774         return nvmeq;
 775
 776  free_cqdma:
 777         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 778                                                         nvmeq->cq_dma_addr);
 779  free_nvmeq:
 780         kfree(nvmeq);
 781         return NULL;
 782 }
 783
 784 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 785                                                         const char *name)
 786 {
 787         if (use_threaded_interrupts)
 788                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 789                                         nvme_irq_check, nvme_irq,
 790                                         IRQF_DISABLED | IRQF_SHARED,
 791                                         name, nvmeq);
 792         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 793                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 794 }
 795
 796 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 797                                         int qid, int cq_size, int vector)
 798 {
 799         int result;
 800         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 801
 802         if (!nvmeq)
 803                 return NULL;
 804
 805         result = adapter_alloc_cq(dev, qid, nvmeq);
 806         if (result < 0)
 807                 goto free_nvmeq;
 808
 809         result = adapter_alloc_sq(dev, qid, nvmeq);
 810         if (result < 0)
 811                 goto release_cq;
 812
 813         result = queue_request_irq(dev, nvmeq, "nvme");
 814         if (result < 0)
 815                 goto release_sq;
 816
 817         return nvmeq;
 818
 819  release_sq:
 820         adapter_delete_sq(dev, qid);
 821  release_cq:
 822         adapter_delete_cq(dev, qid);
 823  free_nvmeq:
 824         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 825                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 826         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 827                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 828         kfree(nvmeq);
 829         return NULL;
 830 }
 831
 832 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 833 {
 834         int result;
 835         u32 aqa;
 836         struct nvme_queue *nvmeq;
 837
 838         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 839
 840         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 841         if (!nvmeq)
 842                 return -ENOMEM;
 843
 844         aqa = nvmeq->q_depth - 1;
 845         aqa |= aqa << 16;
 846
 847         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 848         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 849         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 850
 851         writel(0, &dev->bar->cc);
 852         writel(aqa, &dev->bar->aqa);
 853         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 854         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 855         writel(dev->ctrl_config, &dev->bar->cc);
 856
 857         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 858                 msleep(100);
 859                 if (fatal_signal_pending(current))
 860                         return -EINTR;
 861         }
 862
 863         result = queue_request_irq(dev, nvmeq, "nvme admin");
 864         dev->queues[0] = nvmeq;
 865         return result;
 866 }
 867
 868 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 869                                 unsigned long addr, unsigned length,
 870                                 struct scatterlist **sgp)
 871 {
 872         int i, err, count, nents, offset;
 873         struct scatterlist *sg;
 874         struct page **pages;
 875
 876         if (addr & 3)
 877                 return -EINVAL;
 878         if (!length)
 879                 return -EINVAL;
 880
 881         offset = offset_in_page(addr);
 882         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 883         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 884
 885         err = get_user_pages_fast(addr, count, 1, pages);
 886         if (err < count) {
 887                 count = err;
 888                 err = -EFAULT;
 889                 goto put_pages;
 890         }
 891
 892         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 893         sg_init_table(sg, count);
 894         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 895         length -= (PAGE_SIZE - offset);
 896         for (i = 1; i < count; i++) {
 897                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 898                 length -= PAGE_SIZE;
 899         }
 900
 901         err = -ENOMEM;
 902         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 903                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 904         if (!nents)
 905                 goto put_pages;
 906
 907         kfree(pages);
 908         *sgp = sg;
 909         return nents;
 910
 911  put_pages:
 912         for (i = 0; i < count; i++)
 913                 put_page(pages[i]);
 914         kfree(pages);
 915         return err;
 916 }
 917
 918 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 919                                 unsigned long addr, int length,
 920                                 struct scatterlist *sg, int nents)
 921 {
 922         int i, count;
 923
 924         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 925         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 926
 927         for (i = 0; i < count; i++)
 928                 put_page(sg_page(&sg[i]));
 929 }
 930
 931 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 932                                         unsigned long addr, unsigned length,
 933                                         struct nvme_command *cmd)
 934 {
 935         int err, nents;
 936         struct scatterlist *sg;
 937         struct nvme_prps *prps;
 938
 939         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 940         if (nents < 0)
 941                 return nents;
 942         prps = nvme_setup_prps(dev->queues[0], &cmd->common, sg, length);
 943         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 944         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 945         nvme_free_prps(dev->queues[0], prps);
 946         return err ? -EIO : 0;
 947 }
 948
 949 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 950 {
 951         struct nvme_command c;
 952
 953         memset(&c, 0, sizeof(c));
 954         c.identify.opcode = nvme_admin_identify;
 955         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 956         c.identify.cns = cpu_to_le32(cns);
 957
 958         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 959 }
 960
 961 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
 962 {
 963         struct nvme_command c;
 964
 965         memset(&c, 0, sizeof(c));
 966         c.features.opcode = nvme_admin_get_features;
 967         c.features.nsid = cpu_to_le32(ns->ns_id);
 968         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
 969
 970         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 971 }
 972
 973 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
 974 {
 975         struct nvme_dev *dev = ns->dev;
 976         struct nvme_queue *nvmeq;
 977         struct nvme_user_io io;
 978         struct nvme_command c;
 979         unsigned length;
 980         u32 result;
 981         int nents, status;
 982         struct scatterlist *sg;
 983         struct nvme_prps *prps;
 984
 985         if (copy_from_user(&io, uio, sizeof(io)))
 986                 return -EFAULT;
 987         length = io.nblocks << io.block_shift;
 988         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
 989         if (nents < 0)
 990                 return nents;
 991
 992         memset(&c, 0, sizeof(c));
 993         c.rw.opcode = io.opcode;
 994         c.rw.flags = io.flags;
 995         c.rw.nsid = cpu_to_le32(io.nsid);
 996         c.rw.slba = cpu_to_le64(io.slba);
 997         c.rw.length = cpu_to_le16(io.nblocks - 1);
 998         c.rw.control = cpu_to_le16(io.control);
 999         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1000         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1001         c.rw.apptag = cpu_to_le16(io.apptag);
1002         c.rw.appmask = cpu_to_le16(io.appmask);
1003         nvmeq = get_nvmeq(ns);
1004         /* XXX: metadata */
1005         prps = nvme_setup_prps(nvmeq, &c.common, sg, length);
1006
1007         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1008          * disabled.  We may be preempted at any point, and be rescheduled
1009          * to a different CPU.  That will cause cacheline bouncing, but no
1010          * additional races since q_lock already protects against other CPUs.
1011          */
1012         put_nvmeq(nvmeq);
1013         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1014
1015         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1016         nvme_free_prps(nvmeq, prps);
1017         put_user(result, &uio->result);
1018         return status;
1019 }
1020
1021 static int nvme_download_firmware(struct nvme_ns *ns,
1022                                                 struct nvme_dlfw __user *udlfw)
1023 {
1024         struct nvme_dev *dev = ns->dev;
1025         struct nvme_dlfw dlfw;
1026         struct nvme_command c;
1027         int nents, status;
1028         struct scatterlist *sg;
1029         struct nvme_prps *prps;
1030
1031         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1032                 return -EFAULT;
1033         if (dlfw.length >= (1 << 30))
1034                 return -EINVAL;
1035
1036         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1037         if (nents < 0)
1038                 return nents;
1039
1040         memset(&c, 0, sizeof(c));
1041         c.dlfw.opcode = nvme_admin_download_fw;
1042         c.dlfw.numd = cpu_to_le32(dlfw.length);
1043         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1044         prps = nvme_setup_prps(dev->queues[0], &c.common, sg, dlfw.length * 4);
1045
1046         status = nvme_submit_admin_cmd(dev, &c, NULL);
1047         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1048         nvme_free_prps(dev->queues[0], prps);
1049         return status;
1050 }
1051
1052 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1053 {
1054         struct nvme_dev *dev = ns->dev;
1055         struct nvme_command c;
1056
1057         memset(&c, 0, sizeof(c));
1058         c.common.opcode = nvme_admin_activate_fw;
1059         c.common.rsvd10[0] = cpu_to_le32(arg);
1060
1061         return nvme_submit_admin_cmd(dev, &c, NULL);
1062 }
1063
1064 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1065                                                         unsigned long arg)
1066 {
1067         struct nvme_ns *ns = bdev->bd_disk->private_data;
1068
1069         switch (cmd) {
1070         case NVME_IOCTL_IDENTIFY_NS:
1071                 return nvme_identify(ns, arg, 0);
1072         case NVME_IOCTL_IDENTIFY_CTRL:
1073                 return nvme_identify(ns, arg, 1);
1074         case NVME_IOCTL_GET_RANGE_TYPE:
1075                 return nvme_get_range_type(ns, arg);
1076         case NVME_IOCTL_SUBMIT_IO:
1077                 return nvme_submit_io(ns, (void __user *)arg);
1078         case NVME_IOCTL_DOWNLOAD_FW:
1079                 return nvme_download_firmware(ns, (void __user *)arg);
1080         case NVME_IOCTL_ACTIVATE_FW:
1081                 return nvme_activate_firmware(ns, arg);
1082         default:
1083                 return -ENOTTY;
1084         }
1085 }
1086
1087 static const struct block_device_operations nvme_fops = {
1088         .owner          = THIS_MODULE,
1089         .ioctl          = nvme_ioctl,
1090 };
1091
1092 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1093                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1094 {
1095         struct nvme_ns *ns;
1096         struct gendisk *disk;
1097         int lbaf;
1098
1099         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1100                 return NULL;
1101
1102         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1103         if (!ns)
1104                 return NULL;
1105         ns->queue = blk_alloc_queue(GFP_KERNEL);
1106         if (!ns->queue)
1107                 goto out_free_ns;
1108         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1109                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1110         blk_queue_make_request(ns->queue, nvme_make_request);
1111         ns->dev = dev;
1112         ns->queue->queuedata = ns;
1113
1114         disk = alloc_disk(NVME_MINORS);
1115         if (!disk)
1116                 goto out_free_queue;
1117         ns->ns_id = index;
1118         ns->disk = disk;
1119         lbaf = id->flbas & 0xf;
1120         ns->lba_shift = id->lbaf[lbaf].ds;
1121
1122         disk->major = nvme_major;
1123         disk->minors = NVME_MINORS;
1124         disk->first_minor = NVME_MINORS * index;
1125         disk->fops = &nvme_fops;
1126         disk->private_data = ns;
1127         disk->queue = ns->queue;
1128         disk->driverfs_dev = &dev->pci_dev->dev;
1129         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1130         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1131
1132         return ns;
1133
1134  out_free_queue:
1135         blk_cleanup_queue(ns->queue);
1136  out_free_ns:
1137         kfree(ns);
1138         return NULL;
1139 }
1140
1141 static void nvme_ns_free(struct nvme_ns *ns)
1142 {
1143         put_disk(ns->disk);
1144         blk_cleanup_queue(ns->queue);
1145         kfree(ns);
1146 }
1147
1148 static int set_queue_count(struct nvme_dev *dev, int count)
1149 {
1150         int status;
1151         u32 result;
1152         struct nvme_command c;
1153         u32 q_count = (count - 1) | ((count - 1) << 16);
1154
1155         memset(&c, 0, sizeof(c));
1156         c.features.opcode = nvme_admin_get_features;
1157         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1158         c.features.dword11 = cpu_to_le32(q_count);
1159
1160         status = nvme_submit_admin_cmd(dev, &c, &result);
1161         if (status)
1162                 return -EIO;
1163         return min(result & 0xffff, result >> 16) + 1;
1164 }
1165
1166 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1167 {
1168         int result, cpu, i, nr_queues;
1169
1170         nr_queues = num_online_cpus();
1171         result = set_queue_count(dev, nr_queues);
1172         if (result < 0)
1173                 return result;
1174         if (result < nr_queues)
1175                 nr_queues = result;
1176
1177         /* Deregister the admin queue's interrupt */
1178         free_irq(dev->entry[0].vector, dev->queues[0]);
1179
1180         for (i = 0; i < nr_queues; i++)
1181                 dev->entry[i].entry = i;
1182         for (;;) {
1183                 result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues);
1184                 if (result == 0) {
1185                         break;
1186                 } else if (result > 0) {
1187                         nr_queues = result;
1188                         continue;
1189                 } else {
1190                         nr_queues = 1;
1191                         break;
1192                 }
1193         }
1194
1195         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1196         /* XXX: handle failure here */
1197
1198         cpu = cpumask_first(cpu_online_mask);
1199         for (i = 0; i < nr_queues; i++) {
1200                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1201                 cpu = cpumask_next(cpu, cpu_online_mask);
1202         }
1203
1204         for (i = 0; i < nr_queues; i++) {
1205                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1206                                                         NVME_Q_DEPTH, i);
1207                 if (!dev->queues[i + 1])
1208                         return -ENOMEM;
1209                 dev->queue_count++;
1210         }
1211
1212         return 0;
1213 }
1214
1215 static void nvme_free_queues(struct nvme_dev *dev)
1216 {
1217         int i;
1218
1219         for (i = dev->queue_count - 1; i >= 0; i--)
1220                 nvme_free_queue(dev, i);
1221 }
1222
1223 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1224 {
1225         int res, nn, i;
1226         struct nvme_ns *ns, *next;
1227         struct nvme_id_ctrl *ctrl;
1228         void *id;
1229         dma_addr_t dma_addr;
1230         struct nvme_command cid, crt;
1231
1232         res = nvme_setup_io_queues(dev);
1233         if (res)
1234                 return res;
1235
1236         /* XXX: Switch to a SG list once prp2 works */
1237         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1238                                                                 GFP_KERNEL);
1239
1240         memset(&cid, 0, sizeof(cid));
1241         cid.identify.opcode = nvme_admin_identify;
1242         cid.identify.nsid = 0;
1243         cid.identify.prp1 = cpu_to_le64(dma_addr);
1244         cid.identify.cns = cpu_to_le32(1);
1245
1246         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1247         if (res) {
1248                 res = -EIO;
1249                 goto out_free;
1250         }
1251
1252         ctrl = id;
1253         nn = le32_to_cpup(&ctrl->nn);
1254         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1255         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1256         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1257
1258         cid.identify.cns = 0;
1259         memset(&crt, 0, sizeof(crt));
1260         crt.features.opcode = nvme_admin_get_features;
1261         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1262         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1263
1264         for (i = 0; i < nn; i++) {
1265                 cid.identify.nsid = cpu_to_le32(i);
1266                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1267                 if (res)
1268                         continue;
1269
1270                 if (((struct nvme_id_ns *)id)->ncap == 0)
1271                         continue;
1272
1273                 crt.features.nsid = cpu_to_le32(i);
1274                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1275                 if (res)
1276                         continue;
1277
1278                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1279                 if (ns)
1280                         list_add_tail(&ns->list, &dev->namespaces);
1281         }
1282         list_for_each_entry(ns, &dev->namespaces, list)
1283                 add_disk(ns->disk);
1284
1285         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1286         return 0;
1287
1288  out_free:
1289         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1290                 list_del(&ns->list);
1291                 nvme_ns_free(ns);
1292         }
1293
1294         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1295         return res;
1296 }
1297
1298 static int nvme_dev_remove(struct nvme_dev *dev)
1299 {
1300         struct nvme_ns *ns, *next;
1301
1302         /* TODO: wait all I/O finished or cancel them */
1303
1304         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1305                 list_del(&ns->list);
1306                 del_gendisk(ns->disk);
1307                 nvme_ns_free(ns);
1308         }
1309
1310         nvme_free_queues(dev);
1311
1312         return 0;
1313 }
1314
1315 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1316 {
1317         struct device *dmadev = &dev->pci_dev->dev;
1318         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1319                                                 PAGE_SIZE, PAGE_SIZE, 0);
1320         if (!dev->prp_page_pool)
1321                 return -ENOMEM;
1322
1323         /* Optimisation for I/Os between 4k and 128k */
1324         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1325                                                 256, 256, 0);
1326         if (!dev->prp_small_pool) {
1327                 dma_pool_destroy(dev->prp_page_pool);
1328                 return -ENOMEM;
1329         }
1330         return 0;
1331 }
1332
1333 static void nvme_release_prp_pools(struct nvme_dev *dev)
1334 {
1335         dma_pool_destroy(dev->prp_page_pool);
1336         dma_pool_destroy(dev->prp_small_pool);
1337 }
1338
1339 /* XXX: Use an ida or something to let remove / add work correctly */
1340 static void nvme_set_instance(struct nvme_dev *dev)
1341 {
1342         static int instance;
1343         dev->instance = instance++;
1344 }
1345
1346 static void nvme_release_instance(struct nvme_dev *dev)
1347 {
1348 }
1349
1350 static int __devinit nvme_probe(struct pci_dev *pdev,
1351                                                 const struct pci_device_id *id)
1352 {
1353         int bars, result = -ENOMEM;
1354         struct nvme_dev *dev;
1355
1356         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1357         if (!dev)
1358                 return -ENOMEM;
1359         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1360                                                                 GFP_KERNEL);
1361         if (!dev->entry)
1362                 goto free;
1363         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1364                                                                 GFP_KERNEL);
1365         if (!dev->queues)
1366                 goto free;
1367
1368         if (pci_enable_device_mem(pdev))
1369                 goto free;
1370         pci_set_master(pdev);
1371         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1372         if (pci_request_selected_regions(pdev, bars, "nvme"))
1373                 goto disable;
1374
1375         INIT_LIST_HEAD(&dev->namespaces);
1376         dev->pci_dev = pdev;
1377         pci_set_drvdata(pdev, dev);
1378         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1379         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1380         nvme_set_instance(dev);
1381         dev->entry[0].vector = pdev->irq;
1382
1383         result = nvme_setup_prp_pools(dev);
1384         if (result)
1385                 goto disable_msix;
1386
1387         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1388         if (!dev->bar) {
1389                 result = -ENOMEM;
1390                 goto disable_msix;
1391         }
1392
1393         result = nvme_configure_admin_queue(dev);
1394         if (result)
1395                 goto unmap;
1396         dev->queue_count++;
1397
1398         result = nvme_dev_add(dev);
1399         if (result)
1400                 goto delete;
1401         return 0;
1402
1403  delete:
1404         nvme_free_queues(dev);
1405  unmap:
1406         iounmap(dev->bar);
1407  disable_msix:
1408         pci_disable_msix(pdev);
1409         nvme_release_instance(dev);
1410         nvme_release_prp_pools(dev);
1411  disable:
1412         pci_disable_device(pdev);
1413         pci_release_regions(pdev);
1414  free:
1415         kfree(dev->queues);
1416         kfree(dev->entry);
1417         kfree(dev);
1418         return result;
1419 }
1420
1421 static void __devexit nvme_remove(struct pci_dev *pdev)
1422 {
1423         struct nvme_dev *dev = pci_get_drvdata(pdev);
1424         nvme_dev_remove(dev);
1425         pci_disable_msix(pdev);
1426         iounmap(dev->bar);
1427         nvme_release_instance(dev);
1428         nvme_release_prp_pools(dev);
1429         pci_disable_device(pdev);
1430         pci_release_regions(pdev);
1431         kfree(dev->queues);
1432         kfree(dev->entry);
1433         kfree(dev);
1434 }
1435
1436 /* These functions are yet to be implemented */
1437 #define nvme_error_detected NULL
1438 #define nvme_dump_registers NULL
1439 #define nvme_link_reset NULL
1440 #define nvme_slot_reset NULL
1441 #define nvme_error_resume NULL
1442 #define nvme_suspend NULL
1443 #define nvme_resume NULL
1444
1445 static struct pci_error_handlers nvme_err_handler = {
1446         .error_detected = nvme_error_detected,
1447         .mmio_enabled   = nvme_dump_registers,
1448         .link_reset     = nvme_link_reset,
1449         .slot_reset     = nvme_slot_reset,
1450         .resume         = nvme_error_resume,
1451 };
1452
1453 /* Move to pci_ids.h later */
1454 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1455
1456 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1457         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1458         { 0, }
1459 };
1460 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1461
1462 static struct pci_driver nvme_driver = {
1463         .name           = "nvme",
1464         .id_table       = nvme_id_table,
1465         .probe          = nvme_probe,
1466         .remove         = __devexit_p(nvme_remove),
1467         .suspend        = nvme_suspend,
1468         .resume         = nvme_resume,
1469         .err_handler    = &nvme_err_handler,
1470 };
1471
1472 static int __init nvme_init(void)
1473 {
1474         int result;
1475
1476         nvme_major = register_blkdev(nvme_major, "nvme");
1477         if (nvme_major <= 0)
1478                 return -EBUSY;
1479
1480         result = pci_register_driver(&nvme_driver);
1481         if (!result)
1482                 return 0;
1483
1484         unregister_blkdev(nvme_major, "nvme");
1485         return result;
1486 }
1487
1488 static void __exit nvme_exit(void)
1489 {
1490         pci_unregister_driver(&nvme_driver);
1491         unregister_blkdev(nvme_major, "nvme");
1492 }
1493
1494 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1495 MODULE_LICENSE("GPL");
1496 MODULE_VERSION("0.2");
1497 module_init(nvme_init);
1498 module_exit(nvme_exit);