drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/errno.h>
  24 #include <linux/fs.h>
  25 #include <linux/genhd.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/types.h>
  40 #include <linux/version.h>
  41
  42 #define NVME_Q_DEPTH 1024
  43 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  44 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  45 #define NVME_MINORS 64
  46 #define IO_TIMEOUT      (5 * HZ)
  47 #define ADMIN_TIMEOUT   (60 * HZ)
  48
  49 static int nvme_major;
  50 module_param(nvme_major, int, 0);
  51
  52 static int use_threaded_interrupts;
  53 module_param(use_threaded_interrupts, int, 0);
  54
  55 static DEFINE_SPINLOCK(dev_list_lock);
  56 static LIST_HEAD(dev_list);
  57 static struct task_struct *nvme_thread;
  58
  59 /*
  60  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  61  */
  62 struct nvme_dev {
  63         struct list_head node;
  64         struct nvme_queue **queues;
  65         u32 __iomem *dbs;
  66         struct pci_dev *pci_dev;
  67         struct dma_pool *prp_page_pool;
  68         struct dma_pool *prp_small_pool;
  69         int instance;
  70         int queue_count;
  71         u32 ctrl_config;
  72         struct msix_entry *entry;
  73         struct nvme_bar __iomem *bar;
  74         struct list_head namespaces;
  75         char serial[20];
  76         char model[40];
  77         char firmware_rev[8];
  78 };
  79
  80 /*
  81  * An NVM Express namespace is equivalent to a SCSI LUN
  82  */
  83 struct nvme_ns {
  84         struct list_head list;
  85
  86         struct nvme_dev *dev;
  87         struct request_queue *queue;
  88         struct gendisk *disk;
  89
  90         int ns_id;
  91         int lba_shift;
  92 };
  93
  94 /*
  95  * An NVM Express queue.  Each device has at least two (one for admin
  96  * commands and one for I/O commands).
  97  */
  98 struct nvme_queue {
  99         struct device *q_dmadev;
 100         struct nvme_dev *dev;
 101         spinlock_t q_lock;
 102         struct nvme_command *sq_cmds;
 103         volatile struct nvme_completion *cqes;
 104         dma_addr_t sq_dma_addr;
 105         dma_addr_t cq_dma_addr;
 106         wait_queue_head_t sq_full;
 107         wait_queue_t sq_cong_wait;
 108         struct bio_list sq_cong;
 109         u32 __iomem *q_db;
 110         u16 q_depth;
 111         u16 cq_vector;
 112         u16 sq_head;
 113         u16 sq_tail;
 114         u16 cq_head;
 115         u16 cq_phase;
 116         unsigned long cmdid_data[];
 117 };
 118
 119 /*
 120  * Check we didin't inadvertently grow the command struct
 121  */
 122 static inline void _nvme_check_size(void)
 123 {
 124         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 132         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 133 }
 134
 135 struct nvme_cmd_info {
 136         unsigned long ctx;
 137         unsigned long timeout;
 138 };
 139
 140 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 141 {
 142         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 143 }
 144
 145 /**
 146  * alloc_cmdid() - Allocate a Command ID
 147  * @nvmeq: The queue that will be used for this command
 148  * @ctx: A pointer that will be passed to the handler
 149  * @handler: The ID of the handler to call
 150  *
 151  * Allocate a Command ID for a queue.  The data passed in will
 152  * be passed to the completion handler.  This is implemented by using
 153  * the bottom two bits of the ctx pointer to store the handler ID.
 154  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 155  * We can change this if it becomes a problem.
 156  */
 157 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 158                                                         unsigned timeout)
 159 {
 160         int depth = nvmeq->q_depth - 1;
 161         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 162         int cmdid;
 163
 164         BUG_ON((unsigned long)ctx & 3);
 165
 166         do {
 167                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 168                 if (cmdid >= depth)
 169                         return -EBUSY;
 170         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 171
 172         info[cmdid].ctx = (unsigned long)ctx | handler;
 173         info[cmdid].timeout = jiffies + timeout;
 174         return cmdid;
 175 }
 176
 177 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 178                                                 int handler, unsigned timeout)
 179 {
 180         int cmdid;
 181         wait_event_killable(nvmeq->sq_full,
 182                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 183         return (cmdid < 0) ? -EINTR : cmdid;
 184 }
 185
 186 /*
 187  * If you need more than four handlers, you'll need to change how
 188  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 189  * CMD_CTX value instead, if that works for your situation.
 190  */
 191 enum {
 192         sync_completion_id = 0,
 193         bio_completion_id,
 194 };
 195
 196 /* Special values must be a multiple of 4, and less than 0x1000 */
 197 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 198 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 199 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 200 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 201 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 202
 203 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 204 {
 205         unsigned long data;
 206         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 207
 208         if (cmdid >= nvmeq->q_depth)
 209                 return CMD_CTX_INVALID;
 210         data = info[cmdid].ctx;
 211         info[cmdid].ctx = CMD_CTX_COMPLETED;
 212         clear_bit(cmdid, nvmeq->cmdid_data);
 213         wake_up(&nvmeq->sq_full);
 214         return data;
 215 }
 216
 217 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
 218 {
 219         unsigned long data;
 220         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 221         data = info[cmdid].ctx;
 222         info[cmdid].ctx = CMD_CTX_CANCELLED;
 223         return data;
 224 }
 225
 226 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 227 {
 228         return ns->dev->queues[get_cpu() + 1];
 229 }
 230
 231 static void put_nvmeq(struct nvme_queue *nvmeq)
 232 {
 233         put_cpu();
 234 }
 235
 236 /**
 237  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 238  * @nvmeq: The queue to use
 239  * @cmd: The command to send
 240  *
 241  * Safe to use from interrupt context
 242  */
 243 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 244 {
 245         unsigned long flags;
 246         u16 tail;
 247         spin_lock_irqsave(&nvmeq->q_lock, flags);
 248         tail = nvmeq->sq_tail;
 249         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 250         if (++tail == nvmeq->q_depth)
 251                 tail = 0;
 252         writel(tail, nvmeq->q_db);
 253         nvmeq->sq_tail = tail;
 254         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 255
 256         return 0;
 257 }
 258
 259 struct nvme_prps {
 260         int npages;
 261         dma_addr_t first_dma;
 262         __le64 *list[0];
 263 };
 264
 265 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 266 {
 267         const int last_prp = PAGE_SIZE / 8 - 1;
 268         int i;
 269         dma_addr_t prp_dma;
 270
 271         if (!prps)
 272                 return;
 273
 274         prp_dma = prps->first_dma;
 275
 276         if (prps->npages == 0)
 277                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 278         for (i = 0; i < prps->npages; i++) {
 279                 __le64 *prp_list = prps->list[i];
 280                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 281                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 282                 prp_dma = next_prp_dma;
 283         }
 284         kfree(prps);
 285 }
 286
 287 struct nvme_bio {
 288         struct bio *bio;
 289         int nents;
 290         struct nvme_prps *prps;
 291         struct scatterlist sg[0];
 292 };
 293
 294 /* XXX: use a mempool */
 295 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 296 {
 297         return kzalloc(sizeof(struct nvme_bio) +
 298                         sizeof(struct scatterlist) * nseg, gfp);
 299 }
 300
 301 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 302 {
 303         nvme_free_prps(nvmeq->dev, nbio->prps);
 304         kfree(nbio);
 305 }
 306
 307 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 308                                                 struct nvme_completion *cqe)
 309 {
 310         struct nvme_bio *nbio = ctx;
 311         struct bio *bio = nbio->bio;
 312         u16 status = le16_to_cpup(&cqe->status) >> 1;
 313
 314         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 315                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 316         free_nbio(nvmeq, nbio);
 317         if (status) {
 318                 bio_endio(bio, -EIO);
 319         } else if (bio->bi_vcnt > bio->bi_idx) {
 320                 bio_list_add(&nvmeq->sq_cong, bio);
 321                 wake_up_process(nvme_thread);
 322         } else {
 323                 bio_endio(bio, 0);
 324         }
 325 }
 326
 327 /* length is in bytes */
 328 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 329                                         struct nvme_common_command *cmd,
 330                                         struct scatterlist *sg, int length)
 331 {
 332         struct dma_pool *pool;
 333         int dma_len = sg_dma_len(sg);
 334         u64 dma_addr = sg_dma_address(sg);
 335         int offset = offset_in_page(dma_addr);
 336         __le64 *prp_list;
 337         dma_addr_t prp_dma;
 338         int nprps, npages, i, prp_page;
 339         struct nvme_prps *prps = NULL;
 340
 341         cmd->prp1 = cpu_to_le64(dma_addr);
 342         length -= (PAGE_SIZE - offset);
 343         if (length <= 0)
 344                 return prps;
 345
 346         dma_len -= (PAGE_SIZE - offset);
 347         if (dma_len) {
 348                 dma_addr += (PAGE_SIZE - offset);
 349         } else {
 350                 sg = sg_next(sg);
 351                 dma_addr = sg_dma_address(sg);
 352                 dma_len = sg_dma_len(sg);
 353         }
 354
 355         if (length <= PAGE_SIZE) {
 356                 cmd->prp2 = cpu_to_le64(dma_addr);
 357                 return prps;
 358         }
 359
 360         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 361         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 362         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 363         prp_page = 0;
 364         if (nprps <= (256 / 8)) {
 365                 pool = dev->prp_small_pool;
 366                 prps->npages = 0;
 367         } else {
 368                 pool = dev->prp_page_pool;
 369                 prps->npages = npages;
 370         }
 371
 372         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 373         prps->list[prp_page++] = prp_list;
 374         prps->first_dma = prp_dma;
 375         cmd->prp2 = cpu_to_le64(prp_dma);
 376         i = 0;
 377         for (;;) {
 378                 if (i == PAGE_SIZE / 8) {
 379                         __le64 *old_prp_list = prp_list;
 380                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 381                         prps->list[prp_page++] = prp_list;
 382                         prp_list[0] = old_prp_list[i - 1];
 383                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 384                         i = 1;
 385                 }
 386                 prp_list[i++] = cpu_to_le64(dma_addr);
 387                 dma_len -= PAGE_SIZE;
 388                 dma_addr += PAGE_SIZE;
 389                 length -= PAGE_SIZE;
 390                 if (length <= 0)
 391                         break;
 392                 if (dma_len > 0)
 393                         continue;
 394                 BUG_ON(dma_len < 0);
 395                 sg = sg_next(sg);
 396                 dma_addr = sg_dma_address(sg);
 397                 dma_len = sg_dma_len(sg);
 398         }
 399
 400         return prps;
 401 }
 402
 403 /* NVMe scatterlists require no holes in the virtual address */
 404 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 405                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 406
 407 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 408                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 409 {
 410         struct bio_vec *bvec, *bvprv = NULL;
 411         struct scatterlist *sg = NULL;
 412         int i, old_idx, length = 0, nsegs = 0;
 413
 414         sg_init_table(nbio->sg, psegs);
 415         old_idx = bio->bi_idx;
 416         bio_for_each_segment(bvec, bio, i) {
 417                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 418                         sg->length += bvec->bv_len;
 419                 } else {
 420                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 421                                 break;
 422                         sg = sg ? sg + 1 : nbio->sg;
 423                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 424                                                         bvec->bv_offset);
 425                         nsegs++;
 426                 }
 427                 length += bvec->bv_len;
 428                 bvprv = bvec;
 429         }
 430         bio->bi_idx = i;
 431         nbio->nents = nsegs;
 432         sg_mark_end(sg);
 433         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 434                 bio->bi_idx = old_idx;
 435                 return -ENOMEM;
 436         }
 437         return length;
 438 }
 439
 440 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 441                                                                 int cmdid)
 442 {
 443         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 444
 445         memset(cmnd, 0, sizeof(*cmnd));
 446         cmnd->common.opcode = nvme_cmd_flush;
 447         cmnd->common.command_id = cmdid;
 448         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 449
 450         if (++nvmeq->sq_tail == nvmeq->q_depth)
 451                 nvmeq->sq_tail = 0;
 452         writel(nvmeq->sq_tail, nvmeq->q_db);
 453
 454         return 0;
 455 }
 456
 457 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 458 {
 459         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 460                                                 sync_completion_id, IO_TIMEOUT);
 461         if (unlikely(cmdid < 0))
 462                 return cmdid;
 463
 464         return nvme_submit_flush(nvmeq, ns, cmdid);
 465 }
 466
 467 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 468                                                                 struct bio *bio)
 469 {
 470         struct nvme_command *cmnd;
 471         struct nvme_bio *nbio;
 472         enum dma_data_direction dma_dir;
 473         int cmdid, length, result = -ENOMEM;
 474         u16 control;
 475         u32 dsmgmt;
 476         int psegs = bio_phys_segments(ns->queue, bio);
 477
 478         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 479                 result = nvme_submit_flush_data(nvmeq, ns);
 480                 if (result)
 481                         return result;
 482         }
 483
 484         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 485         if (!nbio)
 486                 goto nomem;
 487         nbio->bio = bio;
 488
 489         result = -EBUSY;
 490         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 491         if (unlikely(cmdid < 0))
 492                 goto free_nbio;
 493
 494         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 495                 return nvme_submit_flush(nvmeq, ns, cmdid);
 496
 497         control = 0;
 498         if (bio->bi_rw & REQ_FUA)
 499                 control |= NVME_RW_FUA;
 500         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 501                 control |= NVME_RW_LR;
 502
 503         dsmgmt = 0;
 504         if (bio->bi_rw & REQ_RAHEAD)
 505                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 506
 507         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 508
 509         memset(cmnd, 0, sizeof(*cmnd));
 510         if (bio_data_dir(bio)) {
 511                 cmnd->rw.opcode = nvme_cmd_write;
 512                 dma_dir = DMA_TO_DEVICE;
 513         } else {
 514                 cmnd->rw.opcode = nvme_cmd_read;
 515                 dma_dir = DMA_FROM_DEVICE;
 516         }
 517
 518         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 519         if (result < 0)
 520                 goto free_nbio;
 521         length = result;
 522
 523         cmnd->rw.command_id = cmdid;
 524         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 525         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 526                                                                 length);
 527         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 528         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 529         cmnd->rw.control = cpu_to_le16(control);
 530         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 531
 532         bio->bi_sector += length >> 9;
 533
 534         if (++nvmeq->sq_tail == nvmeq->q_depth)
 535                 nvmeq->sq_tail = 0;
 536         writel(nvmeq->sq_tail, nvmeq->q_db);
 537
 538         return 0;
 539
 540  free_nbio:
 541         free_nbio(nvmeq, nbio);
 542  nomem:
 543         return result;
 544 }
 545
 546 /*
 547  * NB: return value of non-zero would mean that we were a stacking driver.
 548  * make_request must always succeed.
 549  */
 550 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 551 {
 552         struct nvme_ns *ns = q->queuedata;
 553         struct nvme_queue *nvmeq = get_nvmeq(ns);
 554         int result = -EBUSY;
 555
 556         spin_lock_irq(&nvmeq->q_lock);
 557         if (bio_list_empty(&nvmeq->sq_cong))
 558                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 559         if (unlikely(result)) {
 560                 if (bio_list_empty(&nvmeq->sq_cong))
 561                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 562                 bio_list_add(&nvmeq->sq_cong, bio);
 563         }
 564
 565         spin_unlock_irq(&nvmeq->q_lock);
 566         put_nvmeq(nvmeq);
 567
 568         return 0;
 569 }
 570
 571 struct sync_cmd_info {
 572         struct task_struct *task;
 573         u32 result;
 574         int status;
 575 };
 576
 577 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 578                                                 struct nvme_completion *cqe)
 579 {
 580         struct sync_cmd_info *cmdinfo = ctx;
 581         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 582                 return;
 583         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 584                 return;
 585         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 586                 dev_warn(nvmeq->q_dmadev,
 587                                 "completed id %d twice on queue %d\n",
 588                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 589                 return;
 590         }
 591         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 592                 dev_warn(nvmeq->q_dmadev,
 593                                 "invalid id %d completed on queue %d\n",
 594                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 595                 return;
 596         }
 597         cmdinfo->result = le32_to_cpup(&cqe->result);
 598         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 599         wake_up_process(cmdinfo->task);
 600 }
 601
 602 typedef void (*completion_fn)(struct nvme_queue *, void *,
 603                                                 struct nvme_completion *);
 604
 605 static const completion_fn nvme_completions[4] = {
 606         [sync_completion_id] = sync_completion,
 607         [bio_completion_id]  = bio_completion,
 608 };
 609
 610 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 611 {
 612         u16 head, phase;
 613
 614         head = nvmeq->cq_head;
 615         phase = nvmeq->cq_phase;
 616
 617         for (;;) {
 618                 unsigned long data;
 619                 void *ptr;
 620                 unsigned char handler;
 621                 struct nvme_completion cqe = nvmeq->cqes[head];
 622                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 623                         break;
 624                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 625                 if (++head == nvmeq->q_depth) {
 626                         head = 0;
 627                         phase = !phase;
 628                 }
 629
 630                 data = free_cmdid(nvmeq, cqe.command_id);
 631                 handler = data & 3;
 632                 ptr = (void *)(data & ~3UL);
 633                 nvme_completions[handler](nvmeq, ptr, &cqe);
 634         }
 635
 636         /* If the controller ignores the cq head doorbell and continuously
 637          * writes to the queue, it is theoretically possible to wrap around
 638          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 639          * requires that 0.1% of your interrupts are handled, so this isn't
 640          * a big problem.
 641          */
 642         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 643                 return IRQ_NONE;
 644
 645         writel(head, nvmeq->q_db + 1);
 646         nvmeq->cq_head = head;
 647         nvmeq->cq_phase = phase;
 648
 649         return IRQ_HANDLED;
 650 }
 651
 652 static irqreturn_t nvme_irq(int irq, void *data)
 653 {
 654         irqreturn_t result;
 655         struct nvme_queue *nvmeq = data;
 656         spin_lock(&nvmeq->q_lock);
 657         result = nvme_process_cq(nvmeq);
 658         spin_unlock(&nvmeq->q_lock);
 659         return result;
 660 }
 661
 662 static irqreturn_t nvme_irq_check(int irq, void *data)
 663 {
 664         struct nvme_queue *nvmeq = data;
 665         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 666         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 667                 return IRQ_NONE;
 668         return IRQ_WAKE_THREAD;
 669 }
 670
 671 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 672 {
 673         spin_lock_irq(&nvmeq->q_lock);
 674         cancel_cmdid(nvmeq, cmdid);
 675         spin_unlock_irq(&nvmeq->q_lock);
 676 }
 677
 678 /*
 679  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 680  * if the result is positive, it's an NVM Express status code
 681  */
 682 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 683                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 684 {
 685         int cmdid;
 686         struct sync_cmd_info cmdinfo;
 687
 688         cmdinfo.task = current;
 689         cmdinfo.status = -EINTR;
 690
 691         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 692                                                                 timeout);
 693         if (cmdid < 0)
 694                 return cmdid;
 695         cmd->common.command_id = cmdid;
 696
 697         set_current_state(TASK_KILLABLE);
 698         nvme_submit_cmd(nvmeq, cmd);
 699         schedule();
 700
 701         if (cmdinfo.status == -EINTR) {
 702                 nvme_abort_command(nvmeq, cmdid);
 703                 return -EINTR;
 704         }
 705
 706         if (result)
 707                 *result = cmdinfo.result;
 708
 709         return cmdinfo.status;
 710 }
 711
 712 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 713                                                                 u32 *result)
 714 {
 715         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 716 }
 717
 718 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 719 {
 720         int status;
 721         struct nvme_command c;
 722
 723         memset(&c, 0, sizeof(c));
 724         c.delete_queue.opcode = opcode;
 725         c.delete_queue.qid = cpu_to_le16(id);
 726
 727         status = nvme_submit_admin_cmd(dev, &c, NULL);
 728         if (status)
 729                 return -EIO;
 730         return 0;
 731 }
 732
 733 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 734                                                 struct nvme_queue *nvmeq)
 735 {
 736         int status;
 737         struct nvme_command c;
 738         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 739
 740         memset(&c, 0, sizeof(c));
 741         c.create_cq.opcode = nvme_admin_create_cq;
 742         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 743         c.create_cq.cqid = cpu_to_le16(qid);
 744         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 745         c.create_cq.cq_flags = cpu_to_le16(flags);
 746         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 747
 748         status = nvme_submit_admin_cmd(dev, &c, NULL);
 749         if (status)
 750                 return -EIO;
 751         return 0;
 752 }
 753
 754 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 755                                                 struct nvme_queue *nvmeq)
 756 {
 757         int status;
 758         struct nvme_command c;
 759         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 760
 761         memset(&c, 0, sizeof(c));
 762         c.create_sq.opcode = nvme_admin_create_sq;
 763         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 764         c.create_sq.sqid = cpu_to_le16(qid);
 765         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 766         c.create_sq.sq_flags = cpu_to_le16(flags);
 767         c.create_sq.cqid = cpu_to_le16(qid);
 768
 769         status = nvme_submit_admin_cmd(dev, &c, NULL);
 770         if (status)
 771                 return -EIO;
 772         return 0;
 773 }
 774
 775 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 776 {
 777         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 778 }
 779
 780 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 781 {
 782         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 783 }
 784
 785 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 786 {
 787         struct nvme_queue *nvmeq = dev->queues[qid];
 788         int vector = dev->entry[nvmeq->cq_vector].vector;
 789
 790         irq_set_affinity_hint(vector, NULL);
 791         free_irq(vector, nvmeq);
 792
 793         /* Don't tell the adapter to delete the admin queue */
 794         if (qid) {
 795                 adapter_delete_sq(dev, qid);
 796                 adapter_delete_cq(dev, qid);
 797         }
 798
 799         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 800                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 801         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 802                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 803         kfree(nvmeq);
 804 }
 805
 806 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 807                                                         int depth, int vector)
 808 {
 809         struct device *dmadev = &dev->pci_dev->dev;
 810         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 811         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 812         if (!nvmeq)
 813                 return NULL;
 814
 815         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 816                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 817         if (!nvmeq->cqes)
 818                 goto free_nvmeq;
 819         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 820
 821         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 822                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 823         if (!nvmeq->sq_cmds)
 824                 goto free_cqdma;
 825
 826         nvmeq->q_dmadev = dmadev;
 827         nvmeq->dev = dev;
 828         spin_lock_init(&nvmeq->q_lock);
 829         nvmeq->cq_head = 0;
 830         nvmeq->cq_phase = 1;
 831         init_waitqueue_head(&nvmeq->sq_full);
 832         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 833         bio_list_init(&nvmeq->sq_cong);
 834         nvmeq->q_db = &dev->dbs[qid * 2];
 835         nvmeq->q_depth = depth;
 836         nvmeq->cq_vector = vector;
 837
 838         return nvmeq;
 839
 840  free_cqdma:
 841         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 842                                                         nvmeq->cq_dma_addr);
 843  free_nvmeq:
 844         kfree(nvmeq);
 845         return NULL;
 846 }
 847
 848 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 849                                                         const char *name)
 850 {
 851         if (use_threaded_interrupts)
 852                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 853                                         nvme_irq_check, nvme_irq,
 854                                         IRQF_DISABLED | IRQF_SHARED,
 855                                         name, nvmeq);
 856         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 857                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 858 }
 859
 860 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 861                                         int qid, int cq_size, int vector)
 862 {
 863         int result;
 864         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 865
 866         if (!nvmeq)
 867                 return NULL;
 868
 869         result = adapter_alloc_cq(dev, qid, nvmeq);
 870         if (result < 0)
 871                 goto free_nvmeq;
 872
 873         result = adapter_alloc_sq(dev, qid, nvmeq);
 874         if (result < 0)
 875                 goto release_cq;
 876
 877         result = queue_request_irq(dev, nvmeq, "nvme");
 878         if (result < 0)
 879                 goto release_sq;
 880
 881         return nvmeq;
 882
 883  release_sq:
 884         adapter_delete_sq(dev, qid);
 885  release_cq:
 886         adapter_delete_cq(dev, qid);
 887  free_nvmeq:
 888         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 889                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 890         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 891                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 892         kfree(nvmeq);
 893         return NULL;
 894 }
 895
 896 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 897 {
 898         int result;
 899         u32 aqa;
 900         u64 cap;
 901         unsigned long timeout;
 902         struct nvme_queue *nvmeq;
 903
 904         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 905
 906         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 907         if (!nvmeq)
 908                 return -ENOMEM;
 909
 910         aqa = nvmeq->q_depth - 1;
 911         aqa |= aqa << 16;
 912
 913         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 914         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 915         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 916         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 917
 918         writel(0, &dev->bar->cc);
 919         writel(aqa, &dev->bar->aqa);
 920         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 921         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 922         writel(dev->ctrl_config, &dev->bar->cc);
 923
 924         cap = readq(&dev->bar->cap);
 925         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
 926
 927         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 928                 msleep(100);
 929                 if (fatal_signal_pending(current))
 930                         return -EINTR;
 931                 if (time_after(jiffies, timeout)) {
 932                         dev_err(&dev->pci_dev->dev,
 933                                 "Device not ready; aborting initialisation\n");
 934                         return -ENODEV;
 935                 }
 936         }
 937
 938         result = queue_request_irq(dev, nvmeq, "nvme admin");
 939         dev->queues[0] = nvmeq;
 940         return result;
 941 }
 942
 943 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 944                                 unsigned long addr, unsigned length,
 945                                 struct scatterlist **sgp)
 946 {
 947         int i, err, count, nents, offset;
 948         struct scatterlist *sg;
 949         struct page **pages;
 950
 951         if (addr & 3)
 952                 return -EINVAL;
 953         if (!length)
 954                 return -EINVAL;
 955
 956         offset = offset_in_page(addr);
 957         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 958         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 959
 960         err = get_user_pages_fast(addr, count, 1, pages);
 961         if (err < count) {
 962                 count = err;
 963                 err = -EFAULT;
 964                 goto put_pages;
 965         }
 966
 967         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 968         sg_init_table(sg, count);
 969         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 970         length -= (PAGE_SIZE - offset);
 971         for (i = 1; i < count; i++) {
 972                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 973                 length -= PAGE_SIZE;
 974         }
 975
 976         err = -ENOMEM;
 977         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 978                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 979         if (!nents)
 980                 goto put_pages;
 981
 982         kfree(pages);
 983         *sgp = sg;
 984         return nents;
 985
 986  put_pages:
 987         for (i = 0; i < count; i++)
 988                 put_page(pages[i]);
 989         kfree(pages);
 990         return err;
 991 }
 992
 993 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 994                                 unsigned long addr, int length,
 995                                 struct scatterlist *sg, int nents)
 996 {
 997         int i, count;
 998
 999         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1000         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
1001
1002         for (i = 0; i < count; i++)
1003                 put_page(sg_page(&sg[i]));
1004 }
1005
1006 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
1007                                         unsigned long addr, unsigned length,
1008                                         struct nvme_command *cmd)
1009 {
1010         int err, nents;
1011         struct scatterlist *sg;
1012         struct nvme_prps *prps;
1013
1014         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1015         if (nents < 0)
1016                 return nents;
1017         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1018         err = nvme_submit_admin_cmd(dev, cmd, NULL);
1019         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1020         nvme_free_prps(dev, prps);
1021         return err ? -EIO : 0;
1022 }
1023
1024 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1025 {
1026         struct nvme_command c;
1027
1028         memset(&c, 0, sizeof(c));
1029         c.identify.opcode = nvme_admin_identify;
1030         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1031         c.identify.cns = cpu_to_le32(cns);
1032
1033         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1034 }
1035
1036 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1037 {
1038         struct nvme_command c;
1039
1040         memset(&c, 0, sizeof(c));
1041         c.features.opcode = nvme_admin_get_features;
1042         c.features.nsid = cpu_to_le32(ns->ns_id);
1043         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1044
1045         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1046 }
1047
1048 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1049 {
1050         struct nvme_dev *dev = ns->dev;
1051         struct nvme_queue *nvmeq;
1052         struct nvme_user_io io;
1053         struct nvme_command c;
1054         unsigned length;
1055         int nents, status;
1056         struct scatterlist *sg;
1057         struct nvme_prps *prps;
1058
1059         if (copy_from_user(&io, uio, sizeof(io)))
1060                 return -EFAULT;
1061         length = (io.nblocks + 1) << ns->lba_shift;
1062
1063         switch (io.opcode) {
1064         case nvme_cmd_write:
1065         case nvme_cmd_read:
1066                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1067                                                                 length, &sg);
1068         default:
1069                 return -EFAULT;
1070         }
1071
1072         if (nents < 0)
1073                 return nents;
1074
1075         memset(&c, 0, sizeof(c));
1076         c.rw.opcode = io.opcode;
1077         c.rw.flags = io.flags;
1078         c.rw.nsid = cpu_to_le32(ns->ns_id);
1079         c.rw.slba = cpu_to_le64(io.slba);
1080         c.rw.length = cpu_to_le16(io.nblocks);
1081         c.rw.control = cpu_to_le16(io.control);
1082         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1083         c.rw.reftag = io.reftag;
1084         c.rw.apptag = io.apptag;
1085         c.rw.appmask = io.appmask;
1086         /* XXX: metadata */
1087         prps = nvme_setup_prps(dev, &c.common, sg, length);
1088
1089         nvmeq = get_nvmeq(ns);
1090         /*
1091          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1092          * disabled.  We may be preempted at any point, and be rescheduled
1093          * to a different CPU.  That will cause cacheline bouncing, but no
1094          * additional races since q_lock already protects against other CPUs.
1095          */
1096         put_nvmeq(nvmeq);
1097         status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1098
1099         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1100         nvme_free_prps(dev, prps);
1101         return status;
1102 }
1103
1104 static int nvme_download_firmware(struct nvme_ns *ns,
1105                                                 struct nvme_dlfw __user *udlfw)
1106 {
1107         struct nvme_dev *dev = ns->dev;
1108         struct nvme_dlfw dlfw;
1109         struct nvme_command c;
1110         int nents, status;
1111         struct scatterlist *sg;
1112         struct nvme_prps *prps;
1113
1114         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1115                 return -EFAULT;
1116         if (dlfw.length >= (1 << 30))
1117                 return -EINVAL;
1118
1119         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1120         if (nents < 0)
1121                 return nents;
1122
1123         memset(&c, 0, sizeof(c));
1124         c.dlfw.opcode = nvme_admin_download_fw;
1125         c.dlfw.numd = cpu_to_le32(dlfw.length);
1126         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1127         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1128
1129         status = nvme_submit_admin_cmd(dev, &c, NULL);
1130         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1131         nvme_free_prps(dev, prps);
1132         return status;
1133 }
1134
1135 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1136 {
1137         struct nvme_dev *dev = ns->dev;
1138         struct nvme_command c;
1139
1140         memset(&c, 0, sizeof(c));
1141         c.common.opcode = nvme_admin_activate_fw;
1142         c.common.rsvd10[0] = cpu_to_le32(arg);
1143
1144         return nvme_submit_admin_cmd(dev, &c, NULL);
1145 }
1146
1147 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1148                                                         unsigned long arg)
1149 {
1150         struct nvme_ns *ns = bdev->bd_disk->private_data;
1151
1152         switch (cmd) {
1153         case NVME_IOCTL_IDENTIFY_NS:
1154                 return nvme_identify(ns, arg, 0);
1155         case NVME_IOCTL_IDENTIFY_CTRL:
1156                 return nvme_identify(ns, arg, 1);
1157         case NVME_IOCTL_GET_RANGE_TYPE:
1158                 return nvme_get_range_type(ns, arg);
1159         case NVME_IOCTL_SUBMIT_IO:
1160                 return nvme_submit_io(ns, (void __user *)arg);
1161         case NVME_IOCTL_DOWNLOAD_FW:
1162                 return nvme_download_firmware(ns, (void __user *)arg);
1163         case NVME_IOCTL_ACTIVATE_FW:
1164                 return nvme_activate_firmware(ns, arg);
1165         default:
1166                 return -ENOTTY;
1167         }
1168 }
1169
1170 static const struct block_device_operations nvme_fops = {
1171         .owner          = THIS_MODULE,
1172         .ioctl          = nvme_ioctl,
1173         .compat_ioctl   = nvme_ioctl,
1174 };
1175
1176 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1177 {
1178         int depth = nvmeq->q_depth - 1;
1179         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1180         unsigned long now = jiffies;
1181         int cmdid;
1182
1183         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1184                 unsigned long data;
1185                 void *ptr;
1186                 unsigned char handler;
1187                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1188
1189                 if (!time_after(now, info[cmdid].timeout))
1190                         continue;
1191                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1192                 data = cancel_cmdid(nvmeq, cmdid);
1193                 handler = data & 3;
1194                 ptr = (void *)(data & ~3UL);
1195                 nvme_completions[handler](nvmeq, ptr, &cqe);
1196         }
1197 }
1198
1199 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1200 {
1201         while (bio_list_peek(&nvmeq->sq_cong)) {
1202                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1203                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1204                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1205                         bio_list_add_head(&nvmeq->sq_cong, bio);
1206                         break;
1207                 }
1208                 if (bio_list_empty(&nvmeq->sq_cong))
1209                         remove_wait_queue(&nvmeq->sq_full,
1210                                                         &nvmeq->sq_cong_wait);
1211         }
1212 }
1213
1214 static int nvme_kthread(void *data)
1215 {
1216         struct nvme_dev *dev;
1217
1218         while (!kthread_should_stop()) {
1219                 __set_current_state(TASK_RUNNING);
1220                 spin_lock(&dev_list_lock);
1221                 list_for_each_entry(dev, &dev_list, node) {
1222                         int i;
1223                         for (i = 0; i < dev->queue_count; i++) {
1224                                 struct nvme_queue *nvmeq = dev->queues[i];
1225                                 if (!nvmeq)
1226                                         continue;
1227                                 spin_lock_irq(&nvmeq->q_lock);
1228                                 if (nvme_process_cq(nvmeq))
1229                                         printk("process_cq did something\n");
1230                                 nvme_timeout_ios(nvmeq);
1231                                 nvme_resubmit_bios(nvmeq);
1232                                 spin_unlock_irq(&nvmeq->q_lock);
1233                         }
1234                 }
1235                 spin_unlock(&dev_list_lock);
1236                 set_current_state(TASK_INTERRUPTIBLE);
1237                 schedule_timeout(HZ);
1238         }
1239         return 0;
1240 }
1241
1242 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1243                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1244 {
1245         struct nvme_ns *ns;
1246         struct gendisk *disk;
1247         int lbaf;
1248
1249         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1250                 return NULL;
1251
1252         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1253         if (!ns)
1254                 return NULL;
1255         ns->queue = blk_alloc_queue(GFP_KERNEL);
1256         if (!ns->queue)
1257                 goto out_free_ns;
1258         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1259                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1260         blk_queue_make_request(ns->queue, nvme_make_request);
1261         ns->dev = dev;
1262         ns->queue->queuedata = ns;
1263
1264         disk = alloc_disk(NVME_MINORS);
1265         if (!disk)
1266                 goto out_free_queue;
1267         ns->ns_id = index;
1268         ns->disk = disk;
1269         lbaf = id->flbas & 0xf;
1270         ns->lba_shift = id->lbaf[lbaf].ds;
1271
1272         disk->major = nvme_major;
1273         disk->minors = NVME_MINORS;
1274         disk->first_minor = NVME_MINORS * index;
1275         disk->fops = &nvme_fops;
1276         disk->private_data = ns;
1277         disk->queue = ns->queue;
1278         disk->driverfs_dev = &dev->pci_dev->dev;
1279         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1280         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1281
1282         return ns;
1283
1284  out_free_queue:
1285         blk_cleanup_queue(ns->queue);
1286  out_free_ns:
1287         kfree(ns);
1288         return NULL;
1289 }
1290
1291 static void nvme_ns_free(struct nvme_ns *ns)
1292 {
1293         put_disk(ns->disk);
1294         blk_cleanup_queue(ns->queue);
1295         kfree(ns);
1296 }
1297
1298 static int set_queue_count(struct nvme_dev *dev, int count)
1299 {
1300         int status;
1301         u32 result;
1302         struct nvme_command c;
1303         u32 q_count = (count - 1) | ((count - 1) << 16);
1304
1305         memset(&c, 0, sizeof(c));
1306         c.features.opcode = nvme_admin_get_features;
1307         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1308         c.features.dword11 = cpu_to_le32(q_count);
1309
1310         status = nvme_submit_admin_cmd(dev, &c, &result);
1311         if (status)
1312                 return -EIO;
1313         return min(result & 0xffff, result >> 16) + 1;
1314 }
1315
1316 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1317 {
1318         int result, cpu, i, nr_io_queues;
1319
1320         nr_io_queues = num_online_cpus();
1321         result = set_queue_count(dev, nr_io_queues);
1322         if (result < 0)
1323                 return result;
1324         if (result < nr_io_queues)
1325                 nr_io_queues = result;
1326
1327         /* Deregister the admin queue's interrupt */
1328         free_irq(dev->entry[0].vector, dev->queues[0]);
1329
1330         for (i = 0; i < nr_io_queues; i++)
1331                 dev->entry[i].entry = i;
1332         for (;;) {
1333                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1334                                                                 nr_io_queues);
1335                 if (result == 0) {
1336                         break;
1337                 } else if (result > 0) {
1338                         nr_io_queues = result;
1339                         continue;
1340                 } else {
1341                         nr_io_queues = 1;
1342                         break;
1343                 }
1344         }
1345
1346         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1347         /* XXX: handle failure here */
1348
1349         cpu = cpumask_first(cpu_online_mask);
1350         for (i = 0; i < nr_io_queues; i++) {
1351                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1352                 cpu = cpumask_next(cpu, cpu_online_mask);
1353         }
1354
1355         for (i = 0; i < nr_io_queues; i++) {
1356                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1357                                                         NVME_Q_DEPTH, i);
1358                 if (!dev->queues[i + 1])
1359                         return -ENOMEM;
1360                 dev->queue_count++;
1361         }
1362
1363         for (; i < num_possible_cpus(); i++) {
1364                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1365                 dev->queues[i + 1] = dev->queues[target + 1];
1366         }
1367
1368         return 0;
1369 }
1370
1371 static void nvme_free_queues(struct nvme_dev *dev)
1372 {
1373         int i;
1374
1375         for (i = dev->queue_count - 1; i >= 0; i--)
1376                 nvme_free_queue(dev, i);
1377 }
1378
1379 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1380 {
1381         int res, nn, i;
1382         struct nvme_ns *ns, *next;
1383         struct nvme_id_ctrl *ctrl;
1384         void *id;
1385         dma_addr_t dma_addr;
1386         struct nvme_command cid, crt;
1387
1388         res = nvme_setup_io_queues(dev);
1389         if (res)
1390                 return res;
1391
1392         /* XXX: Switch to a SG list once prp2 works */
1393         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1394                                                                 GFP_KERNEL);
1395
1396         memset(&cid, 0, sizeof(cid));
1397         cid.identify.opcode = nvme_admin_identify;
1398         cid.identify.nsid = 0;
1399         cid.identify.prp1 = cpu_to_le64(dma_addr);
1400         cid.identify.cns = cpu_to_le32(1);
1401
1402         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1403         if (res) {
1404                 res = -EIO;
1405                 goto out_free;
1406         }
1407
1408         ctrl = id;
1409         nn = le32_to_cpup(&ctrl->nn);
1410         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1411         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1412         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1413
1414         cid.identify.cns = 0;
1415         memset(&crt, 0, sizeof(crt));
1416         crt.features.opcode = nvme_admin_get_features;
1417         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1418         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1419
1420         for (i = 0; i <= nn; i++) {
1421                 cid.identify.nsid = cpu_to_le32(i);
1422                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1423                 if (res)
1424                         continue;
1425
1426                 if (((struct nvme_id_ns *)id)->ncap == 0)
1427                         continue;
1428
1429                 crt.features.nsid = cpu_to_le32(i);
1430                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1431                 if (res)
1432                         continue;
1433
1434                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1435                 if (ns)
1436                         list_add_tail(&ns->list, &dev->namespaces);
1437         }
1438         list_for_each_entry(ns, &dev->namespaces, list)
1439                 add_disk(ns->disk);
1440
1441         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1442         return 0;
1443
1444  out_free:
1445         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1446                 list_del(&ns->list);
1447                 nvme_ns_free(ns);
1448         }
1449
1450         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1451         return res;
1452 }
1453
1454 static int nvme_dev_remove(struct nvme_dev *dev)
1455 {
1456         struct nvme_ns *ns, *next;
1457
1458         spin_lock(&dev_list_lock);
1459         list_del(&dev->node);
1460         spin_unlock(&dev_list_lock);
1461
1462         /* TODO: wait all I/O finished or cancel them */
1463
1464         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1465                 list_del(&ns->list);
1466                 del_gendisk(ns->disk);
1467                 nvme_ns_free(ns);
1468         }
1469
1470         nvme_free_queues(dev);
1471
1472         return 0;
1473 }
1474
1475 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1476 {
1477         struct device *dmadev = &dev->pci_dev->dev;
1478         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1479                                                 PAGE_SIZE, PAGE_SIZE, 0);
1480         if (!dev->prp_page_pool)
1481                 return -ENOMEM;
1482
1483         /* Optimisation for I/Os between 4k and 128k */
1484         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1485                                                 256, 256, 0);
1486         if (!dev->prp_small_pool) {
1487                 dma_pool_destroy(dev->prp_page_pool);
1488                 return -ENOMEM;
1489         }
1490         return 0;
1491 }
1492
1493 static void nvme_release_prp_pools(struct nvme_dev *dev)
1494 {
1495         dma_pool_destroy(dev->prp_page_pool);
1496         dma_pool_destroy(dev->prp_small_pool);
1497 }
1498
1499 /* XXX: Use an ida or something to let remove / add work correctly */
1500 static void nvme_set_instance(struct nvme_dev *dev)
1501 {
1502         static int instance;
1503         dev->instance = instance++;
1504 }
1505
1506 static void nvme_release_instance(struct nvme_dev *dev)
1507 {
1508 }
1509
1510 static int __devinit nvme_probe(struct pci_dev *pdev,
1511                                                 const struct pci_device_id *id)
1512 {
1513         int bars, result = -ENOMEM;
1514         struct nvme_dev *dev;
1515
1516         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1517         if (!dev)
1518                 return -ENOMEM;
1519         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1520                                                                 GFP_KERNEL);
1521         if (!dev->entry)
1522                 goto free;
1523         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1524                                                                 GFP_KERNEL);
1525         if (!dev->queues)
1526                 goto free;
1527
1528         if (pci_enable_device_mem(pdev))
1529                 goto free;
1530         pci_set_master(pdev);
1531         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1532         if (pci_request_selected_regions(pdev, bars, "nvme"))
1533                 goto disable;
1534
1535         INIT_LIST_HEAD(&dev->namespaces);
1536         dev->pci_dev = pdev;
1537         pci_set_drvdata(pdev, dev);
1538         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1539         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1540         nvme_set_instance(dev);
1541         dev->entry[0].vector = pdev->irq;
1542
1543         result = nvme_setup_prp_pools(dev);
1544         if (result)
1545                 goto disable_msix;
1546
1547         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1548         if (!dev->bar) {
1549                 result = -ENOMEM;
1550                 goto disable_msix;
1551         }
1552
1553         result = nvme_configure_admin_queue(dev);
1554         if (result)
1555                 goto unmap;
1556         dev->queue_count++;
1557
1558         spin_lock(&dev_list_lock);
1559         list_add(&dev->node, &dev_list);
1560         spin_unlock(&dev_list_lock);
1561
1562         result = nvme_dev_add(dev);
1563         if (result)
1564                 goto delete;
1565
1566         return 0;
1567
1568  delete:
1569         spin_lock(&dev_list_lock);
1570         list_del(&dev->node);
1571         spin_unlock(&dev_list_lock);
1572
1573         nvme_free_queues(dev);
1574  unmap:
1575         iounmap(dev->bar);
1576  disable_msix:
1577         pci_disable_msix(pdev);
1578         nvme_release_instance(dev);
1579         nvme_release_prp_pools(dev);
1580  disable:
1581         pci_disable_device(pdev);
1582         pci_release_regions(pdev);
1583  free:
1584         kfree(dev->queues);
1585         kfree(dev->entry);
1586         kfree(dev);
1587         return result;
1588 }
1589
1590 static void __devexit nvme_remove(struct pci_dev *pdev)
1591 {
1592         struct nvme_dev *dev = pci_get_drvdata(pdev);
1593         nvme_dev_remove(dev);
1594         pci_disable_msix(pdev);
1595         iounmap(dev->bar);
1596         nvme_release_instance(dev);
1597         nvme_release_prp_pools(dev);
1598         pci_disable_device(pdev);
1599         pci_release_regions(pdev);
1600         kfree(dev->queues);
1601         kfree(dev->entry);
1602         kfree(dev);
1603 }
1604
1605 /* These functions are yet to be implemented */
1606 #define nvme_error_detected NULL
1607 #define nvme_dump_registers NULL
1608 #define nvme_link_reset NULL
1609 #define nvme_slot_reset NULL
1610 #define nvme_error_resume NULL
1611 #define nvme_suspend NULL
1612 #define nvme_resume NULL
1613
1614 static struct pci_error_handlers nvme_err_handler = {
1615         .error_detected = nvme_error_detected,
1616         .mmio_enabled   = nvme_dump_registers,
1617         .link_reset     = nvme_link_reset,
1618         .slot_reset     = nvme_slot_reset,
1619         .resume         = nvme_error_resume,
1620 };
1621
1622 /* Move to pci_ids.h later */
1623 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1624
1625 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1626         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1627         { 0, }
1628 };
1629 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1630
1631 static struct pci_driver nvme_driver = {
1632         .name           = "nvme",
1633         .id_table       = nvme_id_table,
1634         .probe          = nvme_probe,
1635         .remove         = __devexit_p(nvme_remove),
1636         .suspend        = nvme_suspend,
1637         .resume         = nvme_resume,
1638         .err_handler    = &nvme_err_handler,
1639 };
1640
1641 static int __init nvme_init(void)
1642 {
1643         int result = -EBUSY;
1644
1645         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1646         if (IS_ERR(nvme_thread))
1647                 return PTR_ERR(nvme_thread);
1648
1649         nvme_major = register_blkdev(nvme_major, "nvme");
1650         if (nvme_major <= 0)
1651                 goto kill_kthread;
1652
1653         result = pci_register_driver(&nvme_driver);
1654         if (result)
1655                 goto unregister_blkdev;
1656         return 0;
1657
1658  unregister_blkdev:
1659         unregister_blkdev(nvme_major, "nvme");
1660  kill_kthread:
1661         kthread_stop(nvme_thread);
1662         return result;
1663 }
1664
1665 static void __exit nvme_exit(void)
1666 {
1667         pci_unregister_driver(&nvme_driver);
1668         unregister_blkdev(nvme_major, "nvme");
1669         kthread_stop(nvme_thread);
1670 }
1671
1672 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1673 MODULE_LICENSE("GPL");
1674 MODULE_VERSION("0.5");
1675 module_init(nvme_init);
1676 module_exit(nvme_exit);