drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/poison.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/version.h>
  40
  41 #define NVME_Q_DEPTH 1024
  42 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  43 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  44 #define NVME_MINORS 64
  45 #define IO_TIMEOUT      (5 * HZ)
  46 #define ADMIN_TIMEOUT   (60 * HZ)
  47
  48 static int nvme_major;
  49 module_param(nvme_major, int, 0);
  50
  51 static int use_threaded_interrupts;
  52 module_param(use_threaded_interrupts, int, 0);
  53
  54 static DEFINE_SPINLOCK(dev_list_lock);
  55 static LIST_HEAD(dev_list);
  56 static struct task_struct *nvme_thread;
  57
  58 /*
  59  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  60  */
  61 struct nvme_dev {
  62         struct list_head node;
  63         struct nvme_queue **queues;
  64         u32 __iomem *dbs;
  65         struct pci_dev *pci_dev;
  66         struct dma_pool *prp_page_pool;
  67         struct dma_pool *prp_small_pool;
  68         int instance;
  69         int queue_count;
  70         u32 ctrl_config;
  71         struct msix_entry *entry;
  72         struct nvme_bar __iomem *bar;
  73         struct list_head namespaces;
  74         char serial[20];
  75         char model[40];
  76         char firmware_rev[8];
  77 };
  78
  79 /*
  80  * An NVM Express namespace is equivalent to a SCSI LUN
  81  */
  82 struct nvme_ns {
  83         struct list_head list;
  84
  85         struct nvme_dev *dev;
  86         struct request_queue *queue;
  87         struct gendisk *disk;
  88
  89         int ns_id;
  90         int lba_shift;
  91 };
  92
  93 /*
  94  * An NVM Express queue.  Each device has at least two (one for admin
  95  * commands and one for I/O commands).
  96  */
  97 struct nvme_queue {
  98         struct device *q_dmadev;
  99         struct nvme_dev *dev;
 100         spinlock_t q_lock;
 101         struct nvme_command *sq_cmds;
 102         volatile struct nvme_completion *cqes;
 103         dma_addr_t sq_dma_addr;
 104         dma_addr_t cq_dma_addr;
 105         wait_queue_head_t sq_full;
 106         wait_queue_t sq_cong_wait;
 107         struct bio_list sq_cong;
 108         u32 __iomem *q_db;
 109         u16 q_depth;
 110         u16 cq_vector;
 111         u16 sq_head;
 112         u16 sq_tail;
 113         u16 cq_head;
 114         u16 cq_phase;
 115         unsigned long cmdid_data[];
 116 };
 117
 118 /*
 119  * Check we didin't inadvertently grow the command struct
 120  */
 121 static inline void _nvme_check_size(void)
 122 {
 123         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 132 }
 133
 134 struct nvme_cmd_info {
 135         unsigned long ctx;
 136         unsigned long timeout;
 137 };
 138
 139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 140 {
 141         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 142 }
 143
 144 /**
 145  * alloc_cmdid() - Allocate a Command ID
 146  * @nvmeq: The queue that will be used for this command
 147  * @ctx: A pointer that will be passed to the handler
 148  * @handler: The ID of the handler to call
 149  *
 150  * Allocate a Command ID for a queue.  The data passed in will
 151  * be passed to the completion handler.  This is implemented by using
 152  * the bottom two bits of the ctx pointer to store the handler ID.
 153  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 154  * We can change this if it becomes a problem.
 155  */
 156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 157                                                         unsigned timeout)
 158 {
 159         int depth = nvmeq->q_depth - 1;
 160         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 161         int cmdid;
 162
 163         BUG_ON((unsigned long)ctx & 3);
 164
 165         do {
 166                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 167                 if (cmdid >= depth)
 168                         return -EBUSY;
 169         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 170
 171         info[cmdid].ctx = (unsigned long)ctx | handler;
 172         info[cmdid].timeout = jiffies + timeout;
 173         return cmdid;
 174 }
 175
 176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 177                                                 int handler, unsigned timeout)
 178 {
 179         int cmdid;
 180         wait_event_killable(nvmeq->sq_full,
 181                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 182         return (cmdid < 0) ? -EINTR : cmdid;
 183 }
 184
 185 /*
 186  * If you need more than four handlers, you'll need to change how
 187  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 188  * CMD_CTX value instead, if that works for your situation.
 189  */
 190 enum {
 191         sync_completion_id = 0,
 192         bio_completion_id,
 193 };
 194
 195 /* Special values must be a multiple of 4, and less than 0x1000 */
 196 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 197 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 198 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 199 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 200 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 201
 202 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 203 {
 204         unsigned long data;
 205         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 206
 207         if (cmdid >= nvmeq->q_depth)
 208                 return CMD_CTX_INVALID;
 209         data = info[cmdid].ctx;
 210         info[cmdid].ctx = CMD_CTX_COMPLETED;
 211         clear_bit(cmdid, nvmeq->cmdid_data);
 212         wake_up(&nvmeq->sq_full);
 213         return data;
 214 }
 215
 216 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 217 {
 218         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 219         info[cmdid].ctx = CMD_CTX_CANCELLED;
 220 }
 221
 222 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 223 {
 224         return ns->dev->queues[get_cpu() + 1];
 225 }
 226
 227 static void put_nvmeq(struct nvme_queue *nvmeq)
 228 {
 229         put_cpu();
 230 }
 231
 232 /**
 233  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 234  * @nvmeq: The queue to use
 235  * @cmd: The command to send
 236  *
 237  * Safe to use from interrupt context
 238  */
 239 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 240 {
 241         unsigned long flags;
 242         u16 tail;
 243         spin_lock_irqsave(&nvmeq->q_lock, flags);
 244         tail = nvmeq->sq_tail;
 245         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 246         if (++tail == nvmeq->q_depth)
 247                 tail = 0;
 248         writel(tail, nvmeq->q_db);
 249         nvmeq->sq_tail = tail;
 250         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 251
 252         return 0;
 253 }
 254
 255 struct nvme_prps {
 256         int npages;
 257         dma_addr_t first_dma;
 258         __le64 *list[0];
 259 };
 260
 261 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 262 {
 263         const int last_prp = PAGE_SIZE / 8 - 1;
 264         int i;
 265         dma_addr_t prp_dma;
 266
 267         if (!prps)
 268                 return;
 269
 270         prp_dma = prps->first_dma;
 271
 272         if (prps->npages == 0)
 273                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 274         for (i = 0; i < prps->npages; i++) {
 275                 __le64 *prp_list = prps->list[i];
 276                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 277                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 278                 prp_dma = next_prp_dma;
 279         }
 280         kfree(prps);
 281 }
 282
 283 struct nvme_bio {
 284         struct bio *bio;
 285         int nents;
 286         struct nvme_prps *prps;
 287         struct scatterlist sg[0];
 288 };
 289
 290 /* XXX: use a mempool */
 291 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 292 {
 293         return kzalloc(sizeof(struct nvme_bio) +
 294                         sizeof(struct scatterlist) * nseg, gfp);
 295 }
 296
 297 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 298 {
 299         nvme_free_prps(nvmeq->dev, nbio->prps);
 300         kfree(nbio);
 301 }
 302
 303 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 304                                                 struct nvme_completion *cqe)
 305 {
 306         struct nvme_bio *nbio = ctx;
 307         struct bio *bio = nbio->bio;
 308         u16 status = le16_to_cpup(&cqe->status) >> 1;
 309
 310         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 311                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 312         free_nbio(nvmeq, nbio);
 313         if (status)
 314                 bio_endio(bio, -EIO);
 315         if (bio->bi_vcnt > bio->bi_idx) {
 316                 bio_list_add(&nvmeq->sq_cong, bio);
 317                 wake_up_process(nvme_thread);
 318         } else {
 319                 bio_endio(bio, 0);
 320         }
 321 }
 322
 323 /* length is in bytes */
 324 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 325                                         struct nvme_common_command *cmd,
 326                                         struct scatterlist *sg, int length)
 327 {
 328         struct dma_pool *pool;
 329         int dma_len = sg_dma_len(sg);
 330         u64 dma_addr = sg_dma_address(sg);
 331         int offset = offset_in_page(dma_addr);
 332         __le64 *prp_list;
 333         dma_addr_t prp_dma;
 334         int nprps, npages, i, prp_page;
 335         struct nvme_prps *prps = NULL;
 336
 337         cmd->prp1 = cpu_to_le64(dma_addr);
 338         length -= (PAGE_SIZE - offset);
 339         if (length <= 0)
 340                 return prps;
 341
 342         dma_len -= (PAGE_SIZE - offset);
 343         if (dma_len) {
 344                 dma_addr += (PAGE_SIZE - offset);
 345         } else {
 346                 sg = sg_next(sg);
 347                 dma_addr = sg_dma_address(sg);
 348                 dma_len = sg_dma_len(sg);
 349         }
 350
 351         if (length <= PAGE_SIZE) {
 352                 cmd->prp2 = cpu_to_le64(dma_addr);
 353                 return prps;
 354         }
 355
 356         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 357         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 358         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 359         prp_page = 0;
 360         if (nprps <= (256 / 8)) {
 361                 pool = dev->prp_small_pool;
 362                 prps->npages = 0;
 363         } else {
 364                 pool = dev->prp_page_pool;
 365                 prps->npages = npages;
 366         }
 367
 368         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 369         prps->list[prp_page++] = prp_list;
 370         prps->first_dma = prp_dma;
 371         cmd->prp2 = cpu_to_le64(prp_dma);
 372         i = 0;
 373         for (;;) {
 374                 if (i == PAGE_SIZE / 8) {
 375                         __le64 *old_prp_list = prp_list;
 376                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 377                         prps->list[prp_page++] = prp_list;
 378                         prp_list[0] = old_prp_list[i - 1];
 379                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 380                         i = 1;
 381                 }
 382                 prp_list[i++] = cpu_to_le64(dma_addr);
 383                 dma_len -= PAGE_SIZE;
 384                 dma_addr += PAGE_SIZE;
 385                 length -= PAGE_SIZE;
 386                 if (length <= 0)
 387                         break;
 388                 if (dma_len > 0)
 389                         continue;
 390                 BUG_ON(dma_len < 0);
 391                 sg = sg_next(sg);
 392                 dma_addr = sg_dma_address(sg);
 393                 dma_len = sg_dma_len(sg);
 394         }
 395
 396         return prps;
 397 }
 398
 399 /* NVMe scatterlists require no holes in the virtual address */
 400 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 401                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 402
 403 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 404                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 405 {
 406         struct bio_vec *bvec, *bvprv = NULL;
 407         struct scatterlist *sg = NULL;
 408         int i, old_idx, length = 0, nsegs = 0;
 409
 410         sg_init_table(nbio->sg, psegs);
 411         old_idx = bio->bi_idx;
 412         bio_for_each_segment(bvec, bio, i) {
 413                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 414                         sg->length += bvec->bv_len;
 415                 } else {
 416                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 417                                 break;
 418                         sg = sg ? sg + 1 : nbio->sg;
 419                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 420                                                         bvec->bv_offset);
 421                         nsegs++;
 422                 }
 423                 length += bvec->bv_len;
 424                 bvprv = bvec;
 425         }
 426         bio->bi_idx = i;
 427         nbio->nents = nsegs;
 428         sg_mark_end(sg);
 429         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 430                 bio->bi_idx = old_idx;
 431                 return -ENOMEM;
 432         }
 433         return length;
 434 }
 435
 436 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 437                                                                 int cmdid)
 438 {
 439         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 440
 441         memset(cmnd, 0, sizeof(*cmnd));
 442         cmnd->common.opcode = nvme_cmd_flush;
 443         cmnd->common.command_id = cmdid;
 444         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 445
 446         if (++nvmeq->sq_tail == nvmeq->q_depth)
 447                 nvmeq->sq_tail = 0;
 448         writel(nvmeq->sq_tail, nvmeq->q_db);
 449
 450         return 0;
 451 }
 452
 453 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 454 {
 455         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 456                                                 sync_completion_id, IO_TIMEOUT);
 457         if (unlikely(cmdid < 0))
 458                 return cmdid;
 459
 460         return nvme_submit_flush(nvmeq, ns, cmdid);
 461 }
 462
 463 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 464                                                                 struct bio *bio)
 465 {
 466         struct nvme_command *cmnd;
 467         struct nvme_bio *nbio;
 468         enum dma_data_direction dma_dir;
 469         int cmdid, length, result = -ENOMEM;
 470         u16 control;
 471         u32 dsmgmt;
 472         int psegs = bio_phys_segments(ns->queue, bio);
 473
 474         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 475                 result = nvme_submit_flush_data(nvmeq, ns);
 476                 if (result)
 477                         return result;
 478         }
 479
 480         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 481         if (!nbio)
 482                 goto nomem;
 483         nbio->bio = bio;
 484
 485         result = -EBUSY;
 486         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 487         if (unlikely(cmdid < 0))
 488                 goto free_nbio;
 489
 490         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 491                 return nvme_submit_flush(nvmeq, ns, cmdid);
 492
 493         control = 0;
 494         if (bio->bi_rw & REQ_FUA)
 495                 control |= NVME_RW_FUA;
 496         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 497                 control |= NVME_RW_LR;
 498
 499         dsmgmt = 0;
 500         if (bio->bi_rw & REQ_RAHEAD)
 501                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 502
 503         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 504
 505         memset(cmnd, 0, sizeof(*cmnd));
 506         if (bio_data_dir(bio)) {
 507                 cmnd->rw.opcode = nvme_cmd_write;
 508                 dma_dir = DMA_TO_DEVICE;
 509         } else {
 510                 cmnd->rw.opcode = nvme_cmd_read;
 511                 dma_dir = DMA_FROM_DEVICE;
 512         }
 513
 514         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 515         if (result < 0)
 516                 goto free_nbio;
 517         length = result;
 518
 519         cmnd->rw.command_id = cmdid;
 520         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 521         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 522                                                                 length);
 523         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 524         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 525         cmnd->rw.control = cpu_to_le16(control);
 526         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 527
 528         bio->bi_sector += length >> 9;
 529
 530         if (++nvmeq->sq_tail == nvmeq->q_depth)
 531                 nvmeq->sq_tail = 0;
 532         writel(nvmeq->sq_tail, nvmeq->q_db);
 533
 534         return 0;
 535
 536  free_nbio:
 537         free_nbio(nvmeq, nbio);
 538  nomem:
 539         return result;
 540 }
 541
 542 /*
 543  * NB: return value of non-zero would mean that we were a stacking driver.
 544  * make_request must always succeed.
 545  */
 546 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 547 {
 548         struct nvme_ns *ns = q->queuedata;
 549         struct nvme_queue *nvmeq = get_nvmeq(ns);
 550         int result = -EBUSY;
 551
 552         spin_lock_irq(&nvmeq->q_lock);
 553         if (bio_list_empty(&nvmeq->sq_cong))
 554                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 555         if (unlikely(result)) {
 556                 if (bio_list_empty(&nvmeq->sq_cong))
 557                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 558                 bio_list_add(&nvmeq->sq_cong, bio);
 559         }
 560
 561         spin_unlock_irq(&nvmeq->q_lock);
 562         put_nvmeq(nvmeq);
 563
 564         return 0;
 565 }
 566
 567 struct sync_cmd_info {
 568         struct task_struct *task;
 569         u32 result;
 570         int status;
 571 };
 572
 573 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 574                                                 struct nvme_completion *cqe)
 575 {
 576         struct sync_cmd_info *cmdinfo = ctx;
 577         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 578                 return;
 579         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 580                 return;
 581         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 582                 dev_warn(nvmeq->q_dmadev,
 583                                 "completed id %d twice on queue %d\n",
 584                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 585                 return;
 586         }
 587         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 588                 dev_warn(nvmeq->q_dmadev,
 589                                 "invalid id %d completed on queue %d\n",
 590                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 591                 return;
 592         }
 593         cmdinfo->result = le32_to_cpup(&cqe->result);
 594         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 595         wake_up_process(cmdinfo->task);
 596 }
 597
 598 typedef void (*completion_fn)(struct nvme_queue *, void *,
 599                                                 struct nvme_completion *);
 600
 601 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 602 {
 603         u16 head, phase;
 604
 605         static const completion_fn completions[4] = {
 606                 [sync_completion_id] = sync_completion,
 607                 [bio_completion_id]  = bio_completion,
 608         };
 609
 610         head = nvmeq->cq_head;
 611         phase = nvmeq->cq_phase;
 612
 613         for (;;) {
 614                 unsigned long data;
 615                 void *ptr;
 616                 unsigned char handler;
 617                 struct nvme_completion cqe = nvmeq->cqes[head];
 618                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 619                         break;
 620                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 621                 if (++head == nvmeq->q_depth) {
 622                         head = 0;
 623                         phase = !phase;
 624                 }
 625
 626                 data = free_cmdid(nvmeq, cqe.command_id);
 627                 handler = data & 3;
 628                 ptr = (void *)(data & ~3UL);
 629                 completions[handler](nvmeq, ptr, &cqe);
 630         }
 631
 632         /* If the controller ignores the cq head doorbell and continuously
 633          * writes to the queue, it is theoretically possible to wrap around
 634          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 635          * requires that 0.1% of your interrupts are handled, so this isn't
 636          * a big problem.
 637          */
 638         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 639                 return IRQ_NONE;
 640
 641         writel(head, nvmeq->q_db + 1);
 642         nvmeq->cq_head = head;
 643         nvmeq->cq_phase = phase;
 644
 645         return IRQ_HANDLED;
 646 }
 647
 648 static irqreturn_t nvme_irq(int irq, void *data)
 649 {
 650         irqreturn_t result;
 651         struct nvme_queue *nvmeq = data;
 652         spin_lock(&nvmeq->q_lock);
 653         result = nvme_process_cq(nvmeq);
 654         spin_unlock(&nvmeq->q_lock);
 655         return result;
 656 }
 657
 658 static irqreturn_t nvme_irq_check(int irq, void *data)
 659 {
 660         struct nvme_queue *nvmeq = data;
 661         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 662         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 663                 return IRQ_NONE;
 664         return IRQ_WAKE_THREAD;
 665 }
 666
 667 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 668 {
 669         spin_lock_irq(&nvmeq->q_lock);
 670         cancel_cmdid_data(nvmeq, cmdid);
 671         spin_unlock_irq(&nvmeq->q_lock);
 672 }
 673
 674 /*
 675  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 676  * if the result is positive, it's an NVM Express status code
 677  */
 678 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 679                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 680 {
 681         int cmdid;
 682         struct sync_cmd_info cmdinfo;
 683
 684         cmdinfo.task = current;
 685         cmdinfo.status = -EINTR;
 686
 687         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 688                                                                 timeout);
 689         if (cmdid < 0)
 690                 return cmdid;
 691         cmd->common.command_id = cmdid;
 692
 693         set_current_state(TASK_KILLABLE);
 694         nvme_submit_cmd(nvmeq, cmd);
 695         schedule();
 696
 697         if (cmdinfo.status == -EINTR) {
 698                 nvme_abort_command(nvmeq, cmdid);
 699                 return -EINTR;
 700         }
 701
 702         if (result)
 703                 *result = cmdinfo.result;
 704
 705         return cmdinfo.status;
 706 }
 707
 708 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 709                                                                 u32 *result)
 710 {
 711         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 712 }
 713
 714 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 715 {
 716         int status;
 717         struct nvme_command c;
 718
 719         memset(&c, 0, sizeof(c));
 720         c.delete_queue.opcode = opcode;
 721         c.delete_queue.qid = cpu_to_le16(id);
 722
 723         status = nvme_submit_admin_cmd(dev, &c, NULL);
 724         if (status)
 725                 return -EIO;
 726         return 0;
 727 }
 728
 729 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 730                                                 struct nvme_queue *nvmeq)
 731 {
 732         int status;
 733         struct nvme_command c;
 734         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 735
 736         memset(&c, 0, sizeof(c));
 737         c.create_cq.opcode = nvme_admin_create_cq;
 738         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 739         c.create_cq.cqid = cpu_to_le16(qid);
 740         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 741         c.create_cq.cq_flags = cpu_to_le16(flags);
 742         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 743
 744         status = nvme_submit_admin_cmd(dev, &c, NULL);
 745         if (status)
 746                 return -EIO;
 747         return 0;
 748 }
 749
 750 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 751                                                 struct nvme_queue *nvmeq)
 752 {
 753         int status;
 754         struct nvme_command c;
 755         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 756
 757         memset(&c, 0, sizeof(c));
 758         c.create_sq.opcode = nvme_admin_create_sq;
 759         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 760         c.create_sq.sqid = cpu_to_le16(qid);
 761         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 762         c.create_sq.sq_flags = cpu_to_le16(flags);
 763         c.create_sq.cqid = cpu_to_le16(qid);
 764
 765         status = nvme_submit_admin_cmd(dev, &c, NULL);
 766         if (status)
 767                 return -EIO;
 768         return 0;
 769 }
 770
 771 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 772 {
 773         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 774 }
 775
 776 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 777 {
 778         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 779 }
 780
 781 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 782 {
 783         struct nvme_queue *nvmeq = dev->queues[qid];
 784
 785         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 786
 787         /* Don't tell the adapter to delete the admin queue */
 788         if (qid) {
 789                 adapter_delete_sq(dev, qid);
 790                 adapter_delete_cq(dev, qid);
 791         }
 792
 793         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 794                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 795         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 796                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 797         kfree(nvmeq);
 798 }
 799
 800 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 801                                                         int depth, int vector)
 802 {
 803         struct device *dmadev = &dev->pci_dev->dev;
 804         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 805         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 806         if (!nvmeq)
 807                 return NULL;
 808
 809         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 810                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 811         if (!nvmeq->cqes)
 812                 goto free_nvmeq;
 813         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 814
 815         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 816                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 817         if (!nvmeq->sq_cmds)
 818                 goto free_cqdma;
 819
 820         nvmeq->q_dmadev = dmadev;
 821         nvmeq->dev = dev;
 822         spin_lock_init(&nvmeq->q_lock);
 823         nvmeq->cq_head = 0;
 824         nvmeq->cq_phase = 1;
 825         init_waitqueue_head(&nvmeq->sq_full);
 826         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 827         bio_list_init(&nvmeq->sq_cong);
 828         nvmeq->q_db = &dev->dbs[qid * 2];
 829         nvmeq->q_depth = depth;
 830         nvmeq->cq_vector = vector;
 831
 832         return nvmeq;
 833
 834  free_cqdma:
 835         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 836                                                         nvmeq->cq_dma_addr);
 837  free_nvmeq:
 838         kfree(nvmeq);
 839         return NULL;
 840 }
 841
 842 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 843                                                         const char *name)
 844 {
 845         if (use_threaded_interrupts)
 846                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 847                                         nvme_irq_check, nvme_irq,
 848                                         IRQF_DISABLED | IRQF_SHARED,
 849                                         name, nvmeq);
 850         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 851                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 852 }
 853
 854 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 855                                         int qid, int cq_size, int vector)
 856 {
 857         int result;
 858         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 859
 860         if (!nvmeq)
 861                 return NULL;
 862
 863         result = adapter_alloc_cq(dev, qid, nvmeq);
 864         if (result < 0)
 865                 goto free_nvmeq;
 866
 867         result = adapter_alloc_sq(dev, qid, nvmeq);
 868         if (result < 0)
 869                 goto release_cq;
 870
 871         result = queue_request_irq(dev, nvmeq, "nvme");
 872         if (result < 0)
 873                 goto release_sq;
 874
 875         return nvmeq;
 876
 877  release_sq:
 878         adapter_delete_sq(dev, qid);
 879  release_cq:
 880         adapter_delete_cq(dev, qid);
 881  free_nvmeq:
 882         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 883                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 884         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 885                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 886         kfree(nvmeq);
 887         return NULL;
 888 }
 889
 890 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 891 {
 892         int result;
 893         u32 aqa;
 894         struct nvme_queue *nvmeq;
 895
 896         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 897
 898         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 899         if (!nvmeq)
 900                 return -ENOMEM;
 901
 902         aqa = nvmeq->q_depth - 1;
 903         aqa |= aqa << 16;
 904
 905         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 906         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 907         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 908
 909         writel(0, &dev->bar->cc);
 910         writel(aqa, &dev->bar->aqa);
 911         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 912         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 913         writel(dev->ctrl_config, &dev->bar->cc);
 914
 915         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 916                 msleep(100);
 917                 if (fatal_signal_pending(current))
 918                         return -EINTR;
 919         }
 920
 921         result = queue_request_irq(dev, nvmeq, "nvme admin");
 922         dev->queues[0] = nvmeq;
 923         return result;
 924 }
 925
 926 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 927                                 unsigned long addr, unsigned length,
 928                                 struct scatterlist **sgp)
 929 {
 930         int i, err, count, nents, offset;
 931         struct scatterlist *sg;
 932         struct page **pages;
 933
 934         if (addr & 3)
 935                 return -EINVAL;
 936         if (!length)
 937                 return -EINVAL;
 938
 939         offset = offset_in_page(addr);
 940         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 941         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 942
 943         err = get_user_pages_fast(addr, count, 1, pages);
 944         if (err < count) {
 945                 count = err;
 946                 err = -EFAULT;
 947                 goto put_pages;
 948         }
 949
 950         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 951         sg_init_table(sg, count);
 952         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 953         length -= (PAGE_SIZE - offset);
 954         for (i = 1; i < count; i++) {
 955                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 956                 length -= PAGE_SIZE;
 957         }
 958
 959         err = -ENOMEM;
 960         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 961                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 962         if (!nents)
 963                 goto put_pages;
 964
 965         kfree(pages);
 966         *sgp = sg;
 967         return nents;
 968
 969  put_pages:
 970         for (i = 0; i < count; i++)
 971                 put_page(pages[i]);
 972         kfree(pages);
 973         return err;
 974 }
 975
 976 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 977                                 unsigned long addr, int length,
 978                                 struct scatterlist *sg, int nents)
 979 {
 980         int i, count;
 981
 982         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 983         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 984
 985         for (i = 0; i < count; i++)
 986                 put_page(sg_page(&sg[i]));
 987 }
 988
 989 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 990                                         unsigned long addr, unsigned length,
 991                                         struct nvme_command *cmd)
 992 {
 993         int err, nents;
 994         struct scatterlist *sg;
 995         struct nvme_prps *prps;
 996
 997         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 998         if (nents < 0)
 999                 return nents;
1000         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1001         err = nvme_submit_admin_cmd(dev, cmd, NULL);
1002         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1003         nvme_free_prps(dev, prps);
1004         return err ? -EIO : 0;
1005 }
1006
1007 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1008 {
1009         struct nvme_command c;
1010
1011         memset(&c, 0, sizeof(c));
1012         c.identify.opcode = nvme_admin_identify;
1013         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1014         c.identify.cns = cpu_to_le32(cns);
1015
1016         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1017 }
1018
1019 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1020 {
1021         struct nvme_command c;
1022
1023         memset(&c, 0, sizeof(c));
1024         c.features.opcode = nvme_admin_get_features;
1025         c.features.nsid = cpu_to_le32(ns->ns_id);
1026         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1027
1028         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1029 }
1030
1031 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1032 {
1033         struct nvme_dev *dev = ns->dev;
1034         struct nvme_queue *nvmeq;
1035         struct nvme_user_io io;
1036         struct nvme_command c;
1037         unsigned length;
1038         int nents, status;
1039         struct scatterlist *sg;
1040         struct nvme_prps *prps;
1041
1042         if (copy_from_user(&io, uio, sizeof(io)))
1043                 return -EFAULT;
1044         length = (io.nblocks + 1) << ns->lba_shift;
1045
1046         switch (io.opcode) {
1047         case nvme_cmd_write:
1048         case nvme_cmd_read:
1049                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1050                                                                 length, &sg);
1051         default:
1052                 return -EFAULT;
1053         }
1054
1055         if (nents < 0)
1056                 return nents;
1057
1058         memset(&c, 0, sizeof(c));
1059         c.rw.opcode = io.opcode;
1060         c.rw.flags = io.flags;
1061         c.rw.nsid = cpu_to_le32(ns->ns_id);
1062         c.rw.slba = cpu_to_le64(io.slba);
1063         c.rw.length = cpu_to_le16(io.nblocks);
1064         c.rw.control = cpu_to_le16(io.control);
1065         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1066         c.rw.reftag = io.reftag;
1067         c.rw.apptag = io.apptag;
1068         c.rw.appmask = io.appmask;
1069         /* XXX: metadata */
1070         prps = nvme_setup_prps(dev, &c.common, sg, length);
1071
1072         nvmeq = get_nvmeq(ns);
1073         /*
1074          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1075          * disabled.  We may be preempted at any point, and be rescheduled
1076          * to a different CPU.  That will cause cacheline bouncing, but no
1077          * additional races since q_lock already protects against other CPUs.
1078          */
1079         put_nvmeq(nvmeq);
1080         status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1081
1082         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1083         nvme_free_prps(dev, prps);
1084         return status;
1085 }
1086
1087 static int nvme_download_firmware(struct nvme_ns *ns,
1088                                                 struct nvme_dlfw __user *udlfw)
1089 {
1090         struct nvme_dev *dev = ns->dev;
1091         struct nvme_dlfw dlfw;
1092         struct nvme_command c;
1093         int nents, status;
1094         struct scatterlist *sg;
1095         struct nvme_prps *prps;
1096
1097         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1098                 return -EFAULT;
1099         if (dlfw.length >= (1 << 30))
1100                 return -EINVAL;
1101
1102         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1103         if (nents < 0)
1104                 return nents;
1105
1106         memset(&c, 0, sizeof(c));
1107         c.dlfw.opcode = nvme_admin_download_fw;
1108         c.dlfw.numd = cpu_to_le32(dlfw.length);
1109         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1110         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1111
1112         status = nvme_submit_admin_cmd(dev, &c, NULL);
1113         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1114         nvme_free_prps(dev, prps);
1115         return status;
1116 }
1117
1118 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1119 {
1120         struct nvme_dev *dev = ns->dev;
1121         struct nvme_command c;
1122
1123         memset(&c, 0, sizeof(c));
1124         c.common.opcode = nvme_admin_activate_fw;
1125         c.common.rsvd10[0] = cpu_to_le32(arg);
1126
1127         return nvme_submit_admin_cmd(dev, &c, NULL);
1128 }
1129
1130 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1131                                                         unsigned long arg)
1132 {
1133         struct nvme_ns *ns = bdev->bd_disk->private_data;
1134
1135         switch (cmd) {
1136         case NVME_IOCTL_IDENTIFY_NS:
1137                 return nvme_identify(ns, arg, 0);
1138         case NVME_IOCTL_IDENTIFY_CTRL:
1139                 return nvme_identify(ns, arg, 1);
1140         case NVME_IOCTL_GET_RANGE_TYPE:
1141                 return nvme_get_range_type(ns, arg);
1142         case NVME_IOCTL_SUBMIT_IO:
1143                 return nvme_submit_io(ns, (void __user *)arg);
1144         case NVME_IOCTL_DOWNLOAD_FW:
1145                 return nvme_download_firmware(ns, (void __user *)arg);
1146         case NVME_IOCTL_ACTIVATE_FW:
1147                 return nvme_activate_firmware(ns, arg);
1148         default:
1149                 return -ENOTTY;
1150         }
1151 }
1152
1153 static const struct block_device_operations nvme_fops = {
1154         .owner          = THIS_MODULE,
1155         .ioctl          = nvme_ioctl,
1156         .compat_ioctl   = nvme_ioctl,
1157 };
1158
1159 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1160 {
1161         while (bio_list_peek(&nvmeq->sq_cong)) {
1162                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1163                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1164                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1165                         bio_list_add_head(&nvmeq->sq_cong, bio);
1166                         break;
1167                 }
1168                 if (bio_list_empty(&nvmeq->sq_cong))
1169                         remove_wait_queue(&nvmeq->sq_full,
1170                                                         &nvmeq->sq_cong_wait);
1171         }
1172 }
1173
1174 static int nvme_kthread(void *data)
1175 {
1176         struct nvme_dev *dev;
1177
1178         while (!kthread_should_stop()) {
1179                 __set_current_state(TASK_RUNNING);
1180                 spin_lock(&dev_list_lock);
1181                 list_for_each_entry(dev, &dev_list, node) {
1182                         int i;
1183                         for (i = 0; i < dev->queue_count; i++) {
1184                                 struct nvme_queue *nvmeq = dev->queues[i];
1185                                 if (!nvmeq)
1186                                         continue;
1187                                 spin_lock_irq(&nvmeq->q_lock);
1188                                 if (nvme_process_cq(nvmeq))
1189                                         printk("process_cq did something\n");
1190                                 nvme_resubmit_bios(nvmeq);
1191                                 spin_unlock_irq(&nvmeq->q_lock);
1192                         }
1193                 }
1194                 spin_unlock(&dev_list_lock);
1195                 set_current_state(TASK_INTERRUPTIBLE);
1196                 schedule_timeout(HZ);
1197         }
1198         return 0;
1199 }
1200
1201 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1202                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1203 {
1204         struct nvme_ns *ns;
1205         struct gendisk *disk;
1206         int lbaf;
1207
1208         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1209                 return NULL;
1210
1211         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1212         if (!ns)
1213                 return NULL;
1214         ns->queue = blk_alloc_queue(GFP_KERNEL);
1215         if (!ns->queue)
1216                 goto out_free_ns;
1217         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1218                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1219         blk_queue_make_request(ns->queue, nvme_make_request);
1220         ns->dev = dev;
1221         ns->queue->queuedata = ns;
1222
1223         disk = alloc_disk(NVME_MINORS);
1224         if (!disk)
1225                 goto out_free_queue;
1226         ns->ns_id = index;
1227         ns->disk = disk;
1228         lbaf = id->flbas & 0xf;
1229         ns->lba_shift = id->lbaf[lbaf].ds;
1230
1231         disk->major = nvme_major;
1232         disk->minors = NVME_MINORS;
1233         disk->first_minor = NVME_MINORS * index;
1234         disk->fops = &nvme_fops;
1235         disk->private_data = ns;
1236         disk->queue = ns->queue;
1237         disk->driverfs_dev = &dev->pci_dev->dev;
1238         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1239         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1240
1241         return ns;
1242
1243  out_free_queue:
1244         blk_cleanup_queue(ns->queue);
1245  out_free_ns:
1246         kfree(ns);
1247         return NULL;
1248 }
1249
1250 static void nvme_ns_free(struct nvme_ns *ns)
1251 {
1252         put_disk(ns->disk);
1253         blk_cleanup_queue(ns->queue);
1254         kfree(ns);
1255 }
1256
1257 static int set_queue_count(struct nvme_dev *dev, int count)
1258 {
1259         int status;
1260         u32 result;
1261         struct nvme_command c;
1262         u32 q_count = (count - 1) | ((count - 1) << 16);
1263
1264         memset(&c, 0, sizeof(c));
1265         c.features.opcode = nvme_admin_get_features;
1266         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1267         c.features.dword11 = cpu_to_le32(q_count);
1268
1269         status = nvme_submit_admin_cmd(dev, &c, &result);
1270         if (status)
1271                 return -EIO;
1272         return min(result & 0xffff, result >> 16) + 1;
1273 }
1274
1275 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1276 {
1277         int result, cpu, i, nr_io_queues;
1278
1279         nr_io_queues = num_online_cpus();
1280         result = set_queue_count(dev, nr_io_queues);
1281         if (result < 0)
1282                 return result;
1283         if (result < nr_io_queues)
1284                 nr_io_queues = result;
1285
1286         /* Deregister the admin queue's interrupt */
1287         free_irq(dev->entry[0].vector, dev->queues[0]);
1288
1289         for (i = 0; i < nr_io_queues; i++)
1290                 dev->entry[i].entry = i;
1291         for (;;) {
1292                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1293                                                                 nr_io_queues);
1294                 if (result == 0) {
1295                         break;
1296                 } else if (result > 0) {
1297                         nr_io_queues = result;
1298                         continue;
1299                 } else {
1300                         nr_io_queues = 1;
1301                         break;
1302                 }
1303         }
1304
1305         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1306         /* XXX: handle failure here */
1307
1308         cpu = cpumask_first(cpu_online_mask);
1309         for (i = 0; i < nr_io_queues; i++) {
1310                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1311                 cpu = cpumask_next(cpu, cpu_online_mask);
1312         }
1313
1314         for (i = 0; i < nr_io_queues; i++) {
1315                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1316                                                         NVME_Q_DEPTH, i);
1317                 if (!dev->queues[i + 1])
1318                         return -ENOMEM;
1319                 dev->queue_count++;
1320         }
1321
1322         for (; i < num_possible_cpus(); i++) {
1323                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1324                 dev->queues[i + 1] = dev->queues[target + 1];
1325         }
1326
1327         return 0;
1328 }
1329
1330 static void nvme_free_queues(struct nvme_dev *dev)
1331 {
1332         int i;
1333
1334         for (i = dev->queue_count - 1; i >= 0; i--)
1335                 nvme_free_queue(dev, i);
1336 }
1337
1338 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1339 {
1340         int res, nn, i;
1341         struct nvme_ns *ns, *next;
1342         struct nvme_id_ctrl *ctrl;
1343         void *id;
1344         dma_addr_t dma_addr;
1345         struct nvme_command cid, crt;
1346
1347         res = nvme_setup_io_queues(dev);
1348         if (res)
1349                 return res;
1350
1351         /* XXX: Switch to a SG list once prp2 works */
1352         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1353                                                                 GFP_KERNEL);
1354
1355         memset(&cid, 0, sizeof(cid));
1356         cid.identify.opcode = nvme_admin_identify;
1357         cid.identify.nsid = 0;
1358         cid.identify.prp1 = cpu_to_le64(dma_addr);
1359         cid.identify.cns = cpu_to_le32(1);
1360
1361         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1362         if (res) {
1363                 res = -EIO;
1364                 goto out_free;
1365         }
1366
1367         ctrl = id;
1368         nn = le32_to_cpup(&ctrl->nn);
1369         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1370         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1371         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1372
1373         cid.identify.cns = 0;
1374         memset(&crt, 0, sizeof(crt));
1375         crt.features.opcode = nvme_admin_get_features;
1376         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1377         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1378
1379         for (i = 0; i <= nn; i++) {
1380                 cid.identify.nsid = cpu_to_le32(i);
1381                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1382                 if (res)
1383                         continue;
1384
1385                 if (((struct nvme_id_ns *)id)->ncap == 0)
1386                         continue;
1387
1388                 crt.features.nsid = cpu_to_le32(i);
1389                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1390                 if (res)
1391                         continue;
1392
1393                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1394                 if (ns)
1395                         list_add_tail(&ns->list, &dev->namespaces);
1396         }
1397         list_for_each_entry(ns, &dev->namespaces, list)
1398                 add_disk(ns->disk);
1399
1400         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1401         return 0;
1402
1403  out_free:
1404         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1405                 list_del(&ns->list);
1406                 nvme_ns_free(ns);
1407         }
1408
1409         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1410         return res;
1411 }
1412
1413 static int nvme_dev_remove(struct nvme_dev *dev)
1414 {
1415         struct nvme_ns *ns, *next;
1416
1417         spin_lock(&dev_list_lock);
1418         list_del(&dev->node);
1419         spin_unlock(&dev_list_lock);
1420
1421         /* TODO: wait all I/O finished or cancel them */
1422
1423         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1424                 list_del(&ns->list);
1425                 del_gendisk(ns->disk);
1426                 nvme_ns_free(ns);
1427         }
1428
1429         nvme_free_queues(dev);
1430
1431         return 0;
1432 }
1433
1434 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1435 {
1436         struct device *dmadev = &dev->pci_dev->dev;
1437         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1438                                                 PAGE_SIZE, PAGE_SIZE, 0);
1439         if (!dev->prp_page_pool)
1440                 return -ENOMEM;
1441
1442         /* Optimisation for I/Os between 4k and 128k */
1443         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1444                                                 256, 256, 0);
1445         if (!dev->prp_small_pool) {
1446                 dma_pool_destroy(dev->prp_page_pool);
1447                 return -ENOMEM;
1448         }
1449         return 0;
1450 }
1451
1452 static void nvme_release_prp_pools(struct nvme_dev *dev)
1453 {
1454         dma_pool_destroy(dev->prp_page_pool);
1455         dma_pool_destroy(dev->prp_small_pool);
1456 }
1457
1458 /* XXX: Use an ida or something to let remove / add work correctly */
1459 static void nvme_set_instance(struct nvme_dev *dev)
1460 {
1461         static int instance;
1462         dev->instance = instance++;
1463 }
1464
1465 static void nvme_release_instance(struct nvme_dev *dev)
1466 {
1467 }
1468
1469 static int __devinit nvme_probe(struct pci_dev *pdev,
1470                                                 const struct pci_device_id *id)
1471 {
1472         int bars, result = -ENOMEM;
1473         struct nvme_dev *dev;
1474
1475         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1476         if (!dev)
1477                 return -ENOMEM;
1478         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1479                                                                 GFP_KERNEL);
1480         if (!dev->entry)
1481                 goto free;
1482         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1483                                                                 GFP_KERNEL);
1484         if (!dev->queues)
1485                 goto free;
1486
1487         if (pci_enable_device_mem(pdev))
1488                 goto free;
1489         pci_set_master(pdev);
1490         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1491         if (pci_request_selected_regions(pdev, bars, "nvme"))
1492                 goto disable;
1493
1494         INIT_LIST_HEAD(&dev->namespaces);
1495         dev->pci_dev = pdev;
1496         pci_set_drvdata(pdev, dev);
1497         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1498         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1499         nvme_set_instance(dev);
1500         dev->entry[0].vector = pdev->irq;
1501
1502         result = nvme_setup_prp_pools(dev);
1503         if (result)
1504                 goto disable_msix;
1505
1506         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1507         if (!dev->bar) {
1508                 result = -ENOMEM;
1509                 goto disable_msix;
1510         }
1511
1512         result = nvme_configure_admin_queue(dev);
1513         if (result)
1514                 goto unmap;
1515         dev->queue_count++;
1516
1517         spin_lock(&dev_list_lock);
1518         list_add(&dev->node, &dev_list);
1519         spin_unlock(&dev_list_lock);
1520
1521         result = nvme_dev_add(dev);
1522         if (result)
1523                 goto delete;
1524
1525         return 0;
1526
1527  delete:
1528         spin_lock(&dev_list_lock);
1529         list_del(&dev->node);
1530         spin_unlock(&dev_list_lock);
1531
1532         nvme_free_queues(dev);
1533  unmap:
1534         iounmap(dev->bar);
1535  disable_msix:
1536         pci_disable_msix(pdev);
1537         nvme_release_instance(dev);
1538         nvme_release_prp_pools(dev);
1539  disable:
1540         pci_disable_device(pdev);
1541         pci_release_regions(pdev);
1542  free:
1543         kfree(dev->queues);
1544         kfree(dev->entry);
1545         kfree(dev);
1546         return result;
1547 }
1548
1549 static void __devexit nvme_remove(struct pci_dev *pdev)
1550 {
1551         struct nvme_dev *dev = pci_get_drvdata(pdev);
1552         nvme_dev_remove(dev);
1553         pci_disable_msix(pdev);
1554         iounmap(dev->bar);
1555         nvme_release_instance(dev);
1556         nvme_release_prp_pools(dev);
1557         pci_disable_device(pdev);
1558         pci_release_regions(pdev);
1559         kfree(dev->queues);
1560         kfree(dev->entry);
1561         kfree(dev);
1562 }
1563
1564 /* These functions are yet to be implemented */
1565 #define nvme_error_detected NULL
1566 #define nvme_dump_registers NULL
1567 #define nvme_link_reset NULL
1568 #define nvme_slot_reset NULL
1569 #define nvme_error_resume NULL
1570 #define nvme_suspend NULL
1571 #define nvme_resume NULL
1572
1573 static struct pci_error_handlers nvme_err_handler = {
1574         .error_detected = nvme_error_detected,
1575         .mmio_enabled   = nvme_dump_registers,
1576         .link_reset     = nvme_link_reset,
1577         .slot_reset     = nvme_slot_reset,
1578         .resume         = nvme_error_resume,
1579 };
1580
1581 /* Move to pci_ids.h later */
1582 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1583
1584 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1585         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1586         { 0, }
1587 };
1588 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1589
1590 static struct pci_driver nvme_driver = {
1591         .name           = "nvme",
1592         .id_table       = nvme_id_table,
1593         .probe          = nvme_probe,
1594         .remove         = __devexit_p(nvme_remove),
1595         .suspend        = nvme_suspend,
1596         .resume         = nvme_resume,
1597         .err_handler    = &nvme_err_handler,
1598 };
1599
1600 static int __init nvme_init(void)
1601 {
1602         int result = -EBUSY;
1603
1604         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1605         if (IS_ERR(nvme_thread))
1606                 return PTR_ERR(nvme_thread);
1607
1608         nvme_major = register_blkdev(nvme_major, "nvme");
1609         if (nvme_major <= 0)
1610                 goto kill_kthread;
1611
1612         result = pci_register_driver(&nvme_driver);
1613         if (result)
1614                 goto unregister_blkdev;
1615         return 0;
1616
1617  unregister_blkdev:
1618         unregister_blkdev(nvme_major, "nvme");
1619  kill_kthread:
1620         kthread_stop(nvme_thread);
1621         return result;
1622 }
1623
1624 static void __exit nvme_exit(void)
1625 {
1626         pci_unregister_driver(&nvme_driver);
1627         unregister_blkdev(nvme_major, "nvme");
1628         kthread_stop(nvme_thread);
1629 }
1630
1631 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1632 MODULE_LICENSE("GPL");
1633 MODULE_VERSION("0.4");
1634 module_init(nvme_init);
1635 module_exit(nvme_exit);