drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/fs.h>
  26 #include <linux/genhd.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kthread.h>
  33 #include <linux/kernel.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/version.h>
  43
  44 #define NVME_Q_DEPTH 1024
  45 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  46 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  47 #define NVME_MINORS 64
  48 #define IO_TIMEOUT      (5 * HZ)
  49 #define ADMIN_TIMEOUT   (60 * HZ)
  50
  51 static int nvme_major;
  52 module_param(nvme_major, int, 0);
  53
  54 static int use_threaded_interrupts;
  55 module_param(use_threaded_interrupts, int, 0);
  56
  57 static DEFINE_SPINLOCK(dev_list_lock);
  58 static LIST_HEAD(dev_list);
  59 static struct task_struct *nvme_thread;
  60
  61 /*
  62  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  63  */
  64 struct nvme_dev {
  65         struct list_head node;
  66         struct nvme_queue **queues;
  67         u32 __iomem *dbs;
  68         struct pci_dev *pci_dev;
  69         struct dma_pool *prp_page_pool;
  70         struct dma_pool *prp_small_pool;
  71         int instance;
  72         int queue_count;
  73         u32 ctrl_config;
  74         struct msix_entry *entry;
  75         struct nvme_bar __iomem *bar;
  76         struct list_head namespaces;
  77         char serial[20];
  78         char model[40];
  79         char firmware_rev[8];
  80 };
  81
  82 /*
  83  * An NVM Express namespace is equivalent to a SCSI LUN
  84  */
  85 struct nvme_ns {
  86         struct list_head list;
  87
  88         struct nvme_dev *dev;
  89         struct request_queue *queue;
  90         struct gendisk *disk;
  91
  92         int ns_id;
  93         int lba_shift;
  94 };
  95
  96 /*
  97  * An NVM Express queue.  Each device has at least two (one for admin
  98  * commands and one for I/O commands).
  99  */
 100 struct nvme_queue {
 101         struct device *q_dmadev;
 102         struct nvme_dev *dev;
 103         spinlock_t q_lock;
 104         struct nvme_command *sq_cmds;
 105         volatile struct nvme_completion *cqes;
 106         dma_addr_t sq_dma_addr;
 107         dma_addr_t cq_dma_addr;
 108         wait_queue_head_t sq_full;
 109         wait_queue_t sq_cong_wait;
 110         struct bio_list sq_cong;
 111         u32 __iomem *q_db;
 112         u16 q_depth;
 113         u16 cq_vector;
 114         u16 sq_head;
 115         u16 sq_tail;
 116         u16 cq_head;
 117         u16 cq_phase;
 118         unsigned long cmdid_data[];
 119 };
 120
 121 /*
 122  * Check we didin't inadvertently grow the command struct
 123  */
 124 static inline void _nvme_check_size(void)
 125 {
 126         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 133         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 134         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 135 }
 136
 137 struct nvme_cmd_info {
 138         unsigned long ctx;
 139         unsigned long timeout;
 140 };
 141
 142 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 143 {
 144         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 145 }
 146
 147 /**
 148  * alloc_cmdid() - Allocate a Command ID
 149  * @nvmeq: The queue that will be used for this command
 150  * @ctx: A pointer that will be passed to the handler
 151  * @handler: The ID of the handler to call
 152  *
 153  * Allocate a Command ID for a queue.  The data passed in will
 154  * be passed to the completion handler.  This is implemented by using
 155  * the bottom two bits of the ctx pointer to store the handler ID.
 156  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 157  * We can change this if it becomes a problem.
 158  *
 159  * May be called with local interrupts disabled and the q_lock held,
 160  * or with interrupts enabled and no locks held.
 161  */
 162 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 163                                                         unsigned timeout)
 164 {
 165         int depth = nvmeq->q_depth - 1;
 166         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 167         int cmdid;
 168
 169         BUG_ON((unsigned long)ctx & 3);
 170
 171         do {
 172                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 173                 if (cmdid >= depth)
 174                         return -EBUSY;
 175         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 176
 177         info[cmdid].ctx = (unsigned long)ctx | handler;
 178         info[cmdid].timeout = jiffies + timeout;
 179         return cmdid;
 180 }
 181
 182 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 183                                                 int handler, unsigned timeout)
 184 {
 185         int cmdid;
 186         wait_event_killable(nvmeq->sq_full,
 187                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 188         return (cmdid < 0) ? -EINTR : cmdid;
 189 }
 190
 191 /*
 192  * If you need more than four handlers, you'll need to change how
 193  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 194  * CMD_CTX value instead, if that works for your situation.
 195  */
 196 enum {
 197         sync_completion_id = 0,
 198         bio_completion_id,
 199 };
 200
 201 /* Special values must be a multiple of 4, and less than 0x1000 */
 202 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 203 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 204 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 205 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 206 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 207
 208 /*
 209  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 210  */
 211 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 212 {
 213         unsigned long data;
 214         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 215
 216         if (cmdid >= nvmeq->q_depth)
 217                 return CMD_CTX_INVALID;
 218         data = info[cmdid].ctx;
 219         info[cmdid].ctx = CMD_CTX_COMPLETED;
 220         clear_bit(cmdid, nvmeq->cmdid_data);
 221         wake_up(&nvmeq->sq_full);
 222         return data;
 223 }
 224
 225 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
 226 {
 227         unsigned long data;
 228         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 229         data = info[cmdid].ctx;
 230         info[cmdid].ctx = CMD_CTX_CANCELLED;
 231         return data;
 232 }
 233
 234 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 235 {
 236         return ns->dev->queues[get_cpu() + 1];
 237 }
 238
 239 static void put_nvmeq(struct nvme_queue *nvmeq)
 240 {
 241         put_cpu();
 242 }
 243
 244 /**
 245  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 246  * @nvmeq: The queue to use
 247  * @cmd: The command to send
 248  *
 249  * Safe to use from interrupt context
 250  */
 251 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 252 {
 253         unsigned long flags;
 254         u16 tail;
 255         spin_lock_irqsave(&nvmeq->q_lock, flags);
 256         tail = nvmeq->sq_tail;
 257         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 258         if (++tail == nvmeq->q_depth)
 259                 tail = 0;
 260         writel(tail, nvmeq->q_db);
 261         nvmeq->sq_tail = tail;
 262         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 263
 264         return 0;
 265 }
 266
 267 struct nvme_prps {
 268         int npages;             /* 0 means small pool in use */
 269         dma_addr_t first_dma;
 270         __le64 *list[0];
 271 };
 272
 273 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 274 {
 275         const int last_prp = PAGE_SIZE / 8 - 1;
 276         int i;
 277         dma_addr_t prp_dma;
 278
 279         if (!prps)
 280                 return;
 281
 282         prp_dma = prps->first_dma;
 283
 284         if (prps->npages == 0)
 285                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 286         for (i = 0; i < prps->npages; i++) {
 287                 __le64 *prp_list = prps->list[i];
 288                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 289                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 290                 prp_dma = next_prp_dma;
 291         }
 292         kfree(prps);
 293 }
 294
 295 struct nvme_bio {
 296         struct bio *bio;
 297         int nents;
 298         struct nvme_prps *prps;
 299         struct scatterlist sg[0];
 300 };
 301
 302 /* XXX: use a mempool */
 303 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 304 {
 305         return kzalloc(sizeof(struct nvme_bio) +
 306                         sizeof(struct scatterlist) * nseg, gfp);
 307 }
 308
 309 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 310 {
 311         nvme_free_prps(nvmeq->dev, nbio->prps);
 312         kfree(nbio);
 313 }
 314
 315 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 316                                                 struct nvme_completion *cqe)
 317 {
 318         struct nvme_bio *nbio = ctx;
 319         struct bio *bio = nbio->bio;
 320         u16 status = le16_to_cpup(&cqe->status) >> 1;
 321
 322         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 323                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 324         free_nbio(nvmeq, nbio);
 325         if (status) {
 326                 bio_endio(bio, -EIO);
 327         } else if (bio->bi_vcnt > bio->bi_idx) {
 328                 if (bio_list_empty(&nvmeq->sq_cong))
 329                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 330                 bio_list_add(&nvmeq->sq_cong, bio);
 331                 wake_up_process(nvme_thread);
 332         } else {
 333                 bio_endio(bio, 0);
 334         }
 335 }
 336
 337 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 338 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 339                                         struct nvme_common_command *cmd,
 340                                         struct scatterlist *sg, int *len,
 341                                         gfp_t gfp)
 342 {
 343         struct dma_pool *pool;
 344         int length = *len;
 345         int dma_len = sg_dma_len(sg);
 346         u64 dma_addr = sg_dma_address(sg);
 347         int offset = offset_in_page(dma_addr);
 348         __le64 *prp_list;
 349         dma_addr_t prp_dma;
 350         int nprps, npages, i;
 351         struct nvme_prps *prps = NULL;
 352
 353         cmd->prp1 = cpu_to_le64(dma_addr);
 354         length -= (PAGE_SIZE - offset);
 355         if (length <= 0)
 356                 return prps;
 357
 358         dma_len -= (PAGE_SIZE - offset);
 359         if (dma_len) {
 360                 dma_addr += (PAGE_SIZE - offset);
 361         } else {
 362                 sg = sg_next(sg);
 363                 dma_addr = sg_dma_address(sg);
 364                 dma_len = sg_dma_len(sg);
 365         }
 366
 367         if (length <= PAGE_SIZE) {
 368                 cmd->prp2 = cpu_to_le64(dma_addr);
 369                 return prps;
 370         }
 371
 372         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 373         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 374         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp);
 375         if (!prps) {
 376                 cmd->prp2 = cpu_to_le64(dma_addr);
 377                 *len = (*len - length) + PAGE_SIZE;
 378                 return prps;
 379         }
 380
 381         if (nprps <= (256 / 8)) {
 382                 pool = dev->prp_small_pool;
 383                 prps->npages = 0;
 384         } else {
 385                 pool = dev->prp_page_pool;
 386                 prps->npages = 1;
 387         }
 388
 389         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 390         if (!prp_list) {
 391                 cmd->prp2 = cpu_to_le64(dma_addr);
 392                 *len = (*len - length) + PAGE_SIZE;
 393                 kfree(prps);
 394                 return NULL;
 395         }
 396         prps->list[0] = prp_list;
 397         prps->first_dma = prp_dma;
 398         cmd->prp2 = cpu_to_le64(prp_dma);
 399         i = 0;
 400         for (;;) {
 401                 if (i == PAGE_SIZE / 8) {
 402                         __le64 *old_prp_list = prp_list;
 403                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 404                         if (!prp_list) {
 405                                 *len = (*len - length);
 406                                 return prps;
 407                         }
 408                         prps->list[prps->npages++] = prp_list;
 409                         prp_list[0] = old_prp_list[i - 1];
 410                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 411                         i = 1;
 412                 }
 413                 prp_list[i++] = cpu_to_le64(dma_addr);
 414                 dma_len -= PAGE_SIZE;
 415                 dma_addr += PAGE_SIZE;
 416                 length -= PAGE_SIZE;
 417                 if (length <= 0)
 418                         break;
 419                 if (dma_len > 0)
 420                         continue;
 421                 BUG_ON(dma_len < 0);
 422                 sg = sg_next(sg);
 423                 dma_addr = sg_dma_address(sg);
 424                 dma_len = sg_dma_len(sg);
 425         }
 426
 427         return prps;
 428 }
 429
 430 /* NVMe scatterlists require no holes in the virtual address */
 431 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 432                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 433
 434 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 435                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 436 {
 437         struct bio_vec *bvec, *bvprv = NULL;
 438         struct scatterlist *sg = NULL;
 439         int i, old_idx, length = 0, nsegs = 0;
 440
 441         sg_init_table(nbio->sg, psegs);
 442         old_idx = bio->bi_idx;
 443         bio_for_each_segment(bvec, bio, i) {
 444                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 445                         sg->length += bvec->bv_len;
 446                 } else {
 447                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 448                                 break;
 449                         sg = sg ? sg + 1 : nbio->sg;
 450                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 451                                                         bvec->bv_offset);
 452                         nsegs++;
 453                 }
 454                 length += bvec->bv_len;
 455                 bvprv = bvec;
 456         }
 457         bio->bi_idx = i;
 458         nbio->nents = nsegs;
 459         sg_mark_end(sg);
 460         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 461                 bio->bi_idx = old_idx;
 462                 return -ENOMEM;
 463         }
 464         return length;
 465 }
 466
 467 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 468                                                                 int cmdid)
 469 {
 470         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 471
 472         memset(cmnd, 0, sizeof(*cmnd));
 473         cmnd->common.opcode = nvme_cmd_flush;
 474         cmnd->common.command_id = cmdid;
 475         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 476
 477         if (++nvmeq->sq_tail == nvmeq->q_depth)
 478                 nvmeq->sq_tail = 0;
 479         writel(nvmeq->sq_tail, nvmeq->q_db);
 480
 481         return 0;
 482 }
 483
 484 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 485 {
 486         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 487                                                 sync_completion_id, IO_TIMEOUT);
 488         if (unlikely(cmdid < 0))
 489                 return cmdid;
 490
 491         return nvme_submit_flush(nvmeq, ns, cmdid);
 492 }
 493
 494 /*
 495  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 496  */
 497 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 498                                                                 struct bio *bio)
 499 {
 500         struct nvme_command *cmnd;
 501         struct nvme_bio *nbio;
 502         enum dma_data_direction dma_dir;
 503         int cmdid, length, result = -ENOMEM;
 504         u16 control;
 505         u32 dsmgmt;
 506         int psegs = bio_phys_segments(ns->queue, bio);
 507
 508         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 509                 result = nvme_submit_flush_data(nvmeq, ns);
 510                 if (result)
 511                         return result;
 512         }
 513
 514         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 515         if (!nbio)
 516                 goto nomem;
 517         nbio->bio = bio;
 518
 519         result = -EBUSY;
 520         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 521         if (unlikely(cmdid < 0))
 522                 goto free_nbio;
 523
 524         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 525                 return nvme_submit_flush(nvmeq, ns, cmdid);
 526
 527         control = 0;
 528         if (bio->bi_rw & REQ_FUA)
 529                 control |= NVME_RW_FUA;
 530         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 531                 control |= NVME_RW_LR;
 532
 533         dsmgmt = 0;
 534         if (bio->bi_rw & REQ_RAHEAD)
 535                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 536
 537         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 538
 539         memset(cmnd, 0, sizeof(*cmnd));
 540         if (bio_data_dir(bio)) {
 541                 cmnd->rw.opcode = nvme_cmd_write;
 542                 dma_dir = DMA_TO_DEVICE;
 543         } else {
 544                 cmnd->rw.opcode = nvme_cmd_read;
 545                 dma_dir = DMA_FROM_DEVICE;
 546         }
 547
 548         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 549         if (result < 0)
 550                 goto free_nbio;
 551         length = result;
 552
 553         cmnd->rw.command_id = cmdid;
 554         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 555         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 556                                                         &length, GFP_ATOMIC);
 557         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 558         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 559         cmnd->rw.control = cpu_to_le16(control);
 560         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 561
 562         bio->bi_sector += length >> 9;
 563
 564         if (++nvmeq->sq_tail == nvmeq->q_depth)
 565                 nvmeq->sq_tail = 0;
 566         writel(nvmeq->sq_tail, nvmeq->q_db);
 567
 568         return 0;
 569
 570  free_nbio:
 571         free_nbio(nvmeq, nbio);
 572  nomem:
 573         return result;
 574 }
 575
 576 /*
 577  * NB: return value of non-zero would mean that we were a stacking driver.
 578  * make_request must always succeed.
 579  */
 580 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 581 {
 582         struct nvme_ns *ns = q->queuedata;
 583         struct nvme_queue *nvmeq = get_nvmeq(ns);
 584         int result = -EBUSY;
 585
 586         spin_lock_irq(&nvmeq->q_lock);
 587         if (bio_list_empty(&nvmeq->sq_cong))
 588                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 589         if (unlikely(result)) {
 590                 if (bio_list_empty(&nvmeq->sq_cong))
 591                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 592                 bio_list_add(&nvmeq->sq_cong, bio);
 593         }
 594
 595         spin_unlock_irq(&nvmeq->q_lock);
 596         put_nvmeq(nvmeq);
 597
 598         return 0;
 599 }
 600
 601 struct sync_cmd_info {
 602         struct task_struct *task;
 603         u32 result;
 604         int status;
 605 };
 606
 607 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 608                                                 struct nvme_completion *cqe)
 609 {
 610         struct sync_cmd_info *cmdinfo = ctx;
 611         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 612                 return;
 613         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 614                 return;
 615         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 616                 dev_warn(nvmeq->q_dmadev,
 617                                 "completed id %d twice on queue %d\n",
 618                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 619                 return;
 620         }
 621         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 622                 dev_warn(nvmeq->q_dmadev,
 623                                 "invalid id %d completed on queue %d\n",
 624                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 625                 return;
 626         }
 627         cmdinfo->result = le32_to_cpup(&cqe->result);
 628         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 629         wake_up_process(cmdinfo->task);
 630 }
 631
 632 typedef void (*completion_fn)(struct nvme_queue *, void *,
 633                                                 struct nvme_completion *);
 634
 635 static const completion_fn nvme_completions[4] = {
 636         [sync_completion_id] = sync_completion,
 637         [bio_completion_id]  = bio_completion,
 638 };
 639
 640 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 641 {
 642         u16 head, phase;
 643
 644         head = nvmeq->cq_head;
 645         phase = nvmeq->cq_phase;
 646
 647         for (;;) {
 648                 unsigned long data;
 649                 void *ptr;
 650                 unsigned char handler;
 651                 struct nvme_completion cqe = nvmeq->cqes[head];
 652                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 653                         break;
 654                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 655                 if (++head == nvmeq->q_depth) {
 656                         head = 0;
 657                         phase = !phase;
 658                 }
 659
 660                 data = free_cmdid(nvmeq, cqe.command_id);
 661                 handler = data & 3;
 662                 ptr = (void *)(data & ~3UL);
 663                 nvme_completions[handler](nvmeq, ptr, &cqe);
 664         }
 665
 666         /* If the controller ignores the cq head doorbell and continuously
 667          * writes to the queue, it is theoretically possible to wrap around
 668          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 669          * requires that 0.1% of your interrupts are handled, so this isn't
 670          * a big problem.
 671          */
 672         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 673                 return IRQ_NONE;
 674
 675         writel(head, nvmeq->q_db + 1);
 676         nvmeq->cq_head = head;
 677         nvmeq->cq_phase = phase;
 678
 679         return IRQ_HANDLED;
 680 }
 681
 682 static irqreturn_t nvme_irq(int irq, void *data)
 683 {
 684         irqreturn_t result;
 685         struct nvme_queue *nvmeq = data;
 686         spin_lock(&nvmeq->q_lock);
 687         result = nvme_process_cq(nvmeq);
 688         spin_unlock(&nvmeq->q_lock);
 689         return result;
 690 }
 691
 692 static irqreturn_t nvme_irq_check(int irq, void *data)
 693 {
 694         struct nvme_queue *nvmeq = data;
 695         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 696         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 697                 return IRQ_NONE;
 698         return IRQ_WAKE_THREAD;
 699 }
 700
 701 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 702 {
 703         spin_lock_irq(&nvmeq->q_lock);
 704         cancel_cmdid(nvmeq, cmdid);
 705         spin_unlock_irq(&nvmeq->q_lock);
 706 }
 707
 708 /*
 709  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 710  * if the result is positive, it's an NVM Express status code
 711  */
 712 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 713                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 714 {
 715         int cmdid;
 716         struct sync_cmd_info cmdinfo;
 717
 718         cmdinfo.task = current;
 719         cmdinfo.status = -EINTR;
 720
 721         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 722                                                                 timeout);
 723         if (cmdid < 0)
 724                 return cmdid;
 725         cmd->common.command_id = cmdid;
 726
 727         set_current_state(TASK_KILLABLE);
 728         nvme_submit_cmd(nvmeq, cmd);
 729         schedule();
 730
 731         if (cmdinfo.status == -EINTR) {
 732                 nvme_abort_command(nvmeq, cmdid);
 733                 return -EINTR;
 734         }
 735
 736         if (result)
 737                 *result = cmdinfo.result;
 738
 739         return cmdinfo.status;
 740 }
 741
 742 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 743                                                                 u32 *result)
 744 {
 745         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 746 }
 747
 748 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 749 {
 750         int status;
 751         struct nvme_command c;
 752
 753         memset(&c, 0, sizeof(c));
 754         c.delete_queue.opcode = opcode;
 755         c.delete_queue.qid = cpu_to_le16(id);
 756
 757         status = nvme_submit_admin_cmd(dev, &c, NULL);
 758         if (status)
 759                 return -EIO;
 760         return 0;
 761 }
 762
 763 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 764                                                 struct nvme_queue *nvmeq)
 765 {
 766         int status;
 767         struct nvme_command c;
 768         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 769
 770         memset(&c, 0, sizeof(c));
 771         c.create_cq.opcode = nvme_admin_create_cq;
 772         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 773         c.create_cq.cqid = cpu_to_le16(qid);
 774         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 775         c.create_cq.cq_flags = cpu_to_le16(flags);
 776         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 777
 778         status = nvme_submit_admin_cmd(dev, &c, NULL);
 779         if (status)
 780                 return -EIO;
 781         return 0;
 782 }
 783
 784 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 785                                                 struct nvme_queue *nvmeq)
 786 {
 787         int status;
 788         struct nvme_command c;
 789         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 790
 791         memset(&c, 0, sizeof(c));
 792         c.create_sq.opcode = nvme_admin_create_sq;
 793         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 794         c.create_sq.sqid = cpu_to_le16(qid);
 795         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 796         c.create_sq.sq_flags = cpu_to_le16(flags);
 797         c.create_sq.cqid = cpu_to_le16(qid);
 798
 799         status = nvme_submit_admin_cmd(dev, &c, NULL);
 800         if (status)
 801                 return -EIO;
 802         return 0;
 803 }
 804
 805 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 806 {
 807         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 808 }
 809
 810 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 811 {
 812         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 813 }
 814
 815 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
 816                                                         dma_addr_t dma_addr)
 817 {
 818         struct nvme_command c;
 819
 820         memset(&c, 0, sizeof(c));
 821         c.identify.opcode = nvme_admin_identify;
 822         c.identify.nsid = cpu_to_le32(nsid);
 823         c.identify.prp1 = cpu_to_le64(dma_addr);
 824         c.identify.cns = cpu_to_le32(cns);
 825
 826         return nvme_submit_admin_cmd(dev, &c, NULL);
 827 }
 828
 829 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
 830                         unsigned dword11, dma_addr_t dma_addr, u32 *result)
 831 {
 832         struct nvme_command c;
 833
 834         memset(&c, 0, sizeof(c));
 835         c.features.opcode = nvme_admin_get_features;
 836         c.features.prp1 = cpu_to_le64(dma_addr);
 837         c.features.fid = cpu_to_le32(fid);
 838         c.features.dword11 = cpu_to_le32(dword11);
 839
 840         return nvme_submit_admin_cmd(dev, &c, result);
 841 }
 842
 843 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 844 {
 845         struct nvme_queue *nvmeq = dev->queues[qid];
 846         int vector = dev->entry[nvmeq->cq_vector].vector;
 847
 848         irq_set_affinity_hint(vector, NULL);
 849         free_irq(vector, nvmeq);
 850
 851         /* Don't tell the adapter to delete the admin queue */
 852         if (qid) {
 853                 adapter_delete_sq(dev, qid);
 854                 adapter_delete_cq(dev, qid);
 855         }
 856
 857         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 858                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 859         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 860                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 861         kfree(nvmeq);
 862 }
 863
 864 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 865                                                         int depth, int vector)
 866 {
 867         struct device *dmadev = &dev->pci_dev->dev;
 868         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 869         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 870         if (!nvmeq)
 871                 return NULL;
 872
 873         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 874                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 875         if (!nvmeq->cqes)
 876                 goto free_nvmeq;
 877         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 878
 879         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 880                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 881         if (!nvmeq->sq_cmds)
 882                 goto free_cqdma;
 883
 884         nvmeq->q_dmadev = dmadev;
 885         nvmeq->dev = dev;
 886         spin_lock_init(&nvmeq->q_lock);
 887         nvmeq->cq_head = 0;
 888         nvmeq->cq_phase = 1;
 889         init_waitqueue_head(&nvmeq->sq_full);
 890         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 891         bio_list_init(&nvmeq->sq_cong);
 892         nvmeq->q_db = &dev->dbs[qid * 2];
 893         nvmeq->q_depth = depth;
 894         nvmeq->cq_vector = vector;
 895
 896         return nvmeq;
 897
 898  free_cqdma:
 899         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 900                                                         nvmeq->cq_dma_addr);
 901  free_nvmeq:
 902         kfree(nvmeq);
 903         return NULL;
 904 }
 905
 906 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 907                                                         const char *name)
 908 {
 909         if (use_threaded_interrupts)
 910                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 911                                         nvme_irq_check, nvme_irq,
 912                                         IRQF_DISABLED | IRQF_SHARED,
 913                                         name, nvmeq);
 914         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 915                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 916 }
 917
 918 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 919                                         int qid, int cq_size, int vector)
 920 {
 921         int result;
 922         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 923
 924         if (!nvmeq)
 925                 return ERR_PTR(-ENOMEM);
 926
 927         result = adapter_alloc_cq(dev, qid, nvmeq);
 928         if (result < 0)
 929                 goto free_nvmeq;
 930
 931         result = adapter_alloc_sq(dev, qid, nvmeq);
 932         if (result < 0)
 933                 goto release_cq;
 934
 935         result = queue_request_irq(dev, nvmeq, "nvme");
 936         if (result < 0)
 937                 goto release_sq;
 938
 939         return nvmeq;
 940
 941  release_sq:
 942         adapter_delete_sq(dev, qid);
 943  release_cq:
 944         adapter_delete_cq(dev, qid);
 945  free_nvmeq:
 946         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 947                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 948         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 949                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 950         kfree(nvmeq);
 951         return ERR_PTR(result);
 952 }
 953
 954 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 955 {
 956         int result;
 957         u32 aqa;
 958         u64 cap;
 959         unsigned long timeout;
 960         struct nvme_queue *nvmeq;
 961
 962         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 963
 964         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 965         if (!nvmeq)
 966                 return -ENOMEM;
 967
 968         aqa = nvmeq->q_depth - 1;
 969         aqa |= aqa << 16;
 970
 971         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 972         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 973         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 974         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 975
 976         writel(0, &dev->bar->cc);
 977         writel(aqa, &dev->bar->aqa);
 978         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 979         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 980         writel(dev->ctrl_config, &dev->bar->cc);
 981
 982         cap = readq(&dev->bar->cap);
 983         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
 984
 985         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 986                 msleep(100);
 987                 if (fatal_signal_pending(current))
 988                         return -EINTR;
 989                 if (time_after(jiffies, timeout)) {
 990                         dev_err(&dev->pci_dev->dev,
 991                                 "Device not ready; aborting initialisation\n");
 992                         return -ENODEV;
 993                 }
 994         }
 995
 996         result = queue_request_irq(dev, nvmeq, "nvme admin");
 997         dev->queues[0] = nvmeq;
 998         return result;
 999 }
1000
1001 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
1002                                 unsigned long addr, unsigned length,
1003                                 struct scatterlist **sgp)
1004 {
1005         int i, err, count, nents, offset;
1006         struct scatterlist *sg;
1007         struct page **pages;
1008
1009         if (addr & 3)
1010                 return -EINVAL;
1011         if (!length)
1012                 return -EINVAL;
1013
1014         offset = offset_in_page(addr);
1015         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1016         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1017
1018         err = get_user_pages_fast(addr, count, 1, pages);
1019         if (err < count) {
1020                 count = err;
1021                 err = -EFAULT;
1022                 goto put_pages;
1023         }
1024
1025         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
1026         sg_init_table(sg, count);
1027         for (i = 0; i < count; i++) {
1028                 sg_set_page(&sg[i], pages[i],
1029                                 min_t(int, length, PAGE_SIZE - offset), offset);
1030                 length -= (PAGE_SIZE - offset);
1031                 offset = 0;
1032         }
1033
1034         err = -ENOMEM;
1035         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1036                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1037         if (!nents)
1038                 goto put_pages;
1039
1040         kfree(pages);
1041         *sgp = sg;
1042         return nents;
1043
1044  put_pages:
1045         for (i = 0; i < count; i++)
1046                 put_page(pages[i]);
1047         kfree(pages);
1048         return err;
1049 }
1050
1051 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1052                         unsigned long addr, int length, struct scatterlist *sg)
1053 {
1054         int i, count;
1055
1056         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1057         dma_unmap_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE);
1058
1059         for (i = 0; i < count; i++)
1060                 put_page(sg_page(&sg[i]));
1061 }
1062
1063 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1064 {
1065         struct nvme_dev *dev = ns->dev;
1066         struct nvme_queue *nvmeq;
1067         struct nvme_user_io io;
1068         struct nvme_command c;
1069         unsigned length;
1070         int nents, status;
1071         struct scatterlist *sg;
1072         struct nvme_prps *prps;
1073
1074         if (copy_from_user(&io, uio, sizeof(io)))
1075                 return -EFAULT;
1076         length = (io.nblocks + 1) << ns->lba_shift;
1077
1078         switch (io.opcode) {
1079         case nvme_cmd_write:
1080         case nvme_cmd_read:
1081         case nvme_cmd_compare:
1082                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1083                                                                 length, &sg);
1084                 break;
1085         default:
1086                 return -EINVAL;
1087         }
1088
1089         if (nents < 0)
1090                 return nents;
1091
1092         memset(&c, 0, sizeof(c));
1093         c.rw.opcode = io.opcode;
1094         c.rw.flags = io.flags;
1095         c.rw.nsid = cpu_to_le32(ns->ns_id);
1096         c.rw.slba = cpu_to_le64(io.slba);
1097         c.rw.length = cpu_to_le16(io.nblocks);
1098         c.rw.control = cpu_to_le16(io.control);
1099         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1100         c.rw.reftag = io.reftag;
1101         c.rw.apptag = io.apptag;
1102         c.rw.appmask = io.appmask;
1103         /* XXX: metadata */
1104         prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1105
1106         nvmeq = get_nvmeq(ns);
1107         /*
1108          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1109          * disabled.  We may be preempted at any point, and be rescheduled
1110          * to a different CPU.  That will cause cacheline bouncing, but no
1111          * additional races since q_lock already protects against other CPUs.
1112          */
1113         put_nvmeq(nvmeq);
1114         if (length != (io.nblocks + 1) << ns->lba_shift)
1115                 status = -ENOMEM;
1116         else
1117                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1118
1119         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg);
1120         nvme_free_prps(dev, prps);
1121         return status;
1122 }
1123
1124 static int nvme_user_admin_cmd(struct nvme_ns *ns,
1125                                         struct nvme_admin_cmd __user *ucmd)
1126 {
1127         struct nvme_dev *dev = ns->dev;
1128         struct nvme_admin_cmd cmd;
1129         struct nvme_command c;
1130         int status, length, nents = 0;
1131         struct scatterlist *sg;
1132         struct nvme_prps *prps = NULL;
1133
1134         if (!capable(CAP_SYS_ADMIN))
1135                 return -EACCES;
1136         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1137                 return -EFAULT;
1138
1139         memset(&c, 0, sizeof(c));
1140         c.common.opcode = cmd.opcode;
1141         c.common.flags = cmd.flags;
1142         c.common.nsid = cpu_to_le32(cmd.nsid);
1143         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1144         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1145         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1146         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1147         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1148         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1149         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1150         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1151
1152         length = cmd.data_len;
1153         if (cmd.data_len) {
1154                 nents = nvme_map_user_pages(dev, 1, cmd.addr, length, &sg);
1155                 if (nents < 0)
1156                         return nents;
1157                 prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1158         }
1159
1160         if (length != cmd.data_len)
1161                 status = -ENOMEM;
1162         else
1163                 status = nvme_submit_admin_cmd(dev, &c, NULL);
1164         if (cmd.data_len) {
1165                 nvme_unmap_user_pages(dev, 0, cmd.addr, cmd.data_len, sg);
1166                 nvme_free_prps(dev, prps);
1167         }
1168         return status;
1169 }
1170
1171 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1172                                                         unsigned long arg)
1173 {
1174         struct nvme_ns *ns = bdev->bd_disk->private_data;
1175
1176         switch (cmd) {
1177         case NVME_IOCTL_ID:
1178                 return ns->ns_id;
1179         case NVME_IOCTL_ADMIN_CMD:
1180                 return nvme_user_admin_cmd(ns, (void __user *)arg);
1181         case NVME_IOCTL_SUBMIT_IO:
1182                 return nvme_submit_io(ns, (void __user *)arg);
1183         default:
1184                 return -ENOTTY;
1185         }
1186 }
1187
1188 static const struct block_device_operations nvme_fops = {
1189         .owner          = THIS_MODULE,
1190         .ioctl          = nvme_ioctl,
1191         .compat_ioctl   = nvme_ioctl,
1192 };
1193
1194 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1195 {
1196         int depth = nvmeq->q_depth - 1;
1197         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1198         unsigned long now = jiffies;
1199         int cmdid;
1200
1201         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1202                 unsigned long data;
1203                 void *ptr;
1204                 unsigned char handler;
1205                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1206
1207                 if (!time_after(now, info[cmdid].timeout))
1208                         continue;
1209                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1210                 data = cancel_cmdid(nvmeq, cmdid);
1211                 handler = data & 3;
1212                 ptr = (void *)(data & ~3UL);
1213                 nvme_completions[handler](nvmeq, ptr, &cqe);
1214         }
1215 }
1216
1217 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1218 {
1219         while (bio_list_peek(&nvmeq->sq_cong)) {
1220                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1221                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1222                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1223                         bio_list_add_head(&nvmeq->sq_cong, bio);
1224                         break;
1225                 }
1226                 if (bio_list_empty(&nvmeq->sq_cong))
1227                         remove_wait_queue(&nvmeq->sq_full,
1228                                                         &nvmeq->sq_cong_wait);
1229         }
1230 }
1231
1232 static int nvme_kthread(void *data)
1233 {
1234         struct nvme_dev *dev;
1235
1236         while (!kthread_should_stop()) {
1237                 __set_current_state(TASK_RUNNING);
1238                 spin_lock(&dev_list_lock);
1239                 list_for_each_entry(dev, &dev_list, node) {
1240                         int i;
1241                         for (i = 0; i < dev->queue_count; i++) {
1242                                 struct nvme_queue *nvmeq = dev->queues[i];
1243                                 if (!nvmeq)
1244                                         continue;
1245                                 spin_lock_irq(&nvmeq->q_lock);
1246                                 if (nvme_process_cq(nvmeq))
1247                                         printk("process_cq did something\n");
1248                                 nvme_timeout_ios(nvmeq);
1249                                 nvme_resubmit_bios(nvmeq);
1250                                 spin_unlock_irq(&nvmeq->q_lock);
1251                         }
1252                 }
1253                 spin_unlock(&dev_list_lock);
1254                 set_current_state(TASK_INTERRUPTIBLE);
1255                 schedule_timeout(HZ);
1256         }
1257         return 0;
1258 }
1259
1260 static DEFINE_IDA(nvme_index_ida);
1261
1262 static int nvme_get_ns_idx(void)
1263 {
1264         int index, error;
1265
1266         do {
1267                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1268                         return -1;
1269
1270                 spin_lock(&dev_list_lock);
1271                 error = ida_get_new(&nvme_index_ida, &index);
1272                 spin_unlock(&dev_list_lock);
1273         } while (error == -EAGAIN);
1274
1275         if (error)
1276                 index = -1;
1277         return index;
1278 }
1279
1280 static void nvme_put_ns_idx(int index)
1281 {
1282         spin_lock(&dev_list_lock);
1283         ida_remove(&nvme_index_ida, index);
1284         spin_unlock(&dev_list_lock);
1285 }
1286
1287 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1288                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1289 {
1290         struct nvme_ns *ns;
1291         struct gendisk *disk;
1292         int lbaf;
1293
1294         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1295                 return NULL;
1296
1297         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1298         if (!ns)
1299                 return NULL;
1300         ns->queue = blk_alloc_queue(GFP_KERNEL);
1301         if (!ns->queue)
1302                 goto out_free_ns;
1303         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1304                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1305         blk_queue_make_request(ns->queue, nvme_make_request);
1306         ns->dev = dev;
1307         ns->queue->queuedata = ns;
1308
1309         disk = alloc_disk(NVME_MINORS);
1310         if (!disk)
1311                 goto out_free_queue;
1312         ns->ns_id = nsid;
1313         ns->disk = disk;
1314         lbaf = id->flbas & 0xf;
1315         ns->lba_shift = id->lbaf[lbaf].ds;
1316
1317         disk->major = nvme_major;
1318         disk->minors = NVME_MINORS;
1319         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1320         disk->fops = &nvme_fops;
1321         disk->private_data = ns;
1322         disk->queue = ns->queue;
1323         disk->driverfs_dev = &dev->pci_dev->dev;
1324         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1325         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1326
1327         return ns;
1328
1329  out_free_queue:
1330         blk_cleanup_queue(ns->queue);
1331  out_free_ns:
1332         kfree(ns);
1333         return NULL;
1334 }
1335
1336 static void nvme_ns_free(struct nvme_ns *ns)
1337 {
1338         int index = ns->disk->first_minor / NVME_MINORS;
1339         put_disk(ns->disk);
1340         nvme_put_ns_idx(index);
1341         blk_cleanup_queue(ns->queue);
1342         kfree(ns);
1343 }
1344
1345 static int set_queue_count(struct nvme_dev *dev, int count)
1346 {
1347         int status;
1348         u32 result;
1349         u32 q_count = (count - 1) | ((count - 1) << 16);
1350
1351         status = nvme_get_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1352                                                                 &result);
1353         if (status)
1354                 return -EIO;
1355         return min(result & 0xffff, result >> 16) + 1;
1356 }
1357
1358 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1359 {
1360         int result, cpu, i, nr_io_queues;
1361
1362         nr_io_queues = num_online_cpus();
1363         result = set_queue_count(dev, nr_io_queues);
1364         if (result < 0)
1365                 return result;
1366         if (result < nr_io_queues)
1367                 nr_io_queues = result;
1368
1369         /* Deregister the admin queue's interrupt */
1370         free_irq(dev->entry[0].vector, dev->queues[0]);
1371
1372         for (i = 0; i < nr_io_queues; i++)
1373                 dev->entry[i].entry = i;
1374         for (;;) {
1375                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1376                                                                 nr_io_queues);
1377                 if (result == 0) {
1378                         break;
1379                 } else if (result > 0) {
1380                         nr_io_queues = result;
1381                         continue;
1382                 } else {
1383                         nr_io_queues = 1;
1384                         break;
1385                 }
1386         }
1387
1388         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1389         /* XXX: handle failure here */
1390
1391         cpu = cpumask_first(cpu_online_mask);
1392         for (i = 0; i < nr_io_queues; i++) {
1393                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1394                 cpu = cpumask_next(cpu, cpu_online_mask);
1395         }
1396
1397         for (i = 0; i < nr_io_queues; i++) {
1398                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1399                                                         NVME_Q_DEPTH, i);
1400                 if (IS_ERR(dev->queues[i + 1]))
1401                         return PTR_ERR(dev->queues[i + 1]);
1402                 dev->queue_count++;
1403         }
1404
1405         for (; i < num_possible_cpus(); i++) {
1406                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1407                 dev->queues[i + 1] = dev->queues[target + 1];
1408         }
1409
1410         return 0;
1411 }
1412
1413 static void nvme_free_queues(struct nvme_dev *dev)
1414 {
1415         int i;
1416
1417         for (i = dev->queue_count - 1; i >= 0; i--)
1418                 nvme_free_queue(dev, i);
1419 }
1420
1421 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1422 {
1423         int res, nn, i;
1424         struct nvme_ns *ns, *next;
1425         struct nvme_id_ctrl *ctrl;
1426         struct nvme_id_ns *id_ns;
1427         void *mem;
1428         dma_addr_t dma_addr;
1429
1430         res = nvme_setup_io_queues(dev);
1431         if (res)
1432                 return res;
1433
1434         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1435                                                                 GFP_KERNEL);
1436
1437         res = nvme_identify(dev, 0, 1, dma_addr);
1438         if (res) {
1439                 res = -EIO;
1440                 goto out_free;
1441         }
1442
1443         ctrl = mem;
1444         nn = le32_to_cpup(&ctrl->nn);
1445         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1446         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1447         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1448
1449         id_ns = mem;
1450         for (i = 1; i <= nn; i++) {
1451                 res = nvme_identify(dev, i, 0, dma_addr);
1452                 if (res)
1453                         continue;
1454
1455                 if (id_ns->ncap == 0)
1456                         continue;
1457
1458                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1459                                                         dma_addr + 4096, NULL);
1460                 if (res)
1461                         continue;
1462
1463                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1464                 if (ns)
1465                         list_add_tail(&ns->list, &dev->namespaces);
1466         }
1467         list_for_each_entry(ns, &dev->namespaces, list)
1468                 add_disk(ns->disk);
1469
1470         goto out;
1471
1472  out_free:
1473         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1474                 list_del(&ns->list);
1475                 nvme_ns_free(ns);
1476         }
1477
1478  out:
1479         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1480         return res;
1481 }
1482
1483 static int nvme_dev_remove(struct nvme_dev *dev)
1484 {
1485         struct nvme_ns *ns, *next;
1486
1487         spin_lock(&dev_list_lock);
1488         list_del(&dev->node);
1489         spin_unlock(&dev_list_lock);
1490
1491         /* TODO: wait all I/O finished or cancel them */
1492
1493         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1494                 list_del(&ns->list);
1495                 del_gendisk(ns->disk);
1496                 nvme_ns_free(ns);
1497         }
1498
1499         nvme_free_queues(dev);
1500
1501         return 0;
1502 }
1503
1504 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1505 {
1506         struct device *dmadev = &dev->pci_dev->dev;
1507         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1508                                                 PAGE_SIZE, PAGE_SIZE, 0);
1509         if (!dev->prp_page_pool)
1510                 return -ENOMEM;
1511
1512         /* Optimisation for I/Os between 4k and 128k */
1513         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1514                                                 256, 256, 0);
1515         if (!dev->prp_small_pool) {
1516                 dma_pool_destroy(dev->prp_page_pool);
1517                 return -ENOMEM;
1518         }
1519         return 0;
1520 }
1521
1522 static void nvme_release_prp_pools(struct nvme_dev *dev)
1523 {
1524         dma_pool_destroy(dev->prp_page_pool);
1525         dma_pool_destroy(dev->prp_small_pool);
1526 }
1527
1528 /* XXX: Use an ida or something to let remove / add work correctly */
1529 static void nvme_set_instance(struct nvme_dev *dev)
1530 {
1531         static int instance;
1532         dev->instance = instance++;
1533 }
1534
1535 static void nvme_release_instance(struct nvme_dev *dev)
1536 {
1537 }
1538
1539 static int __devinit nvme_probe(struct pci_dev *pdev,
1540                                                 const struct pci_device_id *id)
1541 {
1542         int bars, result = -ENOMEM;
1543         struct nvme_dev *dev;
1544
1545         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1546         if (!dev)
1547                 return -ENOMEM;
1548         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1549                                                                 GFP_KERNEL);
1550         if (!dev->entry)
1551                 goto free;
1552         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1553                                                                 GFP_KERNEL);
1554         if (!dev->queues)
1555                 goto free;
1556
1557         if (pci_enable_device_mem(pdev))
1558                 goto free;
1559         pci_set_master(pdev);
1560         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1561         if (pci_request_selected_regions(pdev, bars, "nvme"))
1562                 goto disable;
1563
1564         INIT_LIST_HEAD(&dev->namespaces);
1565         dev->pci_dev = pdev;
1566         pci_set_drvdata(pdev, dev);
1567         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1568         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1569         nvme_set_instance(dev);
1570         dev->entry[0].vector = pdev->irq;
1571
1572         result = nvme_setup_prp_pools(dev);
1573         if (result)
1574                 goto disable_msix;
1575
1576         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1577         if (!dev->bar) {
1578                 result = -ENOMEM;
1579                 goto disable_msix;
1580         }
1581
1582         result = nvme_configure_admin_queue(dev);
1583         if (result)
1584                 goto unmap;
1585         dev->queue_count++;
1586
1587         spin_lock(&dev_list_lock);
1588         list_add(&dev->node, &dev_list);
1589         spin_unlock(&dev_list_lock);
1590
1591         result = nvme_dev_add(dev);
1592         if (result)
1593                 goto delete;
1594
1595         return 0;
1596
1597  delete:
1598         spin_lock(&dev_list_lock);
1599         list_del(&dev->node);
1600         spin_unlock(&dev_list_lock);
1601
1602         nvme_free_queues(dev);
1603  unmap:
1604         iounmap(dev->bar);
1605  disable_msix:
1606         pci_disable_msix(pdev);
1607         nvme_release_instance(dev);
1608         nvme_release_prp_pools(dev);
1609  disable:
1610         pci_disable_device(pdev);
1611         pci_release_regions(pdev);
1612  free:
1613         kfree(dev->queues);
1614         kfree(dev->entry);
1615         kfree(dev);
1616         return result;
1617 }
1618
1619 static void __devexit nvme_remove(struct pci_dev *pdev)
1620 {
1621         struct nvme_dev *dev = pci_get_drvdata(pdev);
1622         nvme_dev_remove(dev);
1623         pci_disable_msix(pdev);
1624         iounmap(dev->bar);
1625         nvme_release_instance(dev);
1626         nvme_release_prp_pools(dev);
1627         pci_disable_device(pdev);
1628         pci_release_regions(pdev);
1629         kfree(dev->queues);
1630         kfree(dev->entry);
1631         kfree(dev);
1632 }
1633
1634 /* These functions are yet to be implemented */
1635 #define nvme_error_detected NULL
1636 #define nvme_dump_registers NULL
1637 #define nvme_link_reset NULL
1638 #define nvme_slot_reset NULL
1639 #define nvme_error_resume NULL
1640 #define nvme_suspend NULL
1641 #define nvme_resume NULL
1642
1643 static struct pci_error_handlers nvme_err_handler = {
1644         .error_detected = nvme_error_detected,
1645         .mmio_enabled   = nvme_dump_registers,
1646         .link_reset     = nvme_link_reset,
1647         .slot_reset     = nvme_slot_reset,
1648         .resume         = nvme_error_resume,
1649 };
1650
1651 /* Move to pci_ids.h later */
1652 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1653
1654 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1655         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1656         { 0, }
1657 };
1658 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1659
1660 static struct pci_driver nvme_driver = {
1661         .name           = "nvme",
1662         .id_table       = nvme_id_table,
1663         .probe          = nvme_probe,
1664         .remove         = __devexit_p(nvme_remove),
1665         .suspend        = nvme_suspend,
1666         .resume         = nvme_resume,
1667         .err_handler    = &nvme_err_handler,
1668 };
1669
1670 static int __init nvme_init(void)
1671 {
1672         int result = -EBUSY;
1673
1674         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1675         if (IS_ERR(nvme_thread))
1676                 return PTR_ERR(nvme_thread);
1677
1678         nvme_major = register_blkdev(nvme_major, "nvme");
1679         if (nvme_major <= 0)
1680                 goto kill_kthread;
1681
1682         result = pci_register_driver(&nvme_driver);
1683         if (result)
1684                 goto unregister_blkdev;
1685         return 0;
1686
1687  unregister_blkdev:
1688         unregister_blkdev(nvme_major, "nvme");
1689  kill_kthread:
1690         kthread_stop(nvme_thread);
1691         return result;
1692 }
1693
1694 static void __exit nvme_exit(void)
1695 {
1696         pci_unregister_driver(&nvme_driver);
1697         unregister_blkdev(nvme_major, "nvme");
1698         kthread_stop(nvme_thread);
1699 }
1700
1701 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1702 MODULE_LICENSE("GPL");
1703 MODULE_VERSION("0.6");
1704 module_init(nvme_init);
1705 module_exit(nvme_exit);