drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/poison.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/version.h>
  40
  41 #define NVME_Q_DEPTH 1024
  42 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  43 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  44 #define NVME_MINORS 64
  45 #define IO_TIMEOUT      (5 * HZ)
  46 #define ADMIN_TIMEOUT   (60 * HZ)
  47
  48 static int nvme_major;
  49 module_param(nvme_major, int, 0);
  50
  51 static int use_threaded_interrupts;
  52 module_param(use_threaded_interrupts, int, 0);
  53
  54 static DEFINE_SPINLOCK(dev_list_lock);
  55 static LIST_HEAD(dev_list);
  56 static struct task_struct *nvme_thread;
  57
  58 /*
  59  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  60  */
  61 struct nvme_dev {
  62         struct list_head node;
  63         struct nvme_queue **queues;
  64         u32 __iomem *dbs;
  65         struct pci_dev *pci_dev;
  66         struct dma_pool *prp_page_pool;
  67         struct dma_pool *prp_small_pool;
  68         int instance;
  69         int queue_count;
  70         u32 ctrl_config;
  71         struct msix_entry *entry;
  72         struct nvme_bar __iomem *bar;
  73         struct list_head namespaces;
  74         char serial[20];
  75         char model[40];
  76         char firmware_rev[8];
  77 };
  78
  79 /*
  80  * An NVM Express namespace is equivalent to a SCSI LUN
  81  */
  82 struct nvme_ns {
  83         struct list_head list;
  84
  85         struct nvme_dev *dev;
  86         struct request_queue *queue;
  87         struct gendisk *disk;
  88
  89         int ns_id;
  90         int lba_shift;
  91 };
  92
  93 /*
  94  * An NVM Express queue.  Each device has at least two (one for admin
  95  * commands and one for I/O commands).
  96  */
  97 struct nvme_queue {
  98         struct device *q_dmadev;
  99         struct nvme_dev *dev;
 100         spinlock_t q_lock;
 101         struct nvme_command *sq_cmds;
 102         volatile struct nvme_completion *cqes;
 103         dma_addr_t sq_dma_addr;
 104         dma_addr_t cq_dma_addr;
 105         wait_queue_head_t sq_full;
 106         wait_queue_t sq_cong_wait;
 107         struct bio_list sq_cong;
 108         u32 __iomem *q_db;
 109         u16 q_depth;
 110         u16 cq_vector;
 111         u16 sq_head;
 112         u16 sq_tail;
 113         u16 cq_head;
 114         u16 cq_phase;
 115         unsigned long cmdid_data[];
 116 };
 117
 118 /*
 119  * Check we didin't inadvertently grow the command struct
 120  */
 121 static inline void _nvme_check_size(void)
 122 {
 123         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 132 }
 133
 134 struct nvme_cmd_info {
 135         unsigned long ctx;
 136         unsigned long timeout;
 137 };
 138
 139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 140 {
 141         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 142 }
 143
 144 /**
 145  * alloc_cmdid - Allocate a Command ID
 146  * @param nvmeq The queue that will be used for this command
 147  * @param ctx A pointer that will be passed to the handler
 148  * @param handler The ID of the handler to call
 149  *
 150  * Allocate a Command ID for a queue.  The data passed in will
 151  * be passed to the completion handler.  This is implemented by using
 152  * the bottom two bits of the ctx pointer to store the handler ID.
 153  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 154  * We can change this if it becomes a problem.
 155  */
 156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 157                                                         unsigned timeout)
 158 {
 159         int depth = nvmeq->q_depth;
 160         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 161         int cmdid;
 162
 163         BUG_ON((unsigned long)ctx & 3);
 164
 165         do {
 166                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 167                 if (cmdid >= depth)
 168                         return -EBUSY;
 169         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 170
 171         info[cmdid].ctx = (unsigned long)ctx | handler;
 172         info[cmdid].timeout = jiffies + timeout;
 173         return cmdid;
 174 }
 175
 176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 177                                                 int handler, unsigned timeout)
 178 {
 179         int cmdid;
 180         wait_event_killable(nvmeq->sq_full,
 181                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 182         return (cmdid < 0) ? -EINTR : cmdid;
 183 }
 184
 185 /* If you need more than four handlers, you'll need to change how
 186  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 187  * CMD_CTX value instead, if that works for your situation.
 188  */
 189 enum {
 190         sync_completion_id = 0,
 191         bio_completion_id,
 192 };
 193
 194 /* Special values must be a multiple of 4, and less than 0x1000 */
 195 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 196 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 197 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 198 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 199 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 200
 201 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 202 {
 203         unsigned long data;
 204         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 205
 206         if (cmdid >= nvmeq->q_depth)
 207                 return CMD_CTX_INVALID;
 208         data = info[cmdid].ctx;
 209         info[cmdid].ctx = CMD_CTX_COMPLETED;
 210         clear_bit(cmdid, nvmeq->cmdid_data);
 211         wake_up(&nvmeq->sq_full);
 212         return data;
 213 }
 214
 215 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 216 {
 217         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 218         info[cmdid].ctx = CMD_CTX_CANCELLED;
 219 }
 220
 221 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 222 {
 223         int qid, cpu = get_cpu();
 224         if (cpu < ns->dev->queue_count)
 225                 qid = cpu + 1;
 226         else
 227                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 228         return ns->dev->queues[qid];
 229 }
 230
 231 static void put_nvmeq(struct nvme_queue *nvmeq)
 232 {
 233         put_cpu();
 234 }
 235
 236 /**
 237  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 238  * @nvmeq: The queue to use
 239  * @cmd: The command to send
 240  *
 241  * Safe to use from interrupt context
 242  */
 243 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 244 {
 245         unsigned long flags;
 246         u16 tail;
 247         /* XXX: Need to check tail isn't going to overrun head */
 248         spin_lock_irqsave(&nvmeq->q_lock, flags);
 249         tail = nvmeq->sq_tail;
 250         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 251         if (++tail == nvmeq->q_depth)
 252                 tail = 0;
 253         writel(tail, nvmeq->q_db);
 254         nvmeq->sq_tail = tail;
 255         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 256
 257         return 0;
 258 }
 259
 260 struct nvme_prps {
 261         int npages;
 262         dma_addr_t first_dma;
 263         __le64 *list[0];
 264 };
 265
 266 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 267 {
 268         const int last_prp = PAGE_SIZE / 8 - 1;
 269         int i;
 270         dma_addr_t prp_dma;
 271
 272         if (!prps)
 273                 return;
 274
 275         prp_dma = prps->first_dma;
 276
 277         if (prps->npages == 0)
 278                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 279         for (i = 0; i < prps->npages; i++) {
 280                 __le64 *prp_list = prps->list[i];
 281                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 282                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 283                 prp_dma = next_prp_dma;
 284         }
 285         kfree(prps);
 286 }
 287
 288 struct nvme_bio {
 289         struct bio *bio;
 290         int nents;
 291         struct nvme_prps *prps;
 292         struct scatterlist sg[0];
 293 };
 294
 295 /* XXX: use a mempool */
 296 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 297 {
 298         return kzalloc(sizeof(struct nvme_bio) +
 299                         sizeof(struct scatterlist) * nseg, gfp);
 300 }
 301
 302 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 303 {
 304         nvme_free_prps(nvmeq->dev, nbio->prps);
 305         kfree(nbio);
 306 }
 307
 308 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 309                                                 struct nvme_completion *cqe)
 310 {
 311         struct nvme_bio *nbio = ctx;
 312         struct bio *bio = nbio->bio;
 313         u16 status = le16_to_cpup(&cqe->status) >> 1;
 314
 315         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 316                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 317         free_nbio(nvmeq, nbio);
 318         if (status)
 319                 bio_endio(bio, -EIO);
 320         if (bio->bi_vcnt > bio->bi_idx) {
 321                 bio_list_add(&nvmeq->sq_cong, bio);
 322                 wake_up_process(nvme_thread);
 323         } else {
 324                 bio_endio(bio, 0);
 325         }
 326 }
 327
 328 /* length is in bytes */
 329 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 330                                         struct nvme_common_command *cmd,
 331                                         struct scatterlist *sg, int length)
 332 {
 333         struct dma_pool *pool;
 334         int dma_len = sg_dma_len(sg);
 335         u64 dma_addr = sg_dma_address(sg);
 336         int offset = offset_in_page(dma_addr);
 337         __le64 *prp_list;
 338         dma_addr_t prp_dma;
 339         int nprps, npages, i, prp_page;
 340         struct nvme_prps *prps = NULL;
 341
 342         cmd->prp1 = cpu_to_le64(dma_addr);
 343         length -= (PAGE_SIZE - offset);
 344         if (length <= 0)
 345                 return prps;
 346
 347         dma_len -= (PAGE_SIZE - offset);
 348         if (dma_len) {
 349                 dma_addr += (PAGE_SIZE - offset);
 350         } else {
 351                 sg = sg_next(sg);
 352                 dma_addr = sg_dma_address(sg);
 353                 dma_len = sg_dma_len(sg);
 354         }
 355
 356         if (length <= PAGE_SIZE) {
 357                 cmd->prp2 = cpu_to_le64(dma_addr);
 358                 return prps;
 359         }
 360
 361         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 362         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 363         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 364         prp_page = 0;
 365         if (nprps <= (256 / 8)) {
 366                 pool = dev->prp_small_pool;
 367                 prps->npages = 0;
 368         } else {
 369                 pool = dev->prp_page_pool;
 370                 prps->npages = npages;
 371         }
 372
 373         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 374         prps->list[prp_page++] = prp_list;
 375         prps->first_dma = prp_dma;
 376         cmd->prp2 = cpu_to_le64(prp_dma);
 377         i = 0;
 378         for (;;) {
 379                 if (i == PAGE_SIZE / 8 - 1) {
 380                         __le64 *old_prp_list = prp_list;
 381                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 382                         prps->list[prp_page++] = prp_list;
 383                         old_prp_list[i] = cpu_to_le64(prp_dma);
 384                         i = 0;
 385                 }
 386                 prp_list[i++] = cpu_to_le64(dma_addr);
 387                 dma_len -= PAGE_SIZE;
 388                 dma_addr += PAGE_SIZE;
 389                 length -= PAGE_SIZE;
 390                 if (length <= 0)
 391                         break;
 392                 if (dma_len > 0)
 393                         continue;
 394                 BUG_ON(dma_len < 0);
 395                 sg = sg_next(sg);
 396                 dma_addr = sg_dma_address(sg);
 397                 dma_len = sg_dma_len(sg);
 398         }
 399
 400         return prps;
 401 }
 402
 403 /* NVMe scatterlists require no holes in the virtual address */
 404 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 405                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 406
 407 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 408                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 409 {
 410         struct bio_vec *bvec, *bvprv = NULL;
 411         struct scatterlist *sg = NULL;
 412         int i, old_idx, length = 0, nsegs = 0;
 413
 414         sg_init_table(nbio->sg, psegs);
 415         old_idx = bio->bi_idx;
 416         bio_for_each_segment(bvec, bio, i) {
 417                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 418                         sg->length += bvec->bv_len;
 419                 } else {
 420                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 421                                 break;
 422                         sg = sg ? sg + 1 : nbio->sg;
 423                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 424                                                         bvec->bv_offset);
 425                         nsegs++;
 426                 }
 427                 length += bvec->bv_len;
 428                 bvprv = bvec;
 429         }
 430         bio->bi_idx = i;
 431         nbio->nents = nsegs;
 432         sg_mark_end(sg);
 433         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 434                 bio->bi_idx = old_idx;
 435                 return -ENOMEM;
 436         }
 437         return length;
 438 }
 439
 440 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 441                                                                 int cmdid)
 442 {
 443         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 444
 445         memset(cmnd, 0, sizeof(*cmnd));
 446         cmnd->common.opcode = nvme_cmd_flush;
 447         cmnd->common.command_id = cmdid;
 448         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 449
 450         if (++nvmeq->sq_tail == nvmeq->q_depth)
 451                 nvmeq->sq_tail = 0;
 452         writel(nvmeq->sq_tail, nvmeq->q_db);
 453
 454         return 0;
 455 }
 456
 457 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 458 {
 459         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 460                                                 sync_completion_id, IO_TIMEOUT);
 461         if (unlikely(cmdid < 0))
 462                 return cmdid;
 463
 464         return nvme_submit_flush(nvmeq, ns, cmdid);
 465 }
 466
 467 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 468                                                                 struct bio *bio)
 469 {
 470         struct nvme_command *cmnd;
 471         struct nvme_bio *nbio;
 472         enum dma_data_direction dma_dir;
 473         int cmdid, length, result = -ENOMEM;
 474         u16 control;
 475         u32 dsmgmt;
 476         int psegs = bio_phys_segments(ns->queue, bio);
 477
 478         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 479                 result = nvme_submit_flush_data(nvmeq, ns);
 480                 if (result)
 481                         return result;
 482         }
 483
 484         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 485         if (!nbio)
 486                 goto nomem;
 487         nbio->bio = bio;
 488
 489         result = -EBUSY;
 490         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 491         if (unlikely(cmdid < 0))
 492                 goto free_nbio;
 493
 494         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 495                 return nvme_submit_flush(nvmeq, ns, cmdid);
 496
 497         control = 0;
 498         if (bio->bi_rw & REQ_FUA)
 499                 control |= NVME_RW_FUA;
 500         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 501                 control |= NVME_RW_LR;
 502
 503         dsmgmt = 0;
 504         if (bio->bi_rw & REQ_RAHEAD)
 505                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 506
 507         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 508
 509         memset(cmnd, 0, sizeof(*cmnd));
 510         if (bio_data_dir(bio)) {
 511                 cmnd->rw.opcode = nvme_cmd_write;
 512                 dma_dir = DMA_TO_DEVICE;
 513         } else {
 514                 cmnd->rw.opcode = nvme_cmd_read;
 515                 dma_dir = DMA_FROM_DEVICE;
 516         }
 517
 518         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 519         if (result < 0)
 520                 goto free_nbio;
 521         length = result;
 522
 523         cmnd->rw.command_id = cmdid;
 524         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 525         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 526                                                                 length);
 527         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 528         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 529         cmnd->rw.control = cpu_to_le16(control);
 530         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 531
 532         if (++nvmeq->sq_tail == nvmeq->q_depth)
 533                 nvmeq->sq_tail = 0;
 534         writel(nvmeq->sq_tail, nvmeq->q_db);
 535
 536         return 0;
 537
 538  free_nbio:
 539         free_nbio(nvmeq, nbio);
 540  nomem:
 541         return result;
 542 }
 543
 544 /*
 545  * NB: return value of non-zero would mean that we were a stacking driver.
 546  * make_request must always succeed.
 547  */
 548 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 549 {
 550         struct nvme_ns *ns = q->queuedata;
 551         struct nvme_queue *nvmeq = get_nvmeq(ns);
 552         int result = -EBUSY;
 553
 554         spin_lock_irq(&nvmeq->q_lock);
 555         if (bio_list_empty(&nvmeq->sq_cong))
 556                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 557         if (unlikely(result)) {
 558                 if (bio_list_empty(&nvmeq->sq_cong))
 559                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 560                 bio_list_add(&nvmeq->sq_cong, bio);
 561         }
 562
 563         spin_unlock_irq(&nvmeq->q_lock);
 564         put_nvmeq(nvmeq);
 565
 566         return 0;
 567 }
 568
 569 struct sync_cmd_info {
 570         struct task_struct *task;
 571         u32 result;
 572         int status;
 573 };
 574
 575 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 576                                                 struct nvme_completion *cqe)
 577 {
 578         struct sync_cmd_info *cmdinfo = ctx;
 579         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 580                 return;
 581         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 582                 return;
 583         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 584                 dev_warn(nvmeq->q_dmadev,
 585                                 "completed id %d twice on queue %d\n",
 586                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 587                 return;
 588         }
 589         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 590                 dev_warn(nvmeq->q_dmadev,
 591                                 "invalid id %d completed on queue %d\n",
 592                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 593                 return;
 594         }
 595         cmdinfo->result = le32_to_cpup(&cqe->result);
 596         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 597         wake_up_process(cmdinfo->task);
 598 }
 599
 600 typedef void (*completion_fn)(struct nvme_queue *, void *,
 601                                                 struct nvme_completion *);
 602
 603 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 604 {
 605         u16 head, phase;
 606
 607         static const completion_fn completions[4] = {
 608                 [sync_completion_id] = sync_completion,
 609                 [bio_completion_id]  = bio_completion,
 610         };
 611
 612         head = nvmeq->cq_head;
 613         phase = nvmeq->cq_phase;
 614
 615         for (;;) {
 616                 unsigned long data;
 617                 void *ptr;
 618                 unsigned char handler;
 619                 struct nvme_completion cqe = nvmeq->cqes[head];
 620                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 621                         break;
 622                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 623                 if (++head == nvmeq->q_depth) {
 624                         head = 0;
 625                         phase = !phase;
 626                 }
 627
 628                 data = free_cmdid(nvmeq, cqe.command_id);
 629                 handler = data & 3;
 630                 ptr = (void *)(data & ~3UL);
 631                 completions[handler](nvmeq, ptr, &cqe);
 632         }
 633
 634         /* If the controller ignores the cq head doorbell and continuously
 635          * writes to the queue, it is theoretically possible to wrap around
 636          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 637          * requires that 0.1% of your interrupts are handled, so this isn't
 638          * a big problem.
 639          */
 640         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 641                 return IRQ_NONE;
 642
 643         writel(head, nvmeq->q_db + 1);
 644         nvmeq->cq_head = head;
 645         nvmeq->cq_phase = phase;
 646
 647         return IRQ_HANDLED;
 648 }
 649
 650 static irqreturn_t nvme_irq(int irq, void *data)
 651 {
 652         irqreturn_t result;
 653         struct nvme_queue *nvmeq = data;
 654         spin_lock(&nvmeq->q_lock);
 655         result = nvme_process_cq(nvmeq);
 656         spin_unlock(&nvmeq->q_lock);
 657         return result;
 658 }
 659
 660 static irqreturn_t nvme_irq_check(int irq, void *data)
 661 {
 662         struct nvme_queue *nvmeq = data;
 663         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 664         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 665                 return IRQ_NONE;
 666         return IRQ_WAKE_THREAD;
 667 }
 668
 669 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 670 {
 671         spin_lock_irq(&nvmeq->q_lock);
 672         cancel_cmdid_data(nvmeq, cmdid);
 673         spin_unlock_irq(&nvmeq->q_lock);
 674 }
 675
 676 /*
 677  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 678  * if the result is positive, it's an NVM Express status code
 679  */
 680 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 681                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 682 {
 683         int cmdid;
 684         struct sync_cmd_info cmdinfo;
 685
 686         cmdinfo.task = current;
 687         cmdinfo.status = -EINTR;
 688
 689         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 690                                                                 timeout);
 691         if (cmdid < 0)
 692                 return cmdid;
 693         cmd->common.command_id = cmdid;
 694
 695         set_current_state(TASK_KILLABLE);
 696         nvme_submit_cmd(nvmeq, cmd);
 697         schedule();
 698
 699         if (cmdinfo.status == -EINTR) {
 700                 nvme_abort_command(nvmeq, cmdid);
 701                 return -EINTR;
 702         }
 703
 704         if (result)
 705                 *result = cmdinfo.result;
 706
 707         return cmdinfo.status;
 708 }
 709
 710 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 711                                                                 u32 *result)
 712 {
 713         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 714 }
 715
 716 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 717 {
 718         int status;
 719         struct nvme_command c;
 720
 721         memset(&c, 0, sizeof(c));
 722         c.delete_queue.opcode = opcode;
 723         c.delete_queue.qid = cpu_to_le16(id);
 724
 725         status = nvme_submit_admin_cmd(dev, &c, NULL);
 726         if (status)
 727                 return -EIO;
 728         return 0;
 729 }
 730
 731 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 732                                                 struct nvme_queue *nvmeq)
 733 {
 734         int status;
 735         struct nvme_command c;
 736         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 737
 738         memset(&c, 0, sizeof(c));
 739         c.create_cq.opcode = nvme_admin_create_cq;
 740         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 741         c.create_cq.cqid = cpu_to_le16(qid);
 742         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 743         c.create_cq.cq_flags = cpu_to_le16(flags);
 744         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 745
 746         status = nvme_submit_admin_cmd(dev, &c, NULL);
 747         if (status)
 748                 return -EIO;
 749         return 0;
 750 }
 751
 752 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 753                                                 struct nvme_queue *nvmeq)
 754 {
 755         int status;
 756         struct nvme_command c;
 757         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 758
 759         memset(&c, 0, sizeof(c));
 760         c.create_sq.opcode = nvme_admin_create_sq;
 761         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 762         c.create_sq.sqid = cpu_to_le16(qid);
 763         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 764         c.create_sq.sq_flags = cpu_to_le16(flags);
 765         c.create_sq.cqid = cpu_to_le16(qid);
 766
 767         status = nvme_submit_admin_cmd(dev, &c, NULL);
 768         if (status)
 769                 return -EIO;
 770         return 0;
 771 }
 772
 773 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 774 {
 775         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 776 }
 777
 778 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 779 {
 780         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 781 }
 782
 783 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 784 {
 785         struct nvme_queue *nvmeq = dev->queues[qid];
 786
 787         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 788
 789         /* Don't tell the adapter to delete the admin queue */
 790         if (qid) {
 791                 adapter_delete_sq(dev, qid);
 792                 adapter_delete_cq(dev, qid);
 793         }
 794
 795         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 796                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 797         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 798                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 799         kfree(nvmeq);
 800 }
 801
 802 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 803                                                         int depth, int vector)
 804 {
 805         struct device *dmadev = &dev->pci_dev->dev;
 806         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 807         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 808         if (!nvmeq)
 809                 return NULL;
 810
 811         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 812                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 813         if (!nvmeq->cqes)
 814                 goto free_nvmeq;
 815         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 816
 817         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 818                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 819         if (!nvmeq->sq_cmds)
 820                 goto free_cqdma;
 821
 822         nvmeq->q_dmadev = dmadev;
 823         nvmeq->dev = dev;
 824         spin_lock_init(&nvmeq->q_lock);
 825         nvmeq->cq_head = 0;
 826         nvmeq->cq_phase = 1;
 827         init_waitqueue_head(&nvmeq->sq_full);
 828         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 829         bio_list_init(&nvmeq->sq_cong);
 830         nvmeq->q_db = &dev->dbs[qid * 2];
 831         nvmeq->q_depth = depth;
 832         nvmeq->cq_vector = vector;
 833
 834         return nvmeq;
 835
 836  free_cqdma:
 837         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 838                                                         nvmeq->cq_dma_addr);
 839  free_nvmeq:
 840         kfree(nvmeq);
 841         return NULL;
 842 }
 843
 844 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 845                                                         const char *name)
 846 {
 847         if (use_threaded_interrupts)
 848                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 849                                         nvme_irq_check, nvme_irq,
 850                                         IRQF_DISABLED | IRQF_SHARED,
 851                                         name, nvmeq);
 852         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 853                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 854 }
 855
 856 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 857                                         int qid, int cq_size, int vector)
 858 {
 859         int result;
 860         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 861
 862         if (!nvmeq)
 863                 return NULL;
 864
 865         result = adapter_alloc_cq(dev, qid, nvmeq);
 866         if (result < 0)
 867                 goto free_nvmeq;
 868
 869         result = adapter_alloc_sq(dev, qid, nvmeq);
 870         if (result < 0)
 871                 goto release_cq;
 872
 873         result = queue_request_irq(dev, nvmeq, "nvme");
 874         if (result < 0)
 875                 goto release_sq;
 876
 877         return nvmeq;
 878
 879  release_sq:
 880         adapter_delete_sq(dev, qid);
 881  release_cq:
 882         adapter_delete_cq(dev, qid);
 883  free_nvmeq:
 884         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 885                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 886         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 887                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 888         kfree(nvmeq);
 889         return NULL;
 890 }
 891
 892 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 893 {
 894         int result;
 895         u32 aqa;
 896         struct nvme_queue *nvmeq;
 897
 898         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 899
 900         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 901         if (!nvmeq)
 902                 return -ENOMEM;
 903
 904         aqa = nvmeq->q_depth - 1;
 905         aqa |= aqa << 16;
 906
 907         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 908         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 909         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 910
 911         writel(0, &dev->bar->cc);
 912         writel(aqa, &dev->bar->aqa);
 913         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 914         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 915         writel(dev->ctrl_config, &dev->bar->cc);
 916
 917         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 918                 msleep(100);
 919                 if (fatal_signal_pending(current))
 920                         return -EINTR;
 921         }
 922
 923         result = queue_request_irq(dev, nvmeq, "nvme admin");
 924         dev->queues[0] = nvmeq;
 925         return result;
 926 }
 927
 928 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 929                                 unsigned long addr, unsigned length,
 930                                 struct scatterlist **sgp)
 931 {
 932         int i, err, count, nents, offset;
 933         struct scatterlist *sg;
 934         struct page **pages;
 935
 936         if (addr & 3)
 937                 return -EINVAL;
 938         if (!length)
 939                 return -EINVAL;
 940
 941         offset = offset_in_page(addr);
 942         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 943         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 944
 945         err = get_user_pages_fast(addr, count, 1, pages);
 946         if (err < count) {
 947                 count = err;
 948                 err = -EFAULT;
 949                 goto put_pages;
 950         }
 951
 952         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 953         sg_init_table(sg, count);
 954         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 955         length -= (PAGE_SIZE - offset);
 956         for (i = 1; i < count; i++) {
 957                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 958                 length -= PAGE_SIZE;
 959         }
 960
 961         err = -ENOMEM;
 962         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 963                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 964         if (!nents)
 965                 goto put_pages;
 966
 967         kfree(pages);
 968         *sgp = sg;
 969         return nents;
 970
 971  put_pages:
 972         for (i = 0; i < count; i++)
 973                 put_page(pages[i]);
 974         kfree(pages);
 975         return err;
 976 }
 977
 978 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 979                                 unsigned long addr, int length,
 980                                 struct scatterlist *sg, int nents)
 981 {
 982         int i, count;
 983
 984         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 985         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 986
 987         for (i = 0; i < count; i++)
 988                 put_page(sg_page(&sg[i]));
 989 }
 990
 991 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 992                                         unsigned long addr, unsigned length,
 993                                         struct nvme_command *cmd)
 994 {
 995         int err, nents;
 996         struct scatterlist *sg;
 997         struct nvme_prps *prps;
 998
 999         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1000         if (nents < 0)
1001                 return nents;
1002         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
1003         err = nvme_submit_admin_cmd(dev, cmd, NULL);
1004         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1005         nvme_free_prps(dev, prps);
1006         return err ? -EIO : 0;
1007 }
1008
1009 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1010 {
1011         struct nvme_command c;
1012
1013         memset(&c, 0, sizeof(c));
1014         c.identify.opcode = nvme_admin_identify;
1015         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1016         c.identify.cns = cpu_to_le32(cns);
1017
1018         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1019 }
1020
1021 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1022 {
1023         struct nvme_command c;
1024
1025         memset(&c, 0, sizeof(c));
1026         c.features.opcode = nvme_admin_get_features;
1027         c.features.nsid = cpu_to_le32(ns->ns_id);
1028         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1029
1030         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1031 }
1032
1033 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1034 {
1035         struct nvme_dev *dev = ns->dev;
1036         struct nvme_queue *nvmeq;
1037         struct nvme_user_io io;
1038         struct nvme_command c;
1039         unsigned length;
1040         u32 result;
1041         int nents, status;
1042         struct scatterlist *sg;
1043         struct nvme_prps *prps;
1044
1045         if (copy_from_user(&io, uio, sizeof(io)))
1046                 return -EFAULT;
1047         length = io.nblocks << io.block_shift;
1048         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
1049         if (nents < 0)
1050                 return nents;
1051
1052         memset(&c, 0, sizeof(c));
1053         c.rw.opcode = io.opcode;
1054         c.rw.flags = io.flags;
1055         c.rw.nsid = cpu_to_le32(io.nsid);
1056         c.rw.slba = cpu_to_le64(io.slba);
1057         c.rw.length = cpu_to_le16(io.nblocks - 1);
1058         c.rw.control = cpu_to_le16(io.control);
1059         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1060         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1061         c.rw.apptag = cpu_to_le16(io.apptag);
1062         c.rw.appmask = cpu_to_le16(io.appmask);
1063         /* XXX: metadata */
1064         prps = nvme_setup_prps(dev, &c.common, sg, length);
1065
1066         nvmeq = get_nvmeq(ns);
1067         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1068          * disabled.  We may be preempted at any point, and be rescheduled
1069          * to a different CPU.  That will cause cacheline bouncing, but no
1070          * additional races since q_lock already protects against other CPUs.
1071          */
1072         put_nvmeq(nvmeq);
1073         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1074
1075         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1076         nvme_free_prps(dev, prps);
1077         put_user(result, &uio->result);
1078         return status;
1079 }
1080
1081 static int nvme_download_firmware(struct nvme_ns *ns,
1082                                                 struct nvme_dlfw __user *udlfw)
1083 {
1084         struct nvme_dev *dev = ns->dev;
1085         struct nvme_dlfw dlfw;
1086         struct nvme_command c;
1087         int nents, status;
1088         struct scatterlist *sg;
1089         struct nvme_prps *prps;
1090
1091         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1092                 return -EFAULT;
1093         if (dlfw.length >= (1 << 30))
1094                 return -EINVAL;
1095
1096         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1097         if (nents < 0)
1098                 return nents;
1099
1100         memset(&c, 0, sizeof(c));
1101         c.dlfw.opcode = nvme_admin_download_fw;
1102         c.dlfw.numd = cpu_to_le32(dlfw.length);
1103         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1104         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1105
1106         status = nvme_submit_admin_cmd(dev, &c, NULL);
1107         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1108         nvme_free_prps(dev, prps);
1109         return status;
1110 }
1111
1112 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1113 {
1114         struct nvme_dev *dev = ns->dev;
1115         struct nvme_command c;
1116
1117         memset(&c, 0, sizeof(c));
1118         c.common.opcode = nvme_admin_activate_fw;
1119         c.common.rsvd10[0] = cpu_to_le32(arg);
1120
1121         return nvme_submit_admin_cmd(dev, &c, NULL);
1122 }
1123
1124 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1125                                                         unsigned long arg)
1126 {
1127         struct nvme_ns *ns = bdev->bd_disk->private_data;
1128
1129         switch (cmd) {
1130         case NVME_IOCTL_IDENTIFY_NS:
1131                 return nvme_identify(ns, arg, 0);
1132         case NVME_IOCTL_IDENTIFY_CTRL:
1133                 return nvme_identify(ns, arg, 1);
1134         case NVME_IOCTL_GET_RANGE_TYPE:
1135                 return nvme_get_range_type(ns, arg);
1136         case NVME_IOCTL_SUBMIT_IO:
1137                 return nvme_submit_io(ns, (void __user *)arg);
1138         case NVME_IOCTL_DOWNLOAD_FW:
1139                 return nvme_download_firmware(ns, (void __user *)arg);
1140         case NVME_IOCTL_ACTIVATE_FW:
1141                 return nvme_activate_firmware(ns, arg);
1142         default:
1143                 return -ENOTTY;
1144         }
1145 }
1146
1147 static const struct block_device_operations nvme_fops = {
1148         .owner          = THIS_MODULE,
1149         .ioctl          = nvme_ioctl,
1150 };
1151
1152 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1153 {
1154         while (bio_list_peek(&nvmeq->sq_cong)) {
1155                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1156                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1157                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1158                         bio_list_add_head(&nvmeq->sq_cong, bio);
1159                         break;
1160                 }
1161         }
1162 }
1163
1164 static int nvme_kthread(void *data)
1165 {
1166         struct nvme_dev *dev;
1167
1168         while (!kthread_should_stop()) {
1169                 __set_current_state(TASK_RUNNING);
1170                 spin_lock(&dev_list_lock);
1171                 list_for_each_entry(dev, &dev_list, node) {
1172                         int i;
1173                         for (i = 0; i < dev->queue_count; i++) {
1174                                 struct nvme_queue *nvmeq = dev->queues[i];
1175                                 if (!nvmeq)
1176                                         continue;
1177                                 spin_lock_irq(&nvmeq->q_lock);
1178                                 if (nvme_process_cq(nvmeq))
1179                                         printk("process_cq did something\n");
1180                                 nvme_resubmit_bios(nvmeq);
1181                                 spin_unlock_irq(&nvmeq->q_lock);
1182                         }
1183                 }
1184                 spin_unlock(&dev_list_lock);
1185                 set_current_state(TASK_INTERRUPTIBLE);
1186                 schedule_timeout(HZ);
1187         }
1188         return 0;
1189 }
1190
1191 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1192                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1193 {
1194         struct nvme_ns *ns;
1195         struct gendisk *disk;
1196         int lbaf;
1197
1198         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1199                 return NULL;
1200
1201         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1202         if (!ns)
1203                 return NULL;
1204         ns->queue = blk_alloc_queue(GFP_KERNEL);
1205         if (!ns->queue)
1206                 goto out_free_ns;
1207         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1208                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1209         blk_queue_make_request(ns->queue, nvme_make_request);
1210         ns->dev = dev;
1211         ns->queue->queuedata = ns;
1212
1213         disk = alloc_disk(NVME_MINORS);
1214         if (!disk)
1215                 goto out_free_queue;
1216         ns->ns_id = index;
1217         ns->disk = disk;
1218         lbaf = id->flbas & 0xf;
1219         ns->lba_shift = id->lbaf[lbaf].ds;
1220
1221         disk->major = nvme_major;
1222         disk->minors = NVME_MINORS;
1223         disk->first_minor = NVME_MINORS * index;
1224         disk->fops = &nvme_fops;
1225         disk->private_data = ns;
1226         disk->queue = ns->queue;
1227         disk->driverfs_dev = &dev->pci_dev->dev;
1228         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1229         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1230
1231         return ns;
1232
1233  out_free_queue:
1234         blk_cleanup_queue(ns->queue);
1235  out_free_ns:
1236         kfree(ns);
1237         return NULL;
1238 }
1239
1240 static void nvme_ns_free(struct nvme_ns *ns)
1241 {
1242         put_disk(ns->disk);
1243         blk_cleanup_queue(ns->queue);
1244         kfree(ns);
1245 }
1246
1247 static int set_queue_count(struct nvme_dev *dev, int count)
1248 {
1249         int status;
1250         u32 result;
1251         struct nvme_command c;
1252         u32 q_count = (count - 1) | ((count - 1) << 16);
1253
1254         memset(&c, 0, sizeof(c));
1255         c.features.opcode = nvme_admin_get_features;
1256         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1257         c.features.dword11 = cpu_to_le32(q_count);
1258
1259         status = nvme_submit_admin_cmd(dev, &c, &result);
1260         if (status)
1261                 return -EIO;
1262         return min(result & 0xffff, result >> 16) + 1;
1263 }
1264
1265 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1266 {
1267         int result, cpu, i, nr_io_queues;
1268
1269         nr_io_queues = num_online_cpus();
1270         result = set_queue_count(dev, nr_io_queues);
1271         if (result < 0)
1272                 return result;
1273         if (result < nr_io_queues)
1274                 nr_io_queues = result;
1275
1276         /* Deregister the admin queue's interrupt */
1277         free_irq(dev->entry[0].vector, dev->queues[0]);
1278
1279         for (i = 0; i < nr_io_queues; i++)
1280                 dev->entry[i].entry = i;
1281         for (;;) {
1282                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1283                                                                 nr_io_queues);
1284                 if (result == 0) {
1285                         break;
1286                 } else if (result > 0) {
1287                         nr_io_queues = result;
1288                         continue;
1289                 } else {
1290                         nr_io_queues = 1;
1291                         break;
1292                 }
1293         }
1294
1295         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1296         /* XXX: handle failure here */
1297
1298         cpu = cpumask_first(cpu_online_mask);
1299         for (i = 0; i < nr_io_queues; i++) {
1300                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1301                 cpu = cpumask_next(cpu, cpu_online_mask);
1302         }
1303
1304         for (i = 0; i < nr_io_queues; i++) {
1305                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1306                                                         NVME_Q_DEPTH, i);
1307                 if (!dev->queues[i + 1])
1308                         return -ENOMEM;
1309                 dev->queue_count++;
1310         }
1311
1312         return 0;
1313 }
1314
1315 static void nvme_free_queues(struct nvme_dev *dev)
1316 {
1317         int i;
1318
1319         for (i = dev->queue_count - 1; i >= 0; i--)
1320                 nvme_free_queue(dev, i);
1321 }
1322
1323 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1324 {
1325         int res, nn, i;
1326         struct nvme_ns *ns, *next;
1327         struct nvme_id_ctrl *ctrl;
1328         void *id;
1329         dma_addr_t dma_addr;
1330         struct nvme_command cid, crt;
1331
1332         res = nvme_setup_io_queues(dev);
1333         if (res)
1334                 return res;
1335
1336         /* XXX: Switch to a SG list once prp2 works */
1337         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1338                                                                 GFP_KERNEL);
1339
1340         memset(&cid, 0, sizeof(cid));
1341         cid.identify.opcode = nvme_admin_identify;
1342         cid.identify.nsid = 0;
1343         cid.identify.prp1 = cpu_to_le64(dma_addr);
1344         cid.identify.cns = cpu_to_le32(1);
1345
1346         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1347         if (res) {
1348                 res = -EIO;
1349                 goto out_free;
1350         }
1351
1352         ctrl = id;
1353         nn = le32_to_cpup(&ctrl->nn);
1354         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1355         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1356         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1357
1358         cid.identify.cns = 0;
1359         memset(&crt, 0, sizeof(crt));
1360         crt.features.opcode = nvme_admin_get_features;
1361         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1362         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1363
1364         for (i = 0; i < nn; i++) {
1365                 cid.identify.nsid = cpu_to_le32(i);
1366                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1367                 if (res)
1368                         continue;
1369
1370                 if (((struct nvme_id_ns *)id)->ncap == 0)
1371                         continue;
1372
1373                 crt.features.nsid = cpu_to_le32(i);
1374                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1375                 if (res)
1376                         continue;
1377
1378                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1379                 if (ns)
1380                         list_add_tail(&ns->list, &dev->namespaces);
1381         }
1382         list_for_each_entry(ns, &dev->namespaces, list)
1383                 add_disk(ns->disk);
1384
1385         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1386         return 0;
1387
1388  out_free:
1389         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1390                 list_del(&ns->list);
1391                 nvme_ns_free(ns);
1392         }
1393
1394         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1395         return res;
1396 }
1397
1398 static int nvme_dev_remove(struct nvme_dev *dev)
1399 {
1400         struct nvme_ns *ns, *next;
1401
1402         spin_lock(&dev_list_lock);
1403         list_del(&dev->node);
1404         spin_unlock(&dev_list_lock);
1405
1406         /* TODO: wait all I/O finished or cancel them */
1407
1408         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1409                 list_del(&ns->list);
1410                 del_gendisk(ns->disk);
1411                 nvme_ns_free(ns);
1412         }
1413
1414         nvme_free_queues(dev);
1415
1416         return 0;
1417 }
1418
1419 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1420 {
1421         struct device *dmadev = &dev->pci_dev->dev;
1422         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1423                                                 PAGE_SIZE, PAGE_SIZE, 0);
1424         if (!dev->prp_page_pool)
1425                 return -ENOMEM;
1426
1427         /* Optimisation for I/Os between 4k and 128k */
1428         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1429                                                 256, 256, 0);
1430         if (!dev->prp_small_pool) {
1431                 dma_pool_destroy(dev->prp_page_pool);
1432                 return -ENOMEM;
1433         }
1434         return 0;
1435 }
1436
1437 static void nvme_release_prp_pools(struct nvme_dev *dev)
1438 {
1439         dma_pool_destroy(dev->prp_page_pool);
1440         dma_pool_destroy(dev->prp_small_pool);
1441 }
1442
1443 /* XXX: Use an ida or something to let remove / add work correctly */
1444 static void nvme_set_instance(struct nvme_dev *dev)
1445 {
1446         static int instance;
1447         dev->instance = instance++;
1448 }
1449
1450 static void nvme_release_instance(struct nvme_dev *dev)
1451 {
1452 }
1453
1454 static int __devinit nvme_probe(struct pci_dev *pdev,
1455                                                 const struct pci_device_id *id)
1456 {
1457         int bars, result = -ENOMEM;
1458         struct nvme_dev *dev;
1459
1460         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1461         if (!dev)
1462                 return -ENOMEM;
1463         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1464                                                                 GFP_KERNEL);
1465         if (!dev->entry)
1466                 goto free;
1467         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1468                                                                 GFP_KERNEL);
1469         if (!dev->queues)
1470                 goto free;
1471
1472         if (pci_enable_device_mem(pdev))
1473                 goto free;
1474         pci_set_master(pdev);
1475         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1476         if (pci_request_selected_regions(pdev, bars, "nvme"))
1477                 goto disable;
1478
1479         INIT_LIST_HEAD(&dev->namespaces);
1480         dev->pci_dev = pdev;
1481         pci_set_drvdata(pdev, dev);
1482         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1483         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1484         nvme_set_instance(dev);
1485         dev->entry[0].vector = pdev->irq;
1486
1487         result = nvme_setup_prp_pools(dev);
1488         if (result)
1489                 goto disable_msix;
1490
1491         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1492         if (!dev->bar) {
1493                 result = -ENOMEM;
1494                 goto disable_msix;
1495         }
1496
1497         result = nvme_configure_admin_queue(dev);
1498         if (result)
1499                 goto unmap;
1500         dev->queue_count++;
1501
1502         spin_lock(&dev_list_lock);
1503         list_add(&dev->node, &dev_list);
1504         spin_unlock(&dev_list_lock);
1505
1506         result = nvme_dev_add(dev);
1507         if (result)
1508                 goto delete;
1509
1510         return 0;
1511
1512  delete:
1513         spin_lock(&dev_list_lock);
1514         list_del(&dev->node);
1515         spin_unlock(&dev_list_lock);
1516
1517         nvme_free_queues(dev);
1518  unmap:
1519         iounmap(dev->bar);
1520  disable_msix:
1521         pci_disable_msix(pdev);
1522         nvme_release_instance(dev);
1523         nvme_release_prp_pools(dev);
1524  disable:
1525         pci_disable_device(pdev);
1526         pci_release_regions(pdev);
1527  free:
1528         kfree(dev->queues);
1529         kfree(dev->entry);
1530         kfree(dev);
1531         return result;
1532 }
1533
1534 static void __devexit nvme_remove(struct pci_dev *pdev)
1535 {
1536         struct nvme_dev *dev = pci_get_drvdata(pdev);
1537         nvme_dev_remove(dev);
1538         pci_disable_msix(pdev);
1539         iounmap(dev->bar);
1540         nvme_release_instance(dev);
1541         nvme_release_prp_pools(dev);
1542         pci_disable_device(pdev);
1543         pci_release_regions(pdev);
1544         kfree(dev->queues);
1545         kfree(dev->entry);
1546         kfree(dev);
1547 }
1548
1549 /* These functions are yet to be implemented */
1550 #define nvme_error_detected NULL
1551 #define nvme_dump_registers NULL
1552 #define nvme_link_reset NULL
1553 #define nvme_slot_reset NULL
1554 #define nvme_error_resume NULL
1555 #define nvme_suspend NULL
1556 #define nvme_resume NULL
1557
1558 static struct pci_error_handlers nvme_err_handler = {
1559         .error_detected = nvme_error_detected,
1560         .mmio_enabled   = nvme_dump_registers,
1561         .link_reset     = nvme_link_reset,
1562         .slot_reset     = nvme_slot_reset,
1563         .resume         = nvme_error_resume,
1564 };
1565
1566 /* Move to pci_ids.h later */
1567 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1568
1569 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1570         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1571         { 0, }
1572 };
1573 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1574
1575 static struct pci_driver nvme_driver = {
1576         .name           = "nvme",
1577         .id_table       = nvme_id_table,
1578         .probe          = nvme_probe,
1579         .remove         = __devexit_p(nvme_remove),
1580         .suspend        = nvme_suspend,
1581         .resume         = nvme_resume,
1582         .err_handler    = &nvme_err_handler,
1583 };
1584
1585 static int __init nvme_init(void)
1586 {
1587         int result = -EBUSY;
1588
1589         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1590         if (IS_ERR(nvme_thread))
1591                 return PTR_ERR(nvme_thread);
1592
1593         nvme_major = register_blkdev(nvme_major, "nvme");
1594         if (nvme_major <= 0)
1595                 goto kill_kthread;
1596
1597         result = pci_register_driver(&nvme_driver);
1598         if (result)
1599                 goto unregister_blkdev;
1600         return 0;
1601
1602  unregister_blkdev:
1603         unregister_blkdev(nvme_major, "nvme");
1604  kill_kthread:
1605         kthread_stop(nvme_thread);
1606         return result;
1607 }
1608
1609 static void __exit nvme_exit(void)
1610 {
1611         pci_unregister_driver(&nvme_driver);
1612         unregister_blkdev(nvme_major, "nvme");
1613         kthread_stop(nvme_thread);
1614 }
1615
1616 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1617 MODULE_LICENSE("GPL");
1618 MODULE_VERSION("0.3");
1619 module_init(nvme_init);
1620 module_exit(nvme_exit);