drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/blkdev.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/kthread.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/poison.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/version.h>
  40
  41 #define NVME_Q_DEPTH 1024
  42 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  43 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  44 #define NVME_MINORS 64
  45 #define IO_TIMEOUT      (5 * HZ)
  46 #define ADMIN_TIMEOUT   (60 * HZ)
  47
  48 static int nvme_major;
  49 module_param(nvme_major, int, 0);
  50
  51 static int use_threaded_interrupts;
  52 module_param(use_threaded_interrupts, int, 0);
  53
  54 static DEFINE_SPINLOCK(dev_list_lock);
  55 static LIST_HEAD(dev_list);
  56 static struct task_struct *nvme_thread;
  57
  58 /*
  59  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  60  */
  61 struct nvme_dev {
  62         struct list_head node;
  63         struct nvme_queue **queues;
  64         u32 __iomem *dbs;
  65         struct pci_dev *pci_dev;
  66         struct dma_pool *prp_page_pool;
  67         struct dma_pool *prp_small_pool;
  68         int instance;
  69         int queue_count;
  70         u32 ctrl_config;
  71         struct msix_entry *entry;
  72         struct nvme_bar __iomem *bar;
  73         struct list_head namespaces;
  74         char serial[20];
  75         char model[40];
  76         char firmware_rev[8];
  77 };
  78
  79 /*
  80  * An NVM Express namespace is equivalent to a SCSI LUN
  81  */
  82 struct nvme_ns {
  83         struct list_head list;
  84
  85         struct nvme_dev *dev;
  86         struct request_queue *queue;
  87         struct gendisk *disk;
  88
  89         int ns_id;
  90         int lba_shift;
  91 };
  92
  93 /*
  94  * An NVM Express queue.  Each device has at least two (one for admin
  95  * commands and one for I/O commands).
  96  */
  97 struct nvme_queue {
  98         struct device *q_dmadev;
  99         struct nvme_dev *dev;
 100         spinlock_t q_lock;
 101         struct nvme_command *sq_cmds;
 102         volatile struct nvme_completion *cqes;
 103         dma_addr_t sq_dma_addr;
 104         dma_addr_t cq_dma_addr;
 105         wait_queue_head_t sq_full;
 106         wait_queue_t sq_cong_wait;
 107         struct bio_list sq_cong;
 108         u32 __iomem *q_db;
 109         u16 q_depth;
 110         u16 cq_vector;
 111         u16 sq_head;
 112         u16 sq_tail;
 113         u16 cq_head;
 114         u16 cq_phase;
 115         unsigned long cmdid_data[];
 116 };
 117
 118 /*
 119  * Check we didin't inadvertently grow the command struct
 120  */
 121 static inline void _nvme_check_size(void)
 122 {
 123         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 124         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 125         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 126         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 130         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 131         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 132 }
 133
 134 struct nvme_cmd_info {
 135         unsigned long ctx;
 136         unsigned long timeout;
 137 };
 138
 139 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 140 {
 141         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 142 }
 143
 144 /**
 145  * alloc_cmdid - Allocate a Command ID
 146  * @param nvmeq The queue that will be used for this command
 147  * @param ctx A pointer that will be passed to the handler
 148  * @param handler The ID of the handler to call
 149  *
 150  * Allocate a Command ID for a queue.  The data passed in will
 151  * be passed to the completion handler.  This is implemented by using
 152  * the bottom two bits of the ctx pointer to store the handler ID.
 153  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 154  * We can change this if it becomes a problem.
 155  */
 156 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 157                                                         unsigned timeout)
 158 {
 159         int depth = nvmeq->q_depth;
 160         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 161         int cmdid;
 162
 163         BUG_ON((unsigned long)ctx & 3);
 164
 165         do {
 166                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 167                 if (cmdid >= depth)
 168                         return -EBUSY;
 169         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 170
 171         info[cmdid].ctx = (unsigned long)ctx | handler;
 172         info[cmdid].timeout = jiffies + timeout;
 173         return cmdid;
 174 }
 175
 176 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 177                                                 int handler, unsigned timeout)
 178 {
 179         int cmdid;
 180         wait_event_killable(nvmeq->sq_full,
 181                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 182         return (cmdid < 0) ? -EINTR : cmdid;
 183 }
 184
 185 /* If you need more than four handlers, you'll need to change how
 186  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 187  * CMD_CTX value instead, if that works for your situation.
 188  */
 189 enum {
 190         sync_completion_id = 0,
 191         bio_completion_id,
 192 };
 193
 194 /* Special values must be a multiple of 4, and less than 0x1000 */
 195 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 196 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 197 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 198 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 199 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 200
 201 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 202 {
 203         unsigned long data;
 204         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 205
 206         if (cmdid >= nvmeq->q_depth)
 207                 return CMD_CTX_INVALID;
 208         data = info[cmdid].ctx;
 209         info[cmdid].ctx = CMD_CTX_COMPLETED;
 210         clear_bit(cmdid, nvmeq->cmdid_data);
 211         wake_up(&nvmeq->sq_full);
 212         return data;
 213 }
 214
 215 static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid)
 216 {
 217         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 218         info[cmdid].ctx = CMD_CTX_CANCELLED;
 219 }
 220
 221 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 222 {
 223         int qid, cpu = get_cpu();
 224         if (cpu < ns->dev->queue_count)
 225                 qid = cpu + 1;
 226         else
 227                 qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1;
 228         return ns->dev->queues[qid];
 229 }
 230
 231 static void put_nvmeq(struct nvme_queue *nvmeq)
 232 {
 233         put_cpu();
 234 }
 235
 236 /**
 237  * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
 238  * @nvmeq: The queue to use
 239  * @cmd: The command to send
 240  *
 241  * Safe to use from interrupt context
 242  */
 243 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 244 {
 245         unsigned long flags;
 246         u16 tail;
 247         /* XXX: Need to check tail isn't going to overrun head */
 248         spin_lock_irqsave(&nvmeq->q_lock, flags);
 249         tail = nvmeq->sq_tail;
 250         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 251         if (++tail == nvmeq->q_depth)
 252                 tail = 0;
 253         writel(tail, nvmeq->q_db);
 254         nvmeq->sq_tail = tail;
 255         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 256
 257         return 0;
 258 }
 259
 260 struct nvme_prps {
 261         int npages;
 262         dma_addr_t first_dma;
 263         __le64 *list[0];
 264 };
 265
 266 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 267 {
 268         const int last_prp = PAGE_SIZE / 8 - 1;
 269         int i;
 270         dma_addr_t prp_dma;
 271
 272         if (!prps)
 273                 return;
 274
 275         prp_dma = prps->first_dma;
 276
 277         if (prps->npages == 0)
 278                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 279         for (i = 0; i < prps->npages; i++) {
 280                 __le64 *prp_list = prps->list[i];
 281                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 282                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 283                 prp_dma = next_prp_dma;
 284         }
 285         kfree(prps);
 286 }
 287
 288 struct nvme_bio {
 289         struct bio *bio;
 290         int nents;
 291         struct nvme_prps *prps;
 292         struct scatterlist sg[0];
 293 };
 294
 295 /* XXX: use a mempool */
 296 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 297 {
 298         return kzalloc(sizeof(struct nvme_bio) +
 299                         sizeof(struct scatterlist) * nseg, gfp);
 300 }
 301
 302 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 303 {
 304         nvme_free_prps(nvmeq->dev, nbio->prps);
 305         kfree(nbio);
 306 }
 307
 308 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 309                                                 struct nvme_completion *cqe)
 310 {
 311         struct nvme_bio *nbio = ctx;
 312         struct bio *bio = nbio->bio;
 313         u16 status = le16_to_cpup(&cqe->status) >> 1;
 314
 315         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 316                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 317         free_nbio(nvmeq, nbio);
 318         bio_endio(bio, status ? -EIO : 0);
 319 }
 320
 321 /* length is in bytes */
 322 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 323                                         struct nvme_common_command *cmd,
 324                                         struct scatterlist *sg, int length)
 325 {
 326         struct dma_pool *pool;
 327         int dma_len = sg_dma_len(sg);
 328         u64 dma_addr = sg_dma_address(sg);
 329         int offset = offset_in_page(dma_addr);
 330         __le64 *prp_list;
 331         dma_addr_t prp_dma;
 332         int nprps, npages, i, prp_page;
 333         struct nvme_prps *prps = NULL;
 334
 335         cmd->prp1 = cpu_to_le64(dma_addr);
 336         length -= (PAGE_SIZE - offset);
 337         if (length <= 0)
 338                 return prps;
 339
 340         dma_len -= (PAGE_SIZE - offset);
 341         if (dma_len) {
 342                 dma_addr += (PAGE_SIZE - offset);
 343         } else {
 344                 sg = sg_next(sg);
 345                 dma_addr = sg_dma_address(sg);
 346                 dma_len = sg_dma_len(sg);
 347         }
 348
 349         if (length <= PAGE_SIZE) {
 350                 cmd->prp2 = cpu_to_le64(dma_addr);
 351                 return prps;
 352         }
 353
 354         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 355         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 356         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC);
 357         prp_page = 0;
 358         if (nprps <= (256 / 8)) {
 359                 pool = dev->prp_small_pool;
 360                 prps->npages = 0;
 361         } else {
 362                 pool = dev->prp_page_pool;
 363                 prps->npages = npages;
 364         }
 365
 366         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 367         prps->list[prp_page++] = prp_list;
 368         prps->first_dma = prp_dma;
 369         cmd->prp2 = cpu_to_le64(prp_dma);
 370         i = 0;
 371         for (;;) {
 372                 if (i == PAGE_SIZE / 8 - 1) {
 373                         __le64 *old_prp_list = prp_list;
 374                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 375                         prps->list[prp_page++] = prp_list;
 376                         old_prp_list[i] = cpu_to_le64(prp_dma);
 377                         i = 0;
 378                 }
 379                 prp_list[i++] = cpu_to_le64(dma_addr);
 380                 dma_len -= PAGE_SIZE;
 381                 dma_addr += PAGE_SIZE;
 382                 length -= PAGE_SIZE;
 383                 if (length <= 0)
 384                         break;
 385                 if (dma_len > 0)
 386                         continue;
 387                 BUG_ON(dma_len < 0);
 388                 sg = sg_next(sg);
 389                 dma_addr = sg_dma_address(sg);
 390                 dma_len = sg_dma_len(sg);
 391         }
 392
 393         return prps;
 394 }
 395
 396 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 397                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 398 {
 399         struct bio_vec *bvec, *bvprv = NULL;
 400         struct scatterlist *sg = NULL;
 401         int i, nsegs = 0;
 402
 403         sg_init_table(nbio->sg, psegs);
 404         bio_for_each_segment(bvec, bio, i) {
 405                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 406                         sg->length += bvec->bv_len;
 407                 } else {
 408                         /* Check bvprv && offset == 0 */
 409                         sg = sg ? sg + 1 : nbio->sg;
 410                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 411                                                         bvec->bv_offset);
 412                         nsegs++;
 413                 }
 414                 bvprv = bvec;
 415         }
 416         nbio->nents = nsegs;
 417         sg_mark_end(sg);
 418         return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir);
 419 }
 420
 421 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 422                                                                 int cmdid)
 423 {
 424         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 425
 426         memset(cmnd, 0, sizeof(*cmnd));
 427         cmnd->common.opcode = nvme_cmd_flush;
 428         cmnd->common.command_id = cmdid;
 429         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 430
 431         if (++nvmeq->sq_tail == nvmeq->q_depth)
 432                 nvmeq->sq_tail = 0;
 433         writel(nvmeq->sq_tail, nvmeq->q_db);
 434
 435         return 0;
 436 }
 437
 438 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 439 {
 440         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 441                                                 sync_completion_id, IO_TIMEOUT);
 442         if (unlikely(cmdid < 0))
 443                 return cmdid;
 444
 445         return nvme_submit_flush(nvmeq, ns, cmdid);
 446 }
 447
 448 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 449                                                                 struct bio *bio)
 450 {
 451         struct nvme_command *cmnd;
 452         struct nvme_bio *nbio;
 453         enum dma_data_direction dma_dir;
 454         int cmdid, result = -ENOMEM;
 455         u16 control;
 456         u32 dsmgmt;
 457         int psegs = bio_phys_segments(ns->queue, bio);
 458
 459         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 460                 result = nvme_submit_flush_data(nvmeq, ns);
 461                 if (result)
 462                         return result;
 463         }
 464
 465         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 466         if (!nbio)
 467                 goto nomem;
 468         nbio->bio = bio;
 469
 470         result = -EBUSY;
 471         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 472         if (unlikely(cmdid < 0))
 473                 goto free_nbio;
 474
 475         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 476                 return nvme_submit_flush(nvmeq, ns, cmdid);
 477
 478         control = 0;
 479         if (bio->bi_rw & REQ_FUA)
 480                 control |= NVME_RW_FUA;
 481         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 482                 control |= NVME_RW_LR;
 483
 484         dsmgmt = 0;
 485         if (bio->bi_rw & REQ_RAHEAD)
 486                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 487
 488         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 489
 490         memset(cmnd, 0, sizeof(*cmnd));
 491         if (bio_data_dir(bio)) {
 492                 cmnd->rw.opcode = nvme_cmd_write;
 493                 dma_dir = DMA_TO_DEVICE;
 494         } else {
 495                 cmnd->rw.opcode = nvme_cmd_read;
 496                 dma_dir = DMA_FROM_DEVICE;
 497         }
 498
 499         result = -ENOMEM;
 500         if (nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs) == 0)
 501                 goto free_nbio;
 502
 503         cmnd->rw.command_id = cmdid;
 504         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 505         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 506                                                                 bio->bi_size);
 507         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 508         cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1);
 509         cmnd->rw.control = cpu_to_le16(control);
 510         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 511
 512         if (++nvmeq->sq_tail == nvmeq->q_depth)
 513                 nvmeq->sq_tail = 0;
 514         writel(nvmeq->sq_tail, nvmeq->q_db);
 515
 516         return 0;
 517
 518  free_nbio:
 519         free_nbio(nvmeq, nbio);
 520  nomem:
 521         return result;
 522 }
 523
 524 /*
 525  * NB: return value of non-zero would mean that we were a stacking driver.
 526  * make_request must always succeed.
 527  */
 528 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 529 {
 530         struct nvme_ns *ns = q->queuedata;
 531         struct nvme_queue *nvmeq = get_nvmeq(ns);
 532         int result = -EBUSY;
 533
 534         spin_lock_irq(&nvmeq->q_lock);
 535         if (bio_list_empty(&nvmeq->sq_cong))
 536                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 537         if (unlikely(result)) {
 538                 if (bio_list_empty(&nvmeq->sq_cong))
 539                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 540                 bio_list_add(&nvmeq->sq_cong, bio);
 541         }
 542
 543         spin_unlock_irq(&nvmeq->q_lock);
 544         put_nvmeq(nvmeq);
 545
 546         return 0;
 547 }
 548
 549 struct sync_cmd_info {
 550         struct task_struct *task;
 551         u32 result;
 552         int status;
 553 };
 554
 555 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 556                                                 struct nvme_completion *cqe)
 557 {
 558         struct sync_cmd_info *cmdinfo = ctx;
 559         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 560                 return;
 561         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 562                 return;
 563         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 564                 dev_warn(nvmeq->q_dmadev,
 565                                 "completed id %d twice on queue %d\n",
 566                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 567                 return;
 568         }
 569         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 570                 dev_warn(nvmeq->q_dmadev,
 571                                 "invalid id %d completed on queue %d\n",
 572                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 573                 return;
 574         }
 575         cmdinfo->result = le32_to_cpup(&cqe->result);
 576         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 577         wake_up_process(cmdinfo->task);
 578 }
 579
 580 typedef void (*completion_fn)(struct nvme_queue *, void *,
 581                                                 struct nvme_completion *);
 582
 583 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 584 {
 585         u16 head, phase;
 586
 587         static const completion_fn completions[4] = {
 588                 [sync_completion_id] = sync_completion,
 589                 [bio_completion_id]  = bio_completion,
 590         };
 591
 592         head = nvmeq->cq_head;
 593         phase = nvmeq->cq_phase;
 594
 595         for (;;) {
 596                 unsigned long data;
 597                 void *ptr;
 598                 unsigned char handler;
 599                 struct nvme_completion cqe = nvmeq->cqes[head];
 600                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 601                         break;
 602                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 603                 if (++head == nvmeq->q_depth) {
 604                         head = 0;
 605                         phase = !phase;
 606                 }
 607
 608                 data = free_cmdid(nvmeq, cqe.command_id);
 609                 handler = data & 3;
 610                 ptr = (void *)(data & ~3UL);
 611                 completions[handler](nvmeq, ptr, &cqe);
 612         }
 613
 614         /* If the controller ignores the cq head doorbell and continuously
 615          * writes to the queue, it is theoretically possible to wrap around
 616          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 617          * requires that 0.1% of your interrupts are handled, so this isn't
 618          * a big problem.
 619          */
 620         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 621                 return IRQ_NONE;
 622
 623         writel(head, nvmeq->q_db + 1);
 624         nvmeq->cq_head = head;
 625         nvmeq->cq_phase = phase;
 626
 627         return IRQ_HANDLED;
 628 }
 629
 630 static irqreturn_t nvme_irq(int irq, void *data)
 631 {
 632         irqreturn_t result;
 633         struct nvme_queue *nvmeq = data;
 634         spin_lock(&nvmeq->q_lock);
 635         result = nvme_process_cq(nvmeq);
 636         spin_unlock(&nvmeq->q_lock);
 637         return result;
 638 }
 639
 640 static irqreturn_t nvme_irq_check(int irq, void *data)
 641 {
 642         struct nvme_queue *nvmeq = data;
 643         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 644         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 645                 return IRQ_NONE;
 646         return IRQ_WAKE_THREAD;
 647 }
 648
 649 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 650 {
 651         spin_lock_irq(&nvmeq->q_lock);
 652         cancel_cmdid_data(nvmeq, cmdid);
 653         spin_unlock_irq(&nvmeq->q_lock);
 654 }
 655
 656 /*
 657  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 658  * if the result is positive, it's an NVM Express status code
 659  */
 660 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 661                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 662 {
 663         int cmdid;
 664         struct sync_cmd_info cmdinfo;
 665
 666         cmdinfo.task = current;
 667         cmdinfo.status = -EINTR;
 668
 669         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 670                                                                 timeout);
 671         if (cmdid < 0)
 672                 return cmdid;
 673         cmd->common.command_id = cmdid;
 674
 675         set_current_state(TASK_KILLABLE);
 676         nvme_submit_cmd(nvmeq, cmd);
 677         schedule();
 678
 679         if (cmdinfo.status == -EINTR) {
 680                 nvme_abort_command(nvmeq, cmdid);
 681                 return -EINTR;
 682         }
 683
 684         if (result)
 685                 *result = cmdinfo.result;
 686
 687         return cmdinfo.status;
 688 }
 689
 690 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 691                                                                 u32 *result)
 692 {
 693         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 694 }
 695
 696 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 697 {
 698         int status;
 699         struct nvme_command c;
 700
 701         memset(&c, 0, sizeof(c));
 702         c.delete_queue.opcode = opcode;
 703         c.delete_queue.qid = cpu_to_le16(id);
 704
 705         status = nvme_submit_admin_cmd(dev, &c, NULL);
 706         if (status)
 707                 return -EIO;
 708         return 0;
 709 }
 710
 711 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 712                                                 struct nvme_queue *nvmeq)
 713 {
 714         int status;
 715         struct nvme_command c;
 716         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 717
 718         memset(&c, 0, sizeof(c));
 719         c.create_cq.opcode = nvme_admin_create_cq;
 720         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 721         c.create_cq.cqid = cpu_to_le16(qid);
 722         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 723         c.create_cq.cq_flags = cpu_to_le16(flags);
 724         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 725
 726         status = nvme_submit_admin_cmd(dev, &c, NULL);
 727         if (status)
 728                 return -EIO;
 729         return 0;
 730 }
 731
 732 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 733                                                 struct nvme_queue *nvmeq)
 734 {
 735         int status;
 736         struct nvme_command c;
 737         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 738
 739         memset(&c, 0, sizeof(c));
 740         c.create_sq.opcode = nvme_admin_create_sq;
 741         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 742         c.create_sq.sqid = cpu_to_le16(qid);
 743         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 744         c.create_sq.sq_flags = cpu_to_le16(flags);
 745         c.create_sq.cqid = cpu_to_le16(qid);
 746
 747         status = nvme_submit_admin_cmd(dev, &c, NULL);
 748         if (status)
 749                 return -EIO;
 750         return 0;
 751 }
 752
 753 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 754 {
 755         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 756 }
 757
 758 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 759 {
 760         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 761 }
 762
 763 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 764 {
 765         struct nvme_queue *nvmeq = dev->queues[qid];
 766
 767         free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq);
 768
 769         /* Don't tell the adapter to delete the admin queue */
 770         if (qid) {
 771                 adapter_delete_sq(dev, qid);
 772                 adapter_delete_cq(dev, qid);
 773         }
 774
 775         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 776                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 777         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 778                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 779         kfree(nvmeq);
 780 }
 781
 782 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 783                                                         int depth, int vector)
 784 {
 785         struct device *dmadev = &dev->pci_dev->dev;
 786         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 787         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 788         if (!nvmeq)
 789                 return NULL;
 790
 791         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 792                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 793         if (!nvmeq->cqes)
 794                 goto free_nvmeq;
 795         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 796
 797         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 798                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 799         if (!nvmeq->sq_cmds)
 800                 goto free_cqdma;
 801
 802         nvmeq->q_dmadev = dmadev;
 803         nvmeq->dev = dev;
 804         spin_lock_init(&nvmeq->q_lock);
 805         nvmeq->cq_head = 0;
 806         nvmeq->cq_phase = 1;
 807         init_waitqueue_head(&nvmeq->sq_full);
 808         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 809         bio_list_init(&nvmeq->sq_cong);
 810         nvmeq->q_db = &dev->dbs[qid * 2];
 811         nvmeq->q_depth = depth;
 812         nvmeq->cq_vector = vector;
 813
 814         return nvmeq;
 815
 816  free_cqdma:
 817         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 818                                                         nvmeq->cq_dma_addr);
 819  free_nvmeq:
 820         kfree(nvmeq);
 821         return NULL;
 822 }
 823
 824 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 825                                                         const char *name)
 826 {
 827         if (use_threaded_interrupts)
 828                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 829                                         nvme_irq_check, nvme_irq,
 830                                         IRQF_DISABLED | IRQF_SHARED,
 831                                         name, nvmeq);
 832         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 833                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 834 }
 835
 836 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 837                                         int qid, int cq_size, int vector)
 838 {
 839         int result;
 840         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 841
 842         if (!nvmeq)
 843                 return NULL;
 844
 845         result = adapter_alloc_cq(dev, qid, nvmeq);
 846         if (result < 0)
 847                 goto free_nvmeq;
 848
 849         result = adapter_alloc_sq(dev, qid, nvmeq);
 850         if (result < 0)
 851                 goto release_cq;
 852
 853         result = queue_request_irq(dev, nvmeq, "nvme");
 854         if (result < 0)
 855                 goto release_sq;
 856
 857         return nvmeq;
 858
 859  release_sq:
 860         adapter_delete_sq(dev, qid);
 861  release_cq:
 862         adapter_delete_cq(dev, qid);
 863  free_nvmeq:
 864         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 865                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 866         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 867                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 868         kfree(nvmeq);
 869         return NULL;
 870 }
 871
 872 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 873 {
 874         int result;
 875         u32 aqa;
 876         struct nvme_queue *nvmeq;
 877
 878         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 879
 880         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 881         if (!nvmeq)
 882                 return -ENOMEM;
 883
 884         aqa = nvmeq->q_depth - 1;
 885         aqa |= aqa << 16;
 886
 887         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 888         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 889         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 890
 891         writel(0, &dev->bar->cc);
 892         writel(aqa, &dev->bar->aqa);
 893         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 894         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 895         writel(dev->ctrl_config, &dev->bar->cc);
 896
 897         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 898                 msleep(100);
 899                 if (fatal_signal_pending(current))
 900                         return -EINTR;
 901         }
 902
 903         result = queue_request_irq(dev, nvmeq, "nvme admin");
 904         dev->queues[0] = nvmeq;
 905         return result;
 906 }
 907
 908 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 909                                 unsigned long addr, unsigned length,
 910                                 struct scatterlist **sgp)
 911 {
 912         int i, err, count, nents, offset;
 913         struct scatterlist *sg;
 914         struct page **pages;
 915
 916         if (addr & 3)
 917                 return -EINVAL;
 918         if (!length)
 919                 return -EINVAL;
 920
 921         offset = offset_in_page(addr);
 922         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 923         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 924
 925         err = get_user_pages_fast(addr, count, 1, pages);
 926         if (err < count) {
 927                 count = err;
 928                 err = -EFAULT;
 929                 goto put_pages;
 930         }
 931
 932         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 933         sg_init_table(sg, count);
 934         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 935         length -= (PAGE_SIZE - offset);
 936         for (i = 1; i < count; i++) {
 937                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
 938                 length -= PAGE_SIZE;
 939         }
 940
 941         err = -ENOMEM;
 942         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
 943                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 944         if (!nents)
 945                 goto put_pages;
 946
 947         kfree(pages);
 948         *sgp = sg;
 949         return nents;
 950
 951  put_pages:
 952         for (i = 0; i < count; i++)
 953                 put_page(pages[i]);
 954         kfree(pages);
 955         return err;
 956 }
 957
 958 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 959                                 unsigned long addr, int length,
 960                                 struct scatterlist *sg, int nents)
 961 {
 962         int i, count;
 963
 964         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
 965         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
 966
 967         for (i = 0; i < count; i++)
 968                 put_page(sg_page(&sg[i]));
 969 }
 970
 971 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
 972                                         unsigned long addr, unsigned length,
 973                                         struct nvme_command *cmd)
 974 {
 975         int err, nents;
 976         struct scatterlist *sg;
 977         struct nvme_prps *prps;
 978
 979         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
 980         if (nents < 0)
 981                 return nents;
 982         prps = nvme_setup_prps(dev, &cmd->common, sg, length);
 983         err = nvme_submit_admin_cmd(dev, cmd, NULL);
 984         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
 985         nvme_free_prps(dev, prps);
 986         return err ? -EIO : 0;
 987 }
 988
 989 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
 990 {
 991         struct nvme_command c;
 992
 993         memset(&c, 0, sizeof(c));
 994         c.identify.opcode = nvme_admin_identify;
 995         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
 996         c.identify.cns = cpu_to_le32(cns);
 997
 998         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
 999 }
1000
1001 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1002 {
1003         struct nvme_command c;
1004
1005         memset(&c, 0, sizeof(c));
1006         c.features.opcode = nvme_admin_get_features;
1007         c.features.nsid = cpu_to_le32(ns->ns_id);
1008         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1009
1010         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1011 }
1012
1013 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1014 {
1015         struct nvme_dev *dev = ns->dev;
1016         struct nvme_queue *nvmeq;
1017         struct nvme_user_io io;
1018         struct nvme_command c;
1019         unsigned length;
1020         u32 result;
1021         int nents, status;
1022         struct scatterlist *sg;
1023         struct nvme_prps *prps;
1024
1025         if (copy_from_user(&io, uio, sizeof(io)))
1026                 return -EFAULT;
1027         length = io.nblocks << io.block_shift;
1028         nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg);
1029         if (nents < 0)
1030                 return nents;
1031
1032         memset(&c, 0, sizeof(c));
1033         c.rw.opcode = io.opcode;
1034         c.rw.flags = io.flags;
1035         c.rw.nsid = cpu_to_le32(io.nsid);
1036         c.rw.slba = cpu_to_le64(io.slba);
1037         c.rw.length = cpu_to_le16(io.nblocks - 1);
1038         c.rw.control = cpu_to_le16(io.control);
1039         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1040         c.rw.reftag = cpu_to_le32(io.reftag);   /* XXX: endian? */
1041         c.rw.apptag = cpu_to_le16(io.apptag);
1042         c.rw.appmask = cpu_to_le16(io.appmask);
1043         /* XXX: metadata */
1044         prps = nvme_setup_prps(dev, &c.common, sg, length);
1045
1046         nvmeq = get_nvmeq(ns);
1047         /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1048          * disabled.  We may be preempted at any point, and be rescheduled
1049          * to a different CPU.  That will cause cacheline bouncing, but no
1050          * additional races since q_lock already protects against other CPUs.
1051          */
1052         put_nvmeq(nvmeq);
1053         status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT);
1054
1055         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1056         nvme_free_prps(dev, prps);
1057         put_user(result, &uio->result);
1058         return status;
1059 }
1060
1061 static int nvme_download_firmware(struct nvme_ns *ns,
1062                                                 struct nvme_dlfw __user *udlfw)
1063 {
1064         struct nvme_dev *dev = ns->dev;
1065         struct nvme_dlfw dlfw;
1066         struct nvme_command c;
1067         int nents, status;
1068         struct scatterlist *sg;
1069         struct nvme_prps *prps;
1070
1071         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1072                 return -EFAULT;
1073         if (dlfw.length >= (1 << 30))
1074                 return -EINVAL;
1075
1076         nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg);
1077         if (nents < 0)
1078                 return nents;
1079
1080         memset(&c, 0, sizeof(c));
1081         c.dlfw.opcode = nvme_admin_download_fw;
1082         c.dlfw.numd = cpu_to_le32(dlfw.length);
1083         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1084         prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4);
1085
1086         status = nvme_submit_admin_cmd(dev, &c, NULL);
1087         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1088         nvme_free_prps(dev, prps);
1089         return status;
1090 }
1091
1092 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1093 {
1094         struct nvme_dev *dev = ns->dev;
1095         struct nvme_command c;
1096
1097         memset(&c, 0, sizeof(c));
1098         c.common.opcode = nvme_admin_activate_fw;
1099         c.common.rsvd10[0] = cpu_to_le32(arg);
1100
1101         return nvme_submit_admin_cmd(dev, &c, NULL);
1102 }
1103
1104 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1105                                                         unsigned long arg)
1106 {
1107         struct nvme_ns *ns = bdev->bd_disk->private_data;
1108
1109         switch (cmd) {
1110         case NVME_IOCTL_IDENTIFY_NS:
1111                 return nvme_identify(ns, arg, 0);
1112         case NVME_IOCTL_IDENTIFY_CTRL:
1113                 return nvme_identify(ns, arg, 1);
1114         case NVME_IOCTL_GET_RANGE_TYPE:
1115                 return nvme_get_range_type(ns, arg);
1116         case NVME_IOCTL_SUBMIT_IO:
1117                 return nvme_submit_io(ns, (void __user *)arg);
1118         case NVME_IOCTL_DOWNLOAD_FW:
1119                 return nvme_download_firmware(ns, (void __user *)arg);
1120         case NVME_IOCTL_ACTIVATE_FW:
1121                 return nvme_activate_firmware(ns, arg);
1122         default:
1123                 return -ENOTTY;
1124         }
1125 }
1126
1127 static const struct block_device_operations nvme_fops = {
1128         .owner          = THIS_MODULE,
1129         .ioctl          = nvme_ioctl,
1130 };
1131
1132 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1133 {
1134         while (bio_list_peek(&nvmeq->sq_cong)) {
1135                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1136                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1137                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1138                         bio_list_add_head(&nvmeq->sq_cong, bio);
1139                         break;
1140                 }
1141         }
1142 }
1143
1144 static int nvme_kthread(void *data)
1145 {
1146         struct nvme_dev *dev;
1147
1148         while (!kthread_should_stop()) {
1149                 __set_current_state(TASK_RUNNING);
1150                 spin_lock(&dev_list_lock);
1151                 list_for_each_entry(dev, &dev_list, node) {
1152                         int i;
1153                         for (i = 0; i < dev->queue_count; i++) {
1154                                 struct nvme_queue *nvmeq = dev->queues[i];
1155                                 if (!nvmeq)
1156                                         continue;
1157                                 spin_lock_irq(&nvmeq->q_lock);
1158                                 if (nvme_process_cq(nvmeq))
1159                                         printk("process_cq did something\n");
1160                                 nvme_resubmit_bios(nvmeq);
1161                                 spin_unlock_irq(&nvmeq->q_lock);
1162                         }
1163                 }
1164                 spin_unlock(&dev_list_lock);
1165                 set_current_state(TASK_INTERRUPTIBLE);
1166                 schedule_timeout(HZ);
1167         }
1168         return 0;
1169 }
1170
1171 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index,
1172                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1173 {
1174         struct nvme_ns *ns;
1175         struct gendisk *disk;
1176         int lbaf;
1177
1178         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1179                 return NULL;
1180
1181         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1182         if (!ns)
1183                 return NULL;
1184         ns->queue = blk_alloc_queue(GFP_KERNEL);
1185         if (!ns->queue)
1186                 goto out_free_ns;
1187         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1188                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1189         blk_queue_make_request(ns->queue, nvme_make_request);
1190         ns->dev = dev;
1191         ns->queue->queuedata = ns;
1192
1193         disk = alloc_disk(NVME_MINORS);
1194         if (!disk)
1195                 goto out_free_queue;
1196         ns->ns_id = index;
1197         ns->disk = disk;
1198         lbaf = id->flbas & 0xf;
1199         ns->lba_shift = id->lbaf[lbaf].ds;
1200
1201         disk->major = nvme_major;
1202         disk->minors = NVME_MINORS;
1203         disk->first_minor = NVME_MINORS * index;
1204         disk->fops = &nvme_fops;
1205         disk->private_data = ns;
1206         disk->queue = ns->queue;
1207         disk->driverfs_dev = &dev->pci_dev->dev;
1208         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index);
1209         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1210
1211         return ns;
1212
1213  out_free_queue:
1214         blk_cleanup_queue(ns->queue);
1215  out_free_ns:
1216         kfree(ns);
1217         return NULL;
1218 }
1219
1220 static void nvme_ns_free(struct nvme_ns *ns)
1221 {
1222         put_disk(ns->disk);
1223         blk_cleanup_queue(ns->queue);
1224         kfree(ns);
1225 }
1226
1227 static int set_queue_count(struct nvme_dev *dev, int count)
1228 {
1229         int status;
1230         u32 result;
1231         struct nvme_command c;
1232         u32 q_count = (count - 1) | ((count - 1) << 16);
1233
1234         memset(&c, 0, sizeof(c));
1235         c.features.opcode = nvme_admin_get_features;
1236         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1237         c.features.dword11 = cpu_to_le32(q_count);
1238
1239         status = nvme_submit_admin_cmd(dev, &c, &result);
1240         if (status)
1241                 return -EIO;
1242         return min(result & 0xffff, result >> 16) + 1;
1243 }
1244
1245 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1246 {
1247         int result, cpu, i, nr_io_queues;
1248
1249         nr_io_queues = num_online_cpus();
1250         result = set_queue_count(dev, nr_io_queues);
1251         if (result < 0)
1252                 return result;
1253         if (result < nr_io_queues)
1254                 nr_io_queues = result;
1255
1256         /* Deregister the admin queue's interrupt */
1257         free_irq(dev->entry[0].vector, dev->queues[0]);
1258
1259         for (i = 0; i < nr_io_queues; i++)
1260                 dev->entry[i].entry = i;
1261         for (;;) {
1262                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1263                                                                 nr_io_queues);
1264                 if (result == 0) {
1265                         break;
1266                 } else if (result > 0) {
1267                         nr_io_queues = result;
1268                         continue;
1269                 } else {
1270                         nr_io_queues = 1;
1271                         break;
1272                 }
1273         }
1274
1275         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1276         /* XXX: handle failure here */
1277
1278         cpu = cpumask_first(cpu_online_mask);
1279         for (i = 0; i < nr_io_queues; i++) {
1280                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1281                 cpu = cpumask_next(cpu, cpu_online_mask);
1282         }
1283
1284         for (i = 0; i < nr_io_queues; i++) {
1285                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1286                                                         NVME_Q_DEPTH, i);
1287                 if (!dev->queues[i + 1])
1288                         return -ENOMEM;
1289                 dev->queue_count++;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static void nvme_free_queues(struct nvme_dev *dev)
1296 {
1297         int i;
1298
1299         for (i = dev->queue_count - 1; i >= 0; i--)
1300                 nvme_free_queue(dev, i);
1301 }
1302
1303 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1304 {
1305         int res, nn, i;
1306         struct nvme_ns *ns, *next;
1307         struct nvme_id_ctrl *ctrl;
1308         void *id;
1309         dma_addr_t dma_addr;
1310         struct nvme_command cid, crt;
1311
1312         res = nvme_setup_io_queues(dev);
1313         if (res)
1314                 return res;
1315
1316         /* XXX: Switch to a SG list once prp2 works */
1317         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1318                                                                 GFP_KERNEL);
1319
1320         memset(&cid, 0, sizeof(cid));
1321         cid.identify.opcode = nvme_admin_identify;
1322         cid.identify.nsid = 0;
1323         cid.identify.prp1 = cpu_to_le64(dma_addr);
1324         cid.identify.cns = cpu_to_le32(1);
1325
1326         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1327         if (res) {
1328                 res = -EIO;
1329                 goto out_free;
1330         }
1331
1332         ctrl = id;
1333         nn = le32_to_cpup(&ctrl->nn);
1334         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1335         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1336         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1337
1338         cid.identify.cns = 0;
1339         memset(&crt, 0, sizeof(crt));
1340         crt.features.opcode = nvme_admin_get_features;
1341         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1342         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1343
1344         for (i = 0; i < nn; i++) {
1345                 cid.identify.nsid = cpu_to_le32(i);
1346                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1347                 if (res)
1348                         continue;
1349
1350                 if (((struct nvme_id_ns *)id)->ncap == 0)
1351                         continue;
1352
1353                 crt.features.nsid = cpu_to_le32(i);
1354                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1355                 if (res)
1356                         continue;
1357
1358                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1359                 if (ns)
1360                         list_add_tail(&ns->list, &dev->namespaces);
1361         }
1362         list_for_each_entry(ns, &dev->namespaces, list)
1363                 add_disk(ns->disk);
1364
1365         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1366         return 0;
1367
1368  out_free:
1369         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1370                 list_del(&ns->list);
1371                 nvme_ns_free(ns);
1372         }
1373
1374         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1375         return res;
1376 }
1377
1378 static int nvme_dev_remove(struct nvme_dev *dev)
1379 {
1380         struct nvme_ns *ns, *next;
1381
1382         spin_lock(&dev_list_lock);
1383         list_del(&dev->node);
1384         spin_unlock(&dev_list_lock);
1385
1386         /* TODO: wait all I/O finished or cancel them */
1387
1388         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1389                 list_del(&ns->list);
1390                 del_gendisk(ns->disk);
1391                 nvme_ns_free(ns);
1392         }
1393
1394         nvme_free_queues(dev);
1395
1396         return 0;
1397 }
1398
1399 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1400 {
1401         struct device *dmadev = &dev->pci_dev->dev;
1402         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1403                                                 PAGE_SIZE, PAGE_SIZE, 0);
1404         if (!dev->prp_page_pool)
1405                 return -ENOMEM;
1406
1407         /* Optimisation for I/Os between 4k and 128k */
1408         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1409                                                 256, 256, 0);
1410         if (!dev->prp_small_pool) {
1411                 dma_pool_destroy(dev->prp_page_pool);
1412                 return -ENOMEM;
1413         }
1414         return 0;
1415 }
1416
1417 static void nvme_release_prp_pools(struct nvme_dev *dev)
1418 {
1419         dma_pool_destroy(dev->prp_page_pool);
1420         dma_pool_destroy(dev->prp_small_pool);
1421 }
1422
1423 /* XXX: Use an ida or something to let remove / add work correctly */
1424 static void nvme_set_instance(struct nvme_dev *dev)
1425 {
1426         static int instance;
1427         dev->instance = instance++;
1428 }
1429
1430 static void nvme_release_instance(struct nvme_dev *dev)
1431 {
1432 }
1433
1434 static int __devinit nvme_probe(struct pci_dev *pdev,
1435                                                 const struct pci_device_id *id)
1436 {
1437         int bars, result = -ENOMEM;
1438         struct nvme_dev *dev;
1439
1440         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1441         if (!dev)
1442                 return -ENOMEM;
1443         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1444                                                                 GFP_KERNEL);
1445         if (!dev->entry)
1446                 goto free;
1447         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1448                                                                 GFP_KERNEL);
1449         if (!dev->queues)
1450                 goto free;
1451
1452         if (pci_enable_device_mem(pdev))
1453                 goto free;
1454         pci_set_master(pdev);
1455         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1456         if (pci_request_selected_regions(pdev, bars, "nvme"))
1457                 goto disable;
1458
1459         INIT_LIST_HEAD(&dev->namespaces);
1460         dev->pci_dev = pdev;
1461         pci_set_drvdata(pdev, dev);
1462         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1463         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1464         nvme_set_instance(dev);
1465         dev->entry[0].vector = pdev->irq;
1466
1467         result = nvme_setup_prp_pools(dev);
1468         if (result)
1469                 goto disable_msix;
1470
1471         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1472         if (!dev->bar) {
1473                 result = -ENOMEM;
1474                 goto disable_msix;
1475         }
1476
1477         result = nvme_configure_admin_queue(dev);
1478         if (result)
1479                 goto unmap;
1480         dev->queue_count++;
1481
1482         spin_lock(&dev_list_lock);
1483         list_add(&dev->node, &dev_list);
1484         spin_unlock(&dev_list_lock);
1485
1486         result = nvme_dev_add(dev);
1487         if (result)
1488                 goto delete;
1489
1490         return 0;
1491
1492  delete:
1493         spin_lock(&dev_list_lock);
1494         list_del(&dev->node);
1495         spin_unlock(&dev_list_lock);
1496
1497         nvme_free_queues(dev);
1498  unmap:
1499         iounmap(dev->bar);
1500  disable_msix:
1501         pci_disable_msix(pdev);
1502         nvme_release_instance(dev);
1503         nvme_release_prp_pools(dev);
1504  disable:
1505         pci_disable_device(pdev);
1506         pci_release_regions(pdev);
1507  free:
1508         kfree(dev->queues);
1509         kfree(dev->entry);
1510         kfree(dev);
1511         return result;
1512 }
1513
1514 static void __devexit nvme_remove(struct pci_dev *pdev)
1515 {
1516         struct nvme_dev *dev = pci_get_drvdata(pdev);
1517         nvme_dev_remove(dev);
1518         pci_disable_msix(pdev);
1519         iounmap(dev->bar);
1520         nvme_release_instance(dev);
1521         nvme_release_prp_pools(dev);
1522         pci_disable_device(pdev);
1523         pci_release_regions(pdev);
1524         kfree(dev->queues);
1525         kfree(dev->entry);
1526         kfree(dev);
1527 }
1528
1529 /* These functions are yet to be implemented */
1530 #define nvme_error_detected NULL
1531 #define nvme_dump_registers NULL
1532 #define nvme_link_reset NULL
1533 #define nvme_slot_reset NULL
1534 #define nvme_error_resume NULL
1535 #define nvme_suspend NULL
1536 #define nvme_resume NULL
1537
1538 static struct pci_error_handlers nvme_err_handler = {
1539         .error_detected = nvme_error_detected,
1540         .mmio_enabled   = nvme_dump_registers,
1541         .link_reset     = nvme_link_reset,
1542         .slot_reset     = nvme_slot_reset,
1543         .resume         = nvme_error_resume,
1544 };
1545
1546 /* Move to pci_ids.h later */
1547 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1548
1549 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1550         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1551         { 0, }
1552 };
1553 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1554
1555 static struct pci_driver nvme_driver = {
1556         .name           = "nvme",
1557         .id_table       = nvme_id_table,
1558         .probe          = nvme_probe,
1559         .remove         = __devexit_p(nvme_remove),
1560         .suspend        = nvme_suspend,
1561         .resume         = nvme_resume,
1562         .err_handler    = &nvme_err_handler,
1563 };
1564
1565 static int __init nvme_init(void)
1566 {
1567         int result = -EBUSY;
1568
1569         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1570         if (IS_ERR(nvme_thread))
1571                 return PTR_ERR(nvme_thread);
1572
1573         nvme_major = register_blkdev(nvme_major, "nvme");
1574         if (nvme_major <= 0)
1575                 goto kill_kthread;
1576
1577         result = pci_register_driver(&nvme_driver);
1578         if (result)
1579                 goto unregister_blkdev;
1580         return 0;
1581
1582  unregister_blkdev:
1583         unregister_blkdev(nvme_major, "nvme");
1584  kill_kthread:
1585         kthread_stop(nvme_thread);
1586         return result;
1587 }
1588
1589 static void __exit nvme_exit(void)
1590 {
1591         pci_unregister_driver(&nvme_driver);
1592         unregister_blkdev(nvme_major, "nvme");
1593         kthread_stop(nvme_thread);
1594 }
1595
1596 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1597 MODULE_LICENSE("GPL");
1598 MODULE_VERSION("0.3");
1599 module_init(nvme_init);
1600 module_exit(nvme_exit);